* [dpdk-stable] [PATCH 17.11] net/mlx5: fix instruction hotspot on replenishing Rx buffer
@ 2019-04-30 20:28 Yongseok Koh
0 siblings, 0 replies; only message in thread
From: Yongseok Koh @ 2019-04-30 20:28 UTC (permalink / raw)
To: yskoh; +Cc: stable, shahafs
On replenishing Rx buffers for vectorized Rx, mbuf->buf_addr isn't needed
to be accessed as it is static and easily calculated from the mbuf address.
Accessing the mbuf content causes unnecessary load stall. non-x86
processors (mostly RISC such as ARM and Power) are more vulnerable to load
stall. For x86, reducing the number of instructions seems to matter most.
Fixes: 545b884b1da3 ("net/mlx5: fix buffer address posting in SSE Rx")
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
---
drivers/net/mlx5/mlx5_rxtx_vec.h | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.h b/drivers/net/mlx5/mlx5_rxtx_vec.h
index 750559b8d..e7367b74d 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec.h
@@ -116,7 +116,22 @@ mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n)
return;
}
for (i = 0; i < n; ++i) {
- wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
+ void *buf_addr;
+
+ /*
+ * Load the virtual address for Rx WQE. non-x86 processors
+ * (mostly RISC such as ARM and Power) are more vulnerable to
+ * load stall. For x86, reducing the number of instructions
+ * seems to matter most.
+ */
+#ifdef RTE_ARCH_X86_64
+ buf_addr = elts[i]->buf_addr;
+#else
+ buf_addr = (char *)elts[i] + sizeof(struct rte_mbuf) +
+ rte_pktmbuf_priv_size(rxq->mp);
+ assert(buf_addr == elts[i]->buf_addr);
+#endif
+ wq[i].addr = rte_cpu_to_be_64((uintptr_t)buf_addr +
RTE_PKTMBUF_HEADROOM);
/* If there's only one MR, no need to replace LKEY in WQEs. */
if (unlikely(!IS_SINGLE_MR(rxq->mr_ctrl.bh_n)))
--
2.11.0
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