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* [dpdk-dev] [PATCH 00/25] patchset for bnxt
@ 2020-09-11  1:55 Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 01/25] net/bnxt: fix port stop process and cleanup resources Ajit Khaparde
                   ` (25 more replies)
  0 siblings, 26 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev

Some fixes and enhancements in the PMD and TruFlow layers

Kishore Padmanabha (14):
  net/bnxt: fix port stop process and cleanup resources
  net/bnxt: fix the drop action flow to support count action
  net/bnxt: reject offload flows with invalid MAC address
  net/bnxt: reduce debug log messages
  net/bnxt: fix to break the ipv4 and ipv6 ingress rule
  net/bnxt: change default flow rule to use 8B encap
  net/bnxt: fix the function id used in the flow flush
  net/bnxt: vfr port clean up during port stop
  net/bnxt: remove VLAN pop action for egress flows
  net/bnxt: increase counter support from 8K to 16K
  net/bnxt: enable support for VXLAN ipv6 encapsulation
  net/bnxt: enable support for nat action with tagged traffic
  net/bnxt: fix out of bound access in action bit handling
  net/bnxt: add support for locks in flow database

Mike Baucom (1):
  net/bnxt: free the em index on failure

Randy Schacher (1):
  net/bnxt: move IF tbl from tunneled to direct HWRM msg

Shahaji Bhosle (2):
  net/bnxt: add a null ptr check for the resource manager
  net/bnxt: update resource allocation settings

Somnath Kotur (6):
  net/bnxt: fix crash in VF rep queue selection
  net/bnxt: fix to conditionally rollback added VF-rep ports
  net/bnxt: fix to explicitly check and set for start cntr ID
  net/bnxt: fix bugs in representor data path
  net/bnxt: fix to check for vnic ptr in bnxt shutdown path
  net/bnxt: fix to have a separate mutex for FW health check

Sriharsha Basavapatna (1):
  net/bnxt: provide switch info while VF-Reps are configured

 drivers/net/bnxt/bnxt.h                       |   13 +-
 drivers/net/bnxt/bnxt_ethdev.c                |  101 +-
 drivers/net/bnxt/bnxt_filter.c                |   14 +-
 drivers/net/bnxt/bnxt_hwrm.c                  |   13 +-
 drivers/net/bnxt/bnxt_reps.c                  |  163 +-
 drivers/net/bnxt/bnxt_reps.h                  |    8 +
 drivers/net/bnxt/bnxt_rxr.c                   |   27 +-
 drivers/net/bnxt/bnxt_vnic.c                  |    3 +
 drivers/net/bnxt/hsi_struct_def_dpdk.h        |  935 ++-
 drivers/net/bnxt/tf_core/tf_em_internal.c     |    5 +-
 drivers/net/bnxt/tf_core/tf_msg.c             |   58 +-
 drivers/net/bnxt/tf_core/tf_rm.c              |   14 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c            |  569 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h            |   34 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c       |   56 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c       |  131 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c          |    8 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h          |    1 +
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c         |   17 +-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h         |    4 +-
 drivers/net/bnxt/tf_ulp/ulp_mapper.c          |   52 +-
 drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c        |    6 -
 drivers/net/bnxt/tf_ulp/ulp_port_db.c         |   41 +
 drivers/net/bnxt/tf_ulp/ulp_port_db.h         |   13 +
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |  153 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h      |    5 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c |  295 +-
 .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 5531 +++++++++++------
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |   66 +-
 .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  767 ++-
 drivers/net/bnxt/tf_ulp/ulp_utils.c           |   43 +-
 drivers/net/bnxt/tf_ulp/ulp_utils.h           |    7 +-
 32 files changed, 5836 insertions(+), 3317 deletions(-)

-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 01/25] net/bnxt: fix port stop process and cleanup resources
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 02/25] net/bnxt: fix the drop action flow to support count action Ajit Khaparde
                   ` (24 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Shahaji Bhosle

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The port deinitialization now cleans up all the resources
properly. If all the ports are stopped then ulp context is
freed.
Added fix to update the correct tfp pointer in the ulp context
with the changes to support multi control channels.

Fixes: 70e64b27af5b42 ("net/bnxt: support ULP session manager cleanup")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
---
 drivers/net/bnxt/bnxt.h                 |  12 +-
 drivers/net/bnxt/bnxt_ethdev.c          |  18 +-
 drivers/net/bnxt/bnxt_reps.c            | 106 ++---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c      | 494 ++++++++++++++----------
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h      |  16 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c |  19 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 131 ++++++-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c   |   4 +-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h   |   4 +-
 9 files changed, 494 insertions(+), 310 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index a190d78bd..d2944aa74 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -823,8 +823,7 @@ struct bnxt_vf_representor {
 	uint16_t		dflt_vnic_id;
 	uint16_t		svif;
 	uint16_t		vfr_tx_cfa_action;
-	uint32_t		rep2vf_flow_id;
-	uint32_t		vf2rep_flow_id;
+	uint32_t		dpdk_port_id;
 	/* Private data store of associated PF/Trusted VF */
 	struct rte_eth_dev	*parent_dev;
 	uint8_t			mac_addr[RTE_ETHER_ADDR_LEN];
@@ -894,11 +893,14 @@ extern int bnxt_logtype_driver;
 	  PMD_DRV_LOG_RAW(level, fmt, ## args)
 
 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
-int32_t bnxt_ulp_init(struct bnxt *bp);
-void bnxt_ulp_deinit(struct bnxt *bp);
+int32_t bnxt_ulp_port_init(struct bnxt *bp);
+void bnxt_ulp_port_deinit(struct bnxt *bp);
 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
-
+int32_t
+bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
+int32_t
+bnxt_ulp_delete_vfr_default_rules(struct bnxt_vf_representor *vfr);
 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
 		       enum bnxt_ulp_intf_type type);
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 75d055be0..fdbd6ce58 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1236,6 +1236,11 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 	if (rc)
 		goto error;
 
+	/* Initialize bnxt ULP port details */
+	rc = bnxt_ulp_port_init(bp);
+	if (rc)
+		goto error;
+
 	eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 	eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 
@@ -1243,8 +1248,6 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 	bnxt_schedule_fw_health_check(bp);
 	pthread_mutex_unlock(&bp->def_cp_lock);
 
-	bnxt_ulp_init(bp);
-
 	return 0;
 
 error:
@@ -1304,8 +1307,8 @@ static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 	/* disable uio/vfio intr/eventfd mapping */
 	rte_intr_disable(intr_handle);
 
-	bnxt_ulp_destroy_df_rules(bp, false);
-	bnxt_ulp_deinit(bp);
+	/* delete the bnxt ULP port details */
+	bnxt_ulp_port_deinit(bp);
 
 	bnxt_cancel_fw_health_check(bp);
 
@@ -1599,8 +1602,6 @@ static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 	if (rc != 0)
 		vnic->flags = old_flags;
 
-	bnxt_ulp_create_df_rules(bp);
-
 	return rc;
 }
 
@@ -3701,9 +3702,14 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
 	struct bnxt *bp = dev->data->dev_private;
 	int ret = 0;
 
+	if (!bp)
+		return -EIO;
+
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
 		struct bnxt_vf_representor *vfr = dev->data->dev_private;
 		bp = vfr->parent_dev->data->dev_private;
+		if (!bp)
+			return -EIO;
 	}
 
 	ret = is_bnxt_in_error(bp);
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 2f2af0d44..3101512c3 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -268,66 +268,37 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
 	struct rte_eth_dev *parent_dev = vfr->parent_dev;
 	struct bnxt *parent_bp = parent_dev->data->dev_private;
-	uint16_t vfr_port_id = vfr_ethdev->data->port_id;
-	struct ulp_tlv_param param_list[] = {
-		{
-			.type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID,
-			.length = 2,
-			.value = {(vfr_port_id >> 8) & 0xff, vfr_port_id & 0xff}
-		},
-		{
-			.type = BNXT_ULP_DF_PARAM_TYPE_LAST,
-			.length = 0,
-			.value = {0}
-		}
-	};
 
-	ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev);
+	if (!parent_bp || !parent_bp->ulp_ctx) {
+		BNXT_TF_DBG(ERR, "Invalid arguments\n");
+		return 0;
+	}
 
-	rc = ulp_default_flow_create(parent_dev, param_list,
-				     BNXT_ULP_DF_TPL_VFREP_TO_VF,
-				     &vfr->rep2vf_flow_id);
+	/* Update the ULP portdata base with the new VFR interface */
+	rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev);
 	if (rc) {
-		BNXT_TF_DBG(DEBUG,
-			    "Default flow rule creation for VFR->VF failed!\n");
-		goto err;
+		BNXT_TF_DBG(ERR, "Failed to update ulp port details vfr:%u\n",
+			    vfr->vf_id);
+		return rc;
 	}
 
-	BNXT_TF_DBG(DEBUG, "*** Default flow rule created for VFR->VF! ***\n");
-	BNXT_TF_DBG(DEBUG, "rep2vf_flow_id = %d\n", vfr->rep2vf_flow_id);
-	rc = ulp_default_flow_db_cfa_action_get(parent_bp->ulp_ctx,
-						vfr->rep2vf_flow_id,
-						&vfr->vfr_tx_cfa_action);
-	if (rc) {
-		BNXT_TF_DBG(DEBUG,
-			    "Failed to get action_ptr for VFR->VF dflt rule\n");
-		goto rep2vf_free;
-	}
-	BNXT_TF_DBG(DEBUG, "tx_cfa_action = %d\n", vfr->vfr_tx_cfa_action);
-	rc = ulp_default_flow_create(parent_dev, param_list,
-				     BNXT_ULP_DF_TPL_VF_TO_VFREP,
-				     &vfr->vf2rep_flow_id);
+	/* Create the default rules for the VFR */
+	rc = bnxt_ulp_create_vfr_default_rules(vfr_ethdev);
 	if (rc) {
-		BNXT_TF_DBG(DEBUG,
-			    "Default flow rule creation for VF->VFR failed!\n");
-		goto rep2vf_free;
+		BNXT_TF_DBG(ERR, "Failed to create VFR default rules vfr:%u\n",
+			    vfr->vf_id);
+		return rc;
 	}
-
-	BNXT_TF_DBG(DEBUG, "*** Default flow rule created for VF->VFR! ***\n");
-	BNXT_TF_DBG(DEBUG, "vfr2rep_flow_id = %d\n", vfr->vf2rep_flow_id);
-
+	/* update the port id so you can backtrack to ethdev */
+	vfr->dpdk_port_id = vfr_ethdev->data->port_id;
 	rc = bnxt_hwrm_cfa_vfr_alloc(parent_bp, vfr->vf_id);
-	if (rc)
-		goto vf2rep_free;
-
-	return 0;
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed in hwrm vfr alloc vfr:%u rc=%d\n",
+			    vfr->vf_id, rc);
+		(void)bnxt_ulp_delete_vfr_default_rules(vfr);
+	}
 
-vf2rep_free:
-	ulp_default_flow_destroy(vfr->parent_dev, vfr->vf2rep_flow_id);
-rep2vf_free:
-	ulp_default_flow_destroy(vfr->parent_dev, vfr->rep2vf_flow_id);
-err:
-	return -EIO;
+	return rc;
 }
 
 static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
@@ -338,7 +309,7 @@ static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 
 	if (!vfr || !vfr->parent_dev) {
 		PMD_DRV_LOG(ERR,
-			    "No memory allocated for representor\n");
+				"No memory allocated for representor\n");
 		return -ENOMEM;
 	}
 
@@ -392,14 +363,12 @@ int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 	rep_info = &parent_bp->rep_info[rep_bp->vf_id];
 
 	pthread_mutex_lock(&rep_info->vfr_start_lock);
-	if (rep_info->conduit_valid) {
-		pthread_mutex_unlock(&rep_info->vfr_start_lock);
-		return 0;
-	}
-	rc = bnxt_get_dflt_vnic_svif(parent_bp, rep_bp);
-	if (rc || !rep_info->conduit_valid) {
-		pthread_mutex_unlock(&rep_info->vfr_start_lock);
-		return rc;
+	if (!rep_info->conduit_valid) {
+		rc = bnxt_get_dflt_vnic_svif(parent_bp, rep_bp);
+		if (rc || !rep_info->conduit_valid) {
+			pthread_mutex_unlock(&rep_info->vfr_start_lock);
+			return rc;
+		}
 	}
 	pthread_mutex_unlock(&rep_info->vfr_start_lock);
 
@@ -418,21 +387,7 @@ int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 
 static int bnxt_tf_vfr_free(struct bnxt_vf_representor *vfr)
 {
-	int rc = 0;
-
-	rc = ulp_default_flow_destroy(vfr->parent_dev,
-				      vfr->rep2vf_flow_id);
-	if (rc)
-		PMD_DRV_LOG(ERR,
-			    "default flow destroy failed rep2vf flowid: %d\n",
-			    vfr->rep2vf_flow_id);
-	rc = ulp_default_flow_destroy(vfr->parent_dev,
-				      vfr->vf2rep_flow_id);
-	if (rc)
-		PMD_DRV_LOG(ERR,
-			    "default flow destroy failed vf2rep flowid: %d\n",
-			    vfr->vf2rep_flow_id);
-	return 0;
+	return bnxt_ulp_delete_vfr_default_rules(vfr);
 }
 
 static int bnxt_vfr_free(struct bnxt_vf_representor *vfr)
@@ -459,7 +414,6 @@ static int bnxt_vfr_free(struct bnxt_vf_representor *vfr)
 		PMD_DRV_LOG(ERR,
 			    "Failed to free representor %d in FW\n",
 			    vfr->vf_id);
-		return rc;
 	}
 
 	PMD_DRV_LOG(DEBUG, "freed representor %d in FW\n",
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 0d4a45513..21baed048 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -32,23 +32,22 @@ static pthread_mutex_t bnxt_ulp_global_mutex = PTHREAD_MUTEX_INITIALIZER;
 
 /*
  * Allow the deletion of context only for the bnxt device that
- * created the session
- * TBD - The implementation of the function should change to
- * using the reference count once tf_session_attach functionality
- * is fixed.
+ * created the session.
  */
 bool
 ulp_ctx_deinit_allowed(void *ptr)
 {
 	struct bnxt *bp = (struct bnxt *)ptr;
 
-	if (!bp)
-		return 0;
+	if (!bp || !bp->ulp_ctx || !bp->ulp_ctx->cfg_data)
+		return false;
 
-	if (&bp->tfp == bp->ulp_ctx->g_tfp)
-		return 1;
+	if (!bp->ulp_ctx->cfg_data->ref_cnt) {
+		BNXT_TF_DBG(DEBUG, "ulp ctx shall initiate deinit\n");
+		return true;
+	}
 
-	return 0;
+	return false;
 }
 
 /*
@@ -155,8 +154,10 @@ ulp_ctx_session_open(struct bnxt *bp,
 			    params.ctrl_chan_name, rc);
 		return -EINVAL;
 	}
-	session->session_opened = 1;
-	session->g_tfp = &bp->tfp;
+	if (!session->session_opened) {
+		session->session_opened = 1;
+		session->g_tfp = &bp->tfp;
+	}
 	return rc;
 }
 
@@ -173,7 +174,6 @@ ulp_ctx_session_close(struct bnxt *bp,
 		tf_close_session(&bp->tfp);
 	session->session_opened = 0;
 	session->g_tfp = NULL;
-	bp->ulp_ctx->g_tfp = NULL;
 }
 
 static void
@@ -285,10 +285,6 @@ ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
 	if (!ulp_ctx || !ulp_ctx->cfg_data)
 		return -EINVAL;
 
-	/* Free the resources for the last device */
-	if (!ulp_ctx_deinit_allowed(bp))
-		return rc;
-
 	tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx);
 	if (!tfp) {
 		BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
@@ -331,11 +327,6 @@ static int32_t
 ulp_ctx_deinit(struct bnxt *bp,
 	       struct bnxt_ulp_session_state *session)
 {
-	if (!session || !bp) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
 	/* close the tf session */
 	ulp_ctx_session_close(bp, session);
 
@@ -356,11 +347,6 @@ ulp_ctx_init(struct bnxt *bp,
 	struct bnxt_ulp_data	*ulp_data;
 	int32_t			rc = 0;
 
-	if (!session || !bp) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
 	/* Allocate memory to hold ulp context data. */
 	ulp_data = rte_zmalloc("bnxt_ulp_data",
 			       sizeof(struct bnxt_ulp_data), 0);
@@ -378,11 +364,12 @@ ulp_ctx_init(struct bnxt *bp,
 	/* Open the ulp session. */
 	rc = ulp_ctx_session_open(bp, session);
 	if (rc) {
+		session->session_opened = 1;
 		(void)ulp_ctx_deinit(bp, session);
 		return rc;
 	}
 
-	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session->g_tfp);
+	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
 	return rc;
 }
 
@@ -395,7 +382,7 @@ ulp_dparms_init(struct bnxt *bp,
 	uint32_t dev_id;
 
 	if (!bp->max_num_kflows)
-		return -EINVAL;
+		return 0;
 
 	if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) {
 		BNXT_TF_DBG(DEBUG, "Failed to get device id\n");
@@ -445,51 +432,37 @@ ulp_dparms_dev_port_intf_update(struct bnxt *bp,
 }
 
 static int32_t
-ulp_ctx_attach(struct bnxt_ulp_context *ulp_ctx,
+ulp_ctx_attach(struct bnxt *bp,
 	       struct bnxt_ulp_session_state *session)
 {
-	if (!ulp_ctx || !session) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
+	int32_t rc = 0;
 
 	/* Increment the ulp context data reference count usage. */
-	ulp_ctx->cfg_data = session->cfg_data;
-	ulp_ctx->cfg_data->ref_cnt++;
+	bp->ulp_ctx->cfg_data = session->cfg_data;
+	bp->ulp_ctx->cfg_data->ref_cnt++;
 
-	/* TBD call TF_session_attach. */
-	ulp_ctx->g_tfp = session->g_tfp;
-	return 0;
-}
-
-static int32_t
-ulp_ctx_detach(struct bnxt *bp,
-	       struct bnxt_ulp_session_state *session)
-{
-	struct bnxt_ulp_context *ulp_ctx;
+	/* update the session details in bnxt tfp */
+	bp->tfp.session = session->g_tfp->session;
 
-	if (!bp || !session) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
+	/* Create a TF Client */
+	rc = ulp_ctx_session_open(bp, session);
+	if (rc) {
+		PMD_DRV_LOG(ERR, "Failed to open ctxt session, rc:%d\n", rc);
+		bp->tfp.session = NULL;
+		return rc;
 	}
-	ulp_ctx = bp->ulp_ctx;
 
-	if (!ulp_ctx->cfg_data)
-		return 0;
-
-	/* TBD call TF_session_detach */
+	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+	return rc;
+}
 
-	/* Increment the ulp context data reference count usage. */
-	if (ulp_ctx->cfg_data->ref_cnt >= 1) {
-		ulp_ctx->cfg_data->ref_cnt--;
-		if (ulp_ctx_deinit_allowed(bp))
-			ulp_ctx_deinit(bp, session);
-		ulp_ctx->cfg_data = NULL;
-		ulp_ctx->g_tfp = NULL;
-		return 0;
+static void
+ulp_ctx_detach(struct bnxt *bp)
+{
+	if (bp->tfp.session) {
+		tf_close_session(&bp->tfp);
+		bp->tfp.session = NULL;
 	}
-	BNXT_TF_DBG(ERR, "context deatach on invalid data\n");
-	return 0;
 }
 
 /*
@@ -542,6 +515,7 @@ ulp_session_init(struct bnxt *bp,
 	struct rte_pci_device		*pci_dev;
 	struct rte_pci_addr		*pci_addr;
 	struct bnxt_ulp_session_state	*session;
+	int rc = 0;
 
 	if (!bp)
 		return NULL;
@@ -567,7 +541,12 @@ ulp_session_init(struct bnxt *bp,
 			/* Add it to the queue */
 			session->pci_info.domain = pci_addr->domain;
 			session->pci_info.bus = pci_addr->bus;
-			pthread_mutex_init(&session->bnxt_ulp_mutex, NULL);
+			rc = pthread_mutex_init(&session->bnxt_ulp_mutex, NULL);
+			if (rc) {
+				BNXT_TF_DBG(ERR, "mutex create failed\n");
+				pthread_mutex_unlock(&bnxt_ulp_global_mutex);
+				return NULL;
+			}
 			STAILQ_INSERT_TAIL(&bnxt_ulp_session_list,
 					   session, next);
 		}
@@ -643,80 +622,122 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
 	return rc;
 }
 
+/* Internal function to delete all the flows belonging to the given port */
+static void
+bnxt_ulp_flush_port_flows(struct bnxt *bp)
+{
+	uint16_t func_id;
+
+	func_id = bnxt_get_fw_func_id(bp->eth_dev->data->port_id,
+				      BNXT_ULP_INTF_TYPE_INVALID);
+	ulp_flow_db_function_flow_flush(bp->ulp_ctx, func_id);
+}
+
+/* Internal function to delete the VFR default flows */
+static void
+bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global)
+{
+	struct bnxt_ulp_vfr_rule_info *info;
+	uint8_t port_id;
+	struct rte_eth_dev *vfr_eth_dev;
+	struct bnxt_vf_representor *vfr_bp;
+
+	if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev))
+		return;
+
+	if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data)
+		return;
+
+	/* Delete default rules for all ports */
+	for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
+		info = &bp->ulp_ctx->cfg_data->vfr_rule_info[port_id];
+		if (!info->valid)
+			continue;
+
+		if (!global && info->parent_port_id !=
+		    bp->eth_dev->data->port_id)
+			continue;
+
+		/* Destroy the flows */
+		ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
+		ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
+		/* Clean up the tx action pointer */
+		vfr_eth_dev = &rte_eth_devices[port_id];
+		if (vfr_eth_dev) {
+			vfr_bp = vfr_eth_dev->data->dev_private;
+			vfr_bp->vfr_tx_cfa_action = 0;
+		}
+		memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
+	}
+}
+
 /*
- * When a port is initialized by dpdk. This functions is called
- * and this function initializes the ULP context and rest of the
+ * When a port is deinit'ed by dpdk. This function is called
+ * and this function clears the ULP context and rest of the
  * infrastructure associated with it.
  */
-int32_t
-bnxt_ulp_init(struct bnxt *bp)
+static void
+bnxt_ulp_deinit(struct bnxt *bp,
+		struct bnxt_ulp_session_state *session)
 {
-	struct bnxt_ulp_session_state *session;
-	bool init;
-	int rc;
+	if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data)
+		return;
 
-	if (!BNXT_TRUFLOW_EN(bp))
-		return 0;
+	/* clean up default flows */
+	bnxt_ulp_destroy_df_rules(bp, true);
 
-	if (bp->ulp_ctx) {
-		BNXT_TF_DBG(DEBUG, "ulp ctx already allocated\n");
-		return -EINVAL;
-	}
+	/* clean up default VFR flows */
+	bnxt_ulp_destroy_vfr_default_rules(bp, true);
 
-	/*
-	 * Multiple uplink ports can be associated with a single vswitch.
-	 * Make sure only the port that is started first will initialize
-	 * the TF session.
-	 */
-	session = ulp_session_init(bp, &init);
-	if (!session) {
-		BNXT_TF_DBG(ERR, "Failed to initialize the tf session\n");
-		return -EINVAL;
-	}
+	/* clean up regular flows */
+	ulp_flow_db_flush_flows(bp->ulp_ctx, BNXT_ULP_REGULAR_FLOW_TABLE);
 
-	bp->ulp_ctx = rte_zmalloc("bnxt_ulp_ctx",
-				  sizeof(struct bnxt_ulp_context), 0);
-	if (!bp->ulp_ctx) {
-		BNXT_TF_DBG(ERR, "Failed to allocate ulp ctx\n");
-		ulp_session_deinit(session);
-		return -ENOMEM;
-	}
+	/* cleanup the eem table scope */
+	ulp_eem_tbl_scope_deinit(bp, bp->ulp_ctx);
 
-	/*
-	 * If ULP is already initialized for a specific domain then simply
-	 * assign the ulp context to this rte_eth_dev.
-	 */
-	if (init) {
-		rc = ulp_ctx_attach(bp->ulp_ctx, session);
-		if (rc) {
-			BNXT_TF_DBG(ERR,
-				    "Failed to attach the ulp context\n");
-			ulp_session_deinit(session);
-			rte_free(bp->ulp_ctx);
-			return rc;
-		}
+	/* cleanup the flow database */
+	ulp_flow_db_deinit(bp->ulp_ctx);
 
-		/* Update bnxt driver flags */
-		rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
-		if (rc) {
-			BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
-			ulp_ctx_detach(bp, session);
-			ulp_session_deinit(session);
-			rte_free(bp->ulp_ctx);
-			return rc;
-		}
+	/* Delete the Mark database */
+	ulp_mark_db_deinit(bp->ulp_ctx);
 
-		/* update the port database */
-		rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
-		if (rc) {
-			BNXT_TF_DBG(ERR,
-				    "Failed to update port database\n");
-			ulp_ctx_detach(bp, session);
-			ulp_session_deinit(session);
-			rte_free(bp->ulp_ctx);
-		}
-		return rc;
-	}
+	/* cleanup the ulp mapper */
+	ulp_mapper_deinit(bp->ulp_ctx);
+
+	/* Delete the Flow Counter Manager */
+	ulp_fc_mgr_deinit(bp->ulp_ctx);
+
+	/* Delete the Port database */
+	ulp_port_db_deinit(bp->ulp_ctx);
+
+	/* Disable NAT feature */
+	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP,
+					 TF_TUNNEL_ENCAP_NAT,
+					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
+					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
+					 0);
+
+	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP,
+					 TF_TUNNEL_ENCAP_NAT,
+					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
+					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
+					 0);
+
+	/* Delete the ulp context and tf session and free the ulp context */
+	ulp_ctx_deinit(bp, session);
+	BNXT_TF_DBG(DEBUG, "ulp ctx has been deinitialized\n");
+}
+
+/*
+ * When a port is initialized by dpdk. This functions is called
+ * and this function initializes the ULP context and rest of the
+ * infrastructure associated with it.
+ */
+static int32_t
+bnxt_ulp_init(struct bnxt *bp,
+	      struct bnxt_ulp_session_state *session)
+{
+	int rc;
 
 	/* Allocate and Initialize the ulp context. */
 	rc = ulp_ctx_init(bp, session);
@@ -727,25 +748,15 @@ bnxt_ulp_init(struct bnxt *bp)
 
 	/* Initialize ulp dparms with values devargs passed */
 	rc = ulp_dparms_init(bp, bp->ulp_ctx);
-
-	/* create the port database */
-	rc = ulp_port_db_init(bp->ulp_ctx, bp->port_cnt);
-	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to create the port database\n");
-		goto jump_to_error;
-	}
-
-	/* Update bnxt driver flags */
-	rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
 	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
+		BNXT_TF_DBG(ERR, "Failed to initialize the dparms\n");
 		goto jump_to_error;
 	}
 
-	/* update the port database */
-	rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
+	/* create the port database */
+	rc = ulp_port_db_init(bp->ulp_ctx, bp->port_cnt);
 	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to update port database\n");
+		BNXT_TF_DBG(ERR, "Failed to create the port database\n");
 		goto jump_to_error;
 	}
 
@@ -804,32 +815,131 @@ bnxt_ulp_init(struct bnxt *bp)
 		BNXT_TF_DBG(ERR, "Failed to set tx global configuration\n");
 		goto jump_to_error;
 	}
-
+	BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n");
 	return rc;
 
 jump_to_error:
-	bnxt_ulp_deinit(bp);
-	return -ENOMEM;
+	bnxt_ulp_deinit(bp, session);
+	return rc;
 }
 
-/* Below are the access functions to access internal data of ulp context. */
+/*
+ * When a port is initialized by dpdk. This functions sets up
+ * the port specific details.
+ */
+int32_t
+bnxt_ulp_port_init(struct bnxt *bp)
+{
+	struct bnxt_ulp_session_state *session;
+	bool initialized;
+	int32_t rc = 0;
+
+	if (!bp || !BNXT_TRUFLOW_EN(bp))
+		return rc;
+
+	if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
+		BNXT_TF_DBG(ERR,
+			    "Skip ulp init for port: %d, not a TVF or PF\n",
+			bp->eth_dev->data->port_id);
+		return rc;
+	}
+
+	if (bp->ulp_ctx) {
+		BNXT_TF_DBG(DEBUG, "ulp ctx already allocated\n");
+		return rc;
+	}
+
+	bp->ulp_ctx = rte_zmalloc("bnxt_ulp_ctx",
+				  sizeof(struct bnxt_ulp_context), 0);
+	if (!bp->ulp_ctx) {
+		BNXT_TF_DBG(ERR, "Failed to allocate ulp ctx\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * Multiple uplink ports can be associated with a single vswitch.
+	 * Make sure only the port that is started first will initialize
+	 * the TF session.
+	 */
+	session = ulp_session_init(bp, &initialized);
+	if (!session) {
+		BNXT_TF_DBG(ERR, "Failed to initialize the tf session\n");
+		rc = -EIO;
+		goto jump_to_error;
+	}
+
+	if (initialized) {
+		/*
+		 * If ULP is already initialized for a specific domain then
+		 * simply assign the ulp context to this rte_eth_dev.
+		 */
+		rc = ulp_ctx_attach(bp, session);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Failed to attach the ulp context\n");
+			goto jump_to_error;
+		}
+	} else {
+		rc = bnxt_ulp_init(bp, session);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Failed to initialize the ulp init\n");
+			goto jump_to_error;
+		}
+	}
+
+	/* Update bnxt driver flags */
+	rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
+		goto jump_to_error;
+	}
+
+	/* update the port database for the given interface */
+	rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to update port database\n");
+		goto jump_to_error;
+	}
+	/* create the default rules */
+	bnxt_ulp_create_df_rules(bp);
+	BNXT_TF_DBG(DEBUG, "ULP Port:%d created and initialized\n",
+		    bp->eth_dev->data->port_id);
+	return rc;
+
+jump_to_error:
+	bnxt_ulp_port_deinit(bp);
+	return rc;
+}
 
 /*
- * When a port is deinit'ed by dpdk. This function is called
- * and this function clears the ULP context and rest of the
- * infrastructure associated with it.
+ * When a port is de-initialized by dpdk. This functions clears up
+ * the port specific details.
  */
 void
-bnxt_ulp_deinit(struct bnxt *bp)
+bnxt_ulp_port_deinit(struct bnxt *bp)
 {
-	struct bnxt_ulp_session_state	*session;
-	struct rte_pci_device		*pci_dev;
-	struct rte_pci_addr		*pci_addr;
+	struct bnxt_ulp_session_state *session;
+	struct rte_pci_device *pci_dev;
+	struct rte_pci_addr *pci_addr;
 
 	if (!BNXT_TRUFLOW_EN(bp))
 		return;
 
-	/* Get the session first */
+	if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
+		BNXT_TF_DBG(ERR,
+			    "Skip ULP deinit port:%d, not a TVF or PF\n",
+			    bp->eth_dev->data->port_id);
+		return;
+	}
+
+	if (!bp->ulp_ctx) {
+		BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
+		return;
+	}
+
+	BNXT_TF_DBG(DEBUG, "ULP Port:%d destroyed\n",
+		    bp->eth_dev->data->port_id);
+
+	/* Get the session details  */
 	pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device);
 	pci_addr = &pci_dev->addr;
 	pthread_mutex_lock(&bnxt_ulp_global_mutex);
@@ -837,57 +947,42 @@ bnxt_ulp_deinit(struct bnxt *bp)
 	pthread_mutex_unlock(&bnxt_ulp_global_mutex);
 
 	/* session not found then just exit */
-	if (!session)
+	if (!session) {
+		/* Free the ulp context */
+		rte_free(bp->ulp_ctx);
+		bp->ulp_ctx = NULL;
 		return;
+	}
 
-	/* clean up default flows */
-	bnxt_ulp_destroy_df_rules(bp, true);
-
-	/* clean up regular flows */
-	ulp_flow_db_flush_flows(bp->ulp_ctx, BNXT_ULP_REGULAR_FLOW_TABLE);
-
-	/* cleanup the eem table scope */
-	ulp_eem_tbl_scope_deinit(bp, bp->ulp_ctx);
-
-	/* cleanup the flow database */
-	ulp_flow_db_deinit(bp->ulp_ctx);
-
-	/* Delete the Mark database */
-	ulp_mark_db_deinit(bp->ulp_ctx);
-
-	/* cleanup the ulp mapper */
-	ulp_mapper_deinit(bp->ulp_ctx);
-
-	/* Delete the Flow Counter Manager */
-	ulp_fc_mgr_deinit(bp->ulp_ctx);
-
-	/* Delete the Port database */
-	ulp_port_db_deinit(bp->ulp_ctx);
-
-	/* Disable NAT feature */
-	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP,
-					 TF_TUNNEL_ENCAP_NAT,
-					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
-					 0);
+	/* Check the reference count to deinit or deattach*/
+	if (bp->ulp_ctx->cfg_data && bp->ulp_ctx->cfg_data->ref_cnt) {
+		bp->ulp_ctx->cfg_data->ref_cnt--;
+		if (bp->ulp_ctx->cfg_data->ref_cnt) {
+			/* free the port details */
+			/* Free the default flow rule associated to this port */
+			bnxt_ulp_destroy_df_rules(bp, false);
+			bnxt_ulp_destroy_vfr_default_rules(bp, false);
 
-	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP,
-					 TF_TUNNEL_ENCAP_NAT,
-					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
-					 0);
+			/* free flows associated with this port */
+			bnxt_ulp_flush_port_flows(bp);
 
-	/* Delete the ulp context and tf session */
-	ulp_ctx_detach(bp, session);
+			/* close the session associated with this port */
+			ulp_ctx_detach(bp);
+		} else {
+			/* Perform ulp ctx deinit */
+			bnxt_ulp_deinit(bp, session);
+		}
+	}
 
-	/* Finally delete the bnxt session*/
+	/* clean up the session */
 	ulp_session_deinit(session);
 
+	/* Free the ulp context */
 	rte_free(bp->ulp_ctx);
-
 	bp->ulp_ctx = NULL;
 }
 
+/* Below are the access functions to access internal data of ulp context. */
 /* Function to set the Mark DB into the context */
 int32_t
 bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx,
@@ -974,7 +1069,6 @@ bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
 		return -EINVAL;
 	}
 
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	ulp->g_tfp = tfp;
 	return 0;
 }
@@ -987,7 +1081,6 @@ bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp)
 		BNXT_TF_DBG(ERR, "Invalid arguments\n");
 		return NULL;
 	}
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	return ulp->g_tfp;
 }
 
@@ -1129,3 +1222,14 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx,
 	*flags =  ulp_ctx->cfg_data->ulp_flags;
 	return 0;
 }
+
+/* Function to get the ulp vfr info from the ulp context. */
+struct bnxt_ulp_vfr_rule_info*
+bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(struct bnxt_ulp_context *ulp_ctx,
+				     uint32_t port_id)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data || port_id >= RTE_MAX_ETHPORTS)
+		return NULL;
+
+	return &ulp_ctx->cfg_data->vfr_rule_info[port_id];
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index d53245215..8a2825ae5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -28,6 +28,13 @@ struct bnxt_ulp_df_rule_info {
 	uint8_t				valid;
 };
 
+struct bnxt_ulp_vfr_rule_info {
+	uint32_t			rep2vf_flow_id;
+	uint32_t			vf2rep_flow_id;
+	uint16_t			parent_port_id;
+	uint8_t				valid;
+};
+
 struct bnxt_ulp_data {
 	uint32_t			tbl_scope_id;
 	struct bnxt_ulp_mark_tbl	*mark_tbl;
@@ -38,12 +45,12 @@ struct bnxt_ulp_data {
 	struct bnxt_ulp_port_db		*port_db;
 	struct bnxt_ulp_fc_info		*fc_info;
 	uint32_t			ulp_flags;
-	struct bnxt_ulp_df_rule_info   df_rule_info[RTE_MAX_ETHPORTS];
+	struct bnxt_ulp_df_rule_info	df_rule_info[RTE_MAX_ETHPORTS];
+	struct bnxt_ulp_vfr_rule_info	vfr_rule_info[RTE_MAX_ETHPORTS];
 };
 
 struct bnxt_ulp_context {
 	struct bnxt_ulp_data	*cfg_data;
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	struct tf		*g_tfp;
 };
 
@@ -58,7 +65,6 @@ struct bnxt_ulp_session_state {
 	pthread_mutex_t				bnxt_ulp_mutex;
 	struct bnxt_ulp_pci_info		pci_info;
 	struct bnxt_ulp_data			*cfg_data;
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	struct tf				*g_tfp;
 	uint32_t				session_opened;
 };
@@ -183,4 +189,8 @@ int32_t
 bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx,
 			  struct bnxt_ulp_df_rule_info *info);
 
+struct bnxt_ulp_vfr_rule_info*
+bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(struct bnxt_ulp_context *ulp_ctx,
+				     uint32_t port_id);
+
 #endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 89fffcf01..2ab00453a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -87,19 +87,19 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	uint32_t class_id, act_tmpl;
 	struct rte_flow *flow_id;
 	uint32_t fid;
-	int ret;
+	int ret = BNXT_TF_RC_ERROR;
 
 	if (bnxt_ulp_flow_validate_args(attr,
 					pattern, actions,
 					error) == BNXT_TF_RC_ERROR) {
 		BNXT_TF_DBG(ERR, "Invalid arguments being passed\n");
-		return NULL;
+		goto parse_error;
 	}
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		return NULL;
+		goto parse_error;
 	}
 
 	/* Initialize the parser params */
@@ -173,20 +173,20 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
 {
 	struct ulp_rte_parser_params		params;
 	uint32_t class_id, act_tmpl;
-	int ret;
+	int ret = BNXT_TF_RC_ERROR;
 	struct bnxt_ulp_context *ulp_ctx;
 
 	if (bnxt_ulp_flow_validate_args(attr,
 					pattern, actions,
 					error) == BNXT_TF_RC_ERROR) {
 		BNXT_TF_DBG(ERR, "Invalid arguments being passed\n");
-		return -EINVAL;
+		goto parse_error;
 	}
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		return -EINVAL;
+		goto parse_error;
 	}
 
 	/* Initialize the parser params */
@@ -289,11 +289,8 @@ bnxt_ulp_flow_flush(struct rte_eth_dev *eth_dev,
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
 	if (!ulp_ctx) {
-		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		rte_flow_error_set(error, EINVAL,
-				   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
-				   "Failed to flush flow.");
-		return -EINVAL;
+		BNXT_TF_DBG(DEBUG, "ULP context is not initialized\n");
+		return ret;
 	}
 	bp = eth_dev->data->dev_private;
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index 46acc1d65..2d0c3bccc 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -377,7 +377,7 @@ int32_t
 ulp_default_flow_destroy(struct rte_eth_dev *eth_dev, uint32_t flow_id)
 {
 	struct bnxt_ulp_context *ulp_ctx;
-	int rc;
+	int rc = 0;
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
 	if (!ulp_ctx) {
@@ -385,6 +385,11 @@ ulp_default_flow_destroy(struct rte_eth_dev *eth_dev, uint32_t flow_id)
 		return -EINVAL;
 	}
 
+	if (!flow_id) {
+		BNXT_TF_DBG(DEBUG, "invalid flow id zero\n");
+		return rc;
+	}
+
 	rc = ulp_mapper_flow_destroy(ulp_ctx, flow_id,
 				     BNXT_ULP_DEFAULT_FLOW_TABLE);
 	if (rc)
@@ -417,7 +422,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
 					 info->port_to_app_flow_id);
 		ulp_default_flow_destroy(bp->eth_dev,
 					 info->app_to_port_flow_id);
-		info->valid = false;
+		memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info));
 		return;
 	}
 
@@ -431,7 +436,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
 					 info->port_to_app_flow_id);
 		ulp_default_flow_destroy(bp->eth_dev,
 					 info->app_to_port_flow_id);
-		info->valid = false;
+		memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info));
 	}
 }
 
@@ -470,22 +475,19 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
 
 	port_id = bp->eth_dev->data->port_id;
 	info = &bp->ulp_ctx->cfg_data->df_rule_info[port_id];
-	BNXT_TF_DBG(INFO, "*** creating port to app default rule ***\n");
 	rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS,
 					  &info->port_to_app_flow_id);
 	if (rc) {
-		PMD_DRV_LOG(ERR,
+		BNXT_TF_DBG(ERR,
 			    "Failed to create port to app default rule\n");
 		return rc;
 	}
-	BNXT_TF_DBG(INFO, "*** created port to app default rule ***\n");
 
 	bp->tx_cfa_action = 0;
-	BNXT_TF_DBG(INFO, "*** creating app to port default rule ***\n");
 	rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT,
 					  &info->app_to_port_flow_id);
 	if (rc) {
-		PMD_DRV_LOG(ERR,
+		BNXT_TF_DBG(ERR,
 			    "Failed to create app to port default rule\n");
 		goto port_to_app_free;
 	}
@@ -497,7 +499,6 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
 		goto app_to_port_free;
 
 	info->valid = true;
-	BNXT_TF_DBG(INFO, "*** created app to port default rule ***\n");
 	return 0;
 
 app_to_port_free:
@@ -508,3 +509,115 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
 
 	return rc;
 }
+
+static int32_t
+bnxt_create_port_vfr_default_rule(struct bnxt *bp,
+				  uint8_t flow_type,
+				  uint16_t vfr_port_id,
+				  uint32_t *flow_id)
+{
+	struct ulp_tlv_param param_list[] = {
+		{
+			.type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID,
+			.length = 2,
+			.value = {(vfr_port_id >> 8) & 0xff, vfr_port_id & 0xff}
+		},
+		{
+			.type = BNXT_ULP_DF_PARAM_TYPE_LAST,
+			.length = 0,
+			.value = {0}
+		}
+	};
+	return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
+				       flow_id);
+}
+
+int32_t
+bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
+{
+	struct bnxt_ulp_vfr_rule_info *info;
+	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
+	struct rte_eth_dev *parent_dev = vfr->parent_dev;
+	struct bnxt *bp = parent_dev->data->dev_private;
+	uint16_t vfr_port_id = vfr_ethdev->data->port_id;
+	uint8_t port_id;
+	int rc;
+
+	if (!bp || !BNXT_TRUFLOW_EN(bp))
+		return 0;
+
+	port_id = vfr_ethdev->data->port_id;
+	info = bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(bp->ulp_ctx, port_id);
+
+	if (!info) {
+		BNXT_TF_DBG(ERR, "Failed to get vfr ulp context\n");
+		return -EINVAL;
+	}
+
+	if (info->valid) {
+		BNXT_TF_DBG(ERR, "VFR already allocated\n");
+		return -EINVAL;
+	}
+
+	memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
+	rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VFREP_TO_VF,
+					       vfr_port_id,
+					       &info->rep2vf_flow_id);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to create VFREP to VF default rule\n");
+		goto error;
+	}
+	rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VF_TO_VFREP,
+					       vfr_port_id,
+					       &info->vf2rep_flow_id);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to create VF to VFREP default rule\n");
+		goto error;
+	}
+	rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
+						info->rep2vf_flow_id,
+						&vfr->vfr_tx_cfa_action);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to get the tx cfa action\n");
+		goto error;
+	}
+
+	/* Update the other details */
+	info->valid = true;
+	info->parent_port_id =  bp->eth_dev->data->port_id;
+	return 0;
+
+error:
+	if (info->rep2vf_flow_id)
+		ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
+	if (info->vf2rep_flow_id)
+		ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
+	return rc;
+}
+
+int32_t
+bnxt_ulp_delete_vfr_default_rules(struct bnxt_vf_representor *vfr)
+{
+	struct bnxt_ulp_vfr_rule_info *info;
+	struct rte_eth_dev *parent_dev = vfr->parent_dev;
+	struct bnxt *bp = parent_dev->data->dev_private;
+
+	if (!bp || !BNXT_TRUFLOW_EN(bp))
+		return 0;
+	info = bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(bp->ulp_ctx,
+						    vfr->dpdk_port_id);
+	if (!info) {
+		BNXT_TF_DBG(ERR, "Failed to get vfr ulp context\n");
+		return -EINVAL;
+	}
+
+	if (!info->valid) {
+		BNXT_TF_DBG(ERR, "VFR already freed\n");
+		return -EINVAL;
+	}
+	ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
+	ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
+	vfr->vfr_tx_cfa_action = 0;
+	memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
+	return 0;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 714451740..cbdf5df68 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -351,10 +351,8 @@ int32_t	ulp_flow_db_deinit(struct bnxt_ulp_context *ulp_ctxt)
 	struct bnxt_ulp_flow_db			*flow_db;
 
 	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
-	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+	if (!flow_db)
 		return -EINVAL;
-	}
 
 	/* Detach the flow database from the ulp context. */
 	bnxt_ulp_cntxt_ptr2_flow_db_set(ulp_ctxt, NULL);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 117e250d6..8c83664d0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -9,8 +9,8 @@
 #include "bnxt_ulp.h"
 #include "ulp_template_db_enum.h"
 
-#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS		128
-#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES	5
+#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS		512
+#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES	8
 
 /*
  * Structure for the flow database resource information
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 02/25] net/bnxt: fix the drop action flow to support count action
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 01/25] net/bnxt: fix port stop process and cleanup resources Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 03/25] net/bnxt: reject offload flows with invalid MAC address Ajit Khaparde
                   ` (23 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Changed the action template to support count action in addition
to a flow that does drop action.

Fixes: fe82f3e02701 ("net/bnxt: support exact match templates")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c  | 5 +++--
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index 14ce16ebd..b669a1408 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -36,7 +36,7 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_0020] = 25,
 	[BNXT_ULP_ACT_HID_0901] = 26,
 	[BNXT_ULP_ACT_HID_0121] = 27,
-	[BNXT_ULP_ACT_HID_0004] = 28,
+	[BNXT_ULP_ACT_HID_0006] = 28,
 	[BNXT_ULP_ACT_HID_0804] = 29,
 	[BNXT_ULP_ACT_HID_0105] = 30,
 	[BNXT_ULP_ACT_HID_0024] = 31,
@@ -332,9 +332,10 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 2
 	},
 	[28] = {
-	.act_hid = BNXT_ULP_ACT_HID_0004,
+	.act_hid = BNXT_ULP_ACT_HID_0006,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
+		BNXT_ULP_ACTION_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 4c6c3599d..f5c43a9f8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -838,7 +838,7 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_0020 = 0x0020,
 	BNXT_ULP_ACT_HID_0901 = 0x0901,
 	BNXT_ULP_ACT_HID_0121 = 0x0121,
-	BNXT_ULP_ACT_HID_0004 = 0x0004,
+	BNXT_ULP_ACT_HID_0006 = 0x0006,
 	BNXT_ULP_ACT_HID_0804 = 0x0804,
 	BNXT_ULP_ACT_HID_0105 = 0x0105,
 	BNXT_ULP_ACT_HID_0024 = 0x0024,
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 03/25] net/bnxt: reject offload flows with invalid MAC address
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 01/25] net/bnxt: fix port stop process and cleanup resources Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 02/25] net/bnxt: fix the drop action flow to support count action Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 04/25] net/bnxt: reduce debug log messages Ajit Khaparde
                   ` (22 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Reject offload flows that have broadcast or multicast
ethernet addresses.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index fcb7c4430..ed95cf60f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -603,6 +603,19 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
 	}
 }
 
+/* Internal Function to indentify broadcast or multicast packets */
+static int32_t
+ulp_rte_parser_is_bcmc_addr(const struct rte_ether_addr *eth_addr)
+{
+	if (rte_is_multicast_ether_addr(eth_addr) ||
+	    rte_is_broadcast_ether_addr(eth_addr)) {
+		BNXT_TF_DBG(DEBUG,
+			    "No support for bcast or mcast addr offload\n");
+		return 1;
+	}
+	return 0;
+}
+
 /* Function to handle the parsing of RTE Flow item Ethernet Header. */
 int32_t
 ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
@@ -625,10 +638,18 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
 		field = ulp_rte_parser_fld_copy(&params->hdr_field[idx],
 						eth_spec->dst.addr_bytes,
 						size);
+		/* Todo: work around to avoid multicast and broadcast addr */
+		if (ulp_rte_parser_is_bcmc_addr(&eth_spec->dst))
+			return BNXT_TF_RC_PARSE_ERR;
+
 		size = sizeof(eth_spec->src.addr_bytes);
 		field = ulp_rte_parser_fld_copy(field,
 						eth_spec->src.addr_bytes,
 						size);
+		/* Todo: work around to avoid multicast and broadcast addr */
+		if (ulp_rte_parser_is_bcmc_addr(&eth_spec->src))
+			return BNXT_TF_RC_PARSE_ERR;
+
 		field = ulp_rte_parser_fld_copy(field,
 						&eth_spec->type,
 						sizeof(eth_spec->type));
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 04/25] net/bnxt: reduce debug log messages
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (2 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 03/25] net/bnxt: reject offload flows with invalid MAC address Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 05/25] net/bnxt: fix to break the ipv4 and ipv6 ingress rule Ajit Khaparde
                   ` (21 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Removed the mark id log message since it is in the data path. Also
optimized the link status debug message.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/bnxt_hwrm.c           | 13 ++++---------
 drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c |  6 ------
 2 files changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index b26952646..57d1026f9 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1343,15 +1343,10 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 
 	HWRM_UNLOCK();
 
-	PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
-	PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
-	PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
-	PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
-	PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
-		    link_info->auto_link_speed_mask);
-	PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
-		    link_info->force_link_speed);
-
+	PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
+		    link_info->link_speed, link_info->auto_mode,
+		    link_info->auto_link_speed, link_info->auto_link_speed_mask,
+		    link_info->support_speeds, link_info->force_link_speed);
 	return rc;
 }
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 4df850f22..8b8dccf9f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -194,9 +194,6 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
 		    ULP_MARK_DB_ENTRY_IS_INVALID(&mtbl->gfid_tbl[idx]))
 			return -EINVAL;
 
-		BNXT_TF_DBG(DEBUG, "Get GFID[0x%0x] = 0x%0x\n",
-			    idx, mtbl->gfid_tbl[idx].mark_id);
-
 		*vfr_flag = ULP_MARK_DB_ENTRY_IS_VFR_ID(&mtbl->gfid_tbl[idx]);
 		*mark = mtbl->gfid_tbl[idx].mark_id;
 	} else {
@@ -204,9 +201,6 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
 		    ULP_MARK_DB_ENTRY_IS_INVALID(&mtbl->lfid_tbl[idx]))
 			return -EINVAL;
 
-		BNXT_TF_DBG(DEBUG, "Get LFID[0x%0x] = 0x%0x\n",
-			    idx, mtbl->lfid_tbl[idx].mark_id);
-
 		*vfr_flag = ULP_MARK_DB_ENTRY_IS_VFR_ID(&mtbl->lfid_tbl[idx]);
 		*mark = mtbl->lfid_tbl[idx].mark_id;
 	}
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 05/25] net/bnxt: fix to break the ipv4 and ipv6 ingress rule
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (3 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 04/25] net/bnxt: reduce debug log messages Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 06/25] net/bnxt: free the em index on failure Ajit Khaparde
                   ` (20 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The ingress rule to match on ipv4 and ipv6 is now two rules to
make sure both rules can coexist at the same time. Added count
action only for ingress flows.

Fixes: fe82f3e02701 ("net/bnxt: support exact match templates")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c |  298 +-
 .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 5522 +++++++++++------
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |   66 +-
 .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  767 ++-
 4 files changed, 4088 insertions(+), 2565 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index b669a1408..22142c137 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -36,64 +36,61 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_0020] = 25,
 	[BNXT_ULP_ACT_HID_0901] = 26,
 	[BNXT_ULP_ACT_HID_0121] = 27,
-	[BNXT_ULP_ACT_HID_0006] = 28,
-	[BNXT_ULP_ACT_HID_0804] = 29,
-	[BNXT_ULP_ACT_HID_0105] = 30,
-	[BNXT_ULP_ACT_HID_0024] = 31,
-	[BNXT_ULP_ACT_HID_0905] = 32,
-	[BNXT_ULP_ACT_HID_0125] = 33,
-	[BNXT_ULP_ACT_HID_0001] = 34,
-	[BNXT_ULP_ACT_HID_0005] = 35,
-	[BNXT_ULP_ACT_HID_0009] = 36,
-	[BNXT_ULP_ACT_HID_000d] = 37,
-	[BNXT_ULP_ACT_HID_0021] = 38,
-	[BNXT_ULP_ACT_HID_0029] = 39,
-	[BNXT_ULP_ACT_HID_0025] = 40,
-	[BNXT_ULP_ACT_HID_002d] = 41,
-	[BNXT_ULP_ACT_HID_0801] = 42,
-	[BNXT_ULP_ACT_HID_0809] = 43,
-	[BNXT_ULP_ACT_HID_0805] = 44,
-	[BNXT_ULP_ACT_HID_080d] = 45,
-	[BNXT_ULP_ACT_HID_0c15] = 46,
-	[BNXT_ULP_ACT_HID_0c19] = 47,
-	[BNXT_ULP_ACT_HID_02f6] = 48,
-	[BNXT_ULP_ACT_HID_04f8] = 49,
-	[BNXT_ULP_ACT_HID_01df] = 50,
-	[BNXT_ULP_ACT_HID_07e5] = 51,
-	[BNXT_ULP_ACT_HID_06ce] = 52,
-	[BNXT_ULP_ACT_HID_02fa] = 53,
-	[BNXT_ULP_ACT_HID_04fc] = 54,
-	[BNXT_ULP_ACT_HID_01e3] = 55,
-	[BNXT_ULP_ACT_HID_07e9] = 56,
-	[BNXT_ULP_ACT_HID_06d2] = 57,
-	[BNXT_ULP_ACT_HID_03f7] = 58,
-	[BNXT_ULP_ACT_HID_05f9] = 59,
-	[BNXT_ULP_ACT_HID_02e0] = 60,
-	[BNXT_ULP_ACT_HID_08e6] = 61,
-	[BNXT_ULP_ACT_HID_07cf] = 62,
-	[BNXT_ULP_ACT_HID_03fb] = 63,
-	[BNXT_ULP_ACT_HID_05fd] = 64,
-	[BNXT_ULP_ACT_HID_02e4] = 65,
-	[BNXT_ULP_ACT_HID_08ea] = 66,
-	[BNXT_ULP_ACT_HID_07d3] = 67,
-	[BNXT_ULP_ACT_HID_040d] = 68,
-	[BNXT_ULP_ACT_HID_040f] = 69,
-	[BNXT_ULP_ACT_HID_0413] = 70,
-	[BNXT_ULP_ACT_HID_0c0d] = 71,
+	[BNXT_ULP_ACT_HID_0004] = 28,
+	[BNXT_ULP_ACT_HID_0006] = 29,
+	[BNXT_ULP_ACT_HID_0804] = 30,
+	[BNXT_ULP_ACT_HID_0105] = 31,
+	[BNXT_ULP_ACT_HID_0024] = 32,
+	[BNXT_ULP_ACT_HID_0905] = 33,
+	[BNXT_ULP_ACT_HID_0125] = 34,
+	[BNXT_ULP_ACT_HID_0001] = 35,
+	[BNXT_ULP_ACT_HID_0005] = 36,
+	[BNXT_ULP_ACT_HID_0009] = 37,
+	[BNXT_ULP_ACT_HID_000d] = 38,
+	[BNXT_ULP_ACT_HID_0021] = 39,
+	[BNXT_ULP_ACT_HID_0029] = 40,
+	[BNXT_ULP_ACT_HID_0025] = 41,
+	[BNXT_ULP_ACT_HID_002d] = 42,
+	[BNXT_ULP_ACT_HID_0801] = 43,
+	[BNXT_ULP_ACT_HID_0809] = 44,
+	[BNXT_ULP_ACT_HID_0805] = 45,
+	[BNXT_ULP_ACT_HID_080d] = 46,
+	[BNXT_ULP_ACT_HID_0c15] = 47,
+	[BNXT_ULP_ACT_HID_0c19] = 48,
+	[BNXT_ULP_ACT_HID_02f6] = 49,
+	[BNXT_ULP_ACT_HID_04f8] = 50,
+	[BNXT_ULP_ACT_HID_01df] = 51,
+	[BNXT_ULP_ACT_HID_07e5] = 52,
+	[BNXT_ULP_ACT_HID_06ce] = 53,
+	[BNXT_ULP_ACT_HID_02fa] = 54,
+	[BNXT_ULP_ACT_HID_04fc] = 55,
+	[BNXT_ULP_ACT_HID_01e3] = 56,
+	[BNXT_ULP_ACT_HID_07e9] = 57,
+	[BNXT_ULP_ACT_HID_06d2] = 58,
+	[BNXT_ULP_ACT_HID_03f7] = 59,
+	[BNXT_ULP_ACT_HID_05f9] = 60,
+	[BNXT_ULP_ACT_HID_02e0] = 61,
+	[BNXT_ULP_ACT_HID_08e6] = 62,
+	[BNXT_ULP_ACT_HID_07cf] = 63,
+	[BNXT_ULP_ACT_HID_03fb] = 64,
+	[BNXT_ULP_ACT_HID_05fd] = 65,
+	[BNXT_ULP_ACT_HID_02e4] = 66,
+	[BNXT_ULP_ACT_HID_08ea] = 67,
+	[BNXT_ULP_ACT_HID_07d3] = 68,
+	[BNXT_ULP_ACT_HID_040d] = 69,
+	[BNXT_ULP_ACT_HID_040f] = 70,
+	[BNXT_ULP_ACT_HID_0413] = 71,
 	[BNXT_ULP_ACT_HID_0567] = 72,
 	[BNXT_ULP_ACT_HID_0a49] = 73,
 	[BNXT_ULP_ACT_HID_050e] = 74,
-	[BNXT_ULP_ACT_HID_0d0e] = 75,
-	[BNXT_ULP_ACT_HID_0668] = 76,
-	[BNXT_ULP_ACT_HID_0b4a] = 77,
-	[BNXT_ULP_ACT_HID_0411] = 78,
-	[BNXT_ULP_ACT_HID_056b] = 79,
-	[BNXT_ULP_ACT_HID_0a4d] = 80,
-	[BNXT_ULP_ACT_HID_0c11] = 81,
-	[BNXT_ULP_ACT_HID_0512] = 82,
-	[BNXT_ULP_ACT_HID_0d12] = 83,
-	[BNXT_ULP_ACT_HID_066c] = 84,
-	[BNXT_ULP_ACT_HID_0b4e] = 85
+	[BNXT_ULP_ACT_HID_0668] = 75,
+	[BNXT_ULP_ACT_HID_0b4a] = 76,
+	[BNXT_ULP_ACT_HID_0411] = 77,
+	[BNXT_ULP_ACT_HID_056b] = 78,
+	[BNXT_ULP_ACT_HID_0a4d] = 79,
+	[BNXT_ULP_ACT_HID_0512] = 80,
+	[BNXT_ULP_ACT_HID_066c] = 81,
+	[BNXT_ULP_ACT_HID_0b4e] = 82
 };
 
 struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
@@ -332,6 +329,13 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 2
 	},
 	[28] = {
+	.act_hid = BNXT_ULP_ACT_HID_0004,
+	.act_sig = { .bits =
+		BNXT_ULP_ACTION_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 2
+	},
+	[29] = {
 	.act_hid = BNXT_ULP_ACT_HID_0006,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -339,7 +343,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[29] = {
+	[30] = {
 	.act_hid = BNXT_ULP_ACT_HID_0804,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -347,7 +351,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[30] = {
+	[31] = {
 	.act_hid = BNXT_ULP_ACT_HID_0105,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -355,7 +359,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[31] = {
+	[32] = {
 	.act_hid = BNXT_ULP_ACT_HID_0024,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -363,7 +367,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[32] = {
+	[33] = {
 	.act_hid = BNXT_ULP_ACT_HID_0905,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -372,7 +376,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[33] = {
+	[34] = {
 	.act_hid = BNXT_ULP_ACT_HID_0125,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -381,14 +385,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[34] = {
+	[35] = {
 	.act_hid = BNXT_ULP_ACT_HID_0001,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[35] = {
+	[36] = {
 	.act_hid = BNXT_ULP_ACT_HID_0005,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -396,7 +400,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[36] = {
+	[37] = {
 	.act_hid = BNXT_ULP_ACT_HID_0009,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -404,7 +408,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[37] = {
+	[38] = {
 	.act_hid = BNXT_ULP_ACT_HID_000d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -413,7 +417,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[38] = {
+	[39] = {
 	.act_hid = BNXT_ULP_ACT_HID_0021,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -421,7 +425,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[39] = {
+	[40] = {
 	.act_hid = BNXT_ULP_ACT_HID_0029,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -430,7 +434,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[40] = {
+	[41] = {
 	.act_hid = BNXT_ULP_ACT_HID_0025,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -439,7 +443,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[41] = {
+	[42] = {
 	.act_hid = BNXT_ULP_ACT_HID_002d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -449,7 +453,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[42] = {
+	[43] = {
 	.act_hid = BNXT_ULP_ACT_HID_0801,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -457,7 +461,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[43] = {
+	[44] = {
 	.act_hid = BNXT_ULP_ACT_HID_0809,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -466,7 +470,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[44] = {
+	[45] = {
 	.act_hid = BNXT_ULP_ACT_HID_0805,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -475,7 +479,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[45] = {
+	[46] = {
 	.act_hid = BNXT_ULP_ACT_HID_080d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -485,14 +489,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[46] = {
+	[47] = {
 	.act_hid = BNXT_ULP_ACT_HID_0c15,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[47] = {
+	[48] = {
 	.act_hid = BNXT_ULP_ACT_HID_0c19,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
@@ -500,14 +504,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[48] = {
+	[49] = {
 	.act_hid = BNXT_ULP_ACT_HID_02f6,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[49] = {
+	[50] = {
 	.act_hid = BNXT_ULP_ACT_HID_04f8,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
@@ -515,14 +519,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[50] = {
+	[51] = {
 	.act_hid = BNXT_ULP_ACT_HID_01df,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[51] = {
+	[52] = {
 	.act_hid = BNXT_ULP_ACT_HID_07e5,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
@@ -531,7 +535,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[52] = {
+	[53] = {
 	.act_hid = BNXT_ULP_ACT_HID_06ce,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
@@ -541,7 +545,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[53] = {
+	[54] = {
 	.act_hid = BNXT_ULP_ACT_HID_02fa,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -549,7 +553,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[54] = {
+	[55] = {
 	.act_hid = BNXT_ULP_ACT_HID_04fc,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -558,7 +562,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[55] = {
+	[56] = {
 	.act_hid = BNXT_ULP_ACT_HID_01e3,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -566,7 +570,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[56] = {
+	[57] = {
 	.act_hid = BNXT_ULP_ACT_HID_07e9,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -576,7 +580,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[57] = {
+	[58] = {
 	.act_hid = BNXT_ULP_ACT_HID_06d2,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -587,7 +591,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[58] = {
+	[59] = {
 	.act_hid = BNXT_ULP_ACT_HID_03f7,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -595,7 +599,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[59] = {
+	[60] = {
 	.act_hid = BNXT_ULP_ACT_HID_05f9,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -604,7 +608,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[60] = {
+	[61] = {
 	.act_hid = BNXT_ULP_ACT_HID_02e0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -612,7 +616,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[61] = {
+	[62] = {
 	.act_hid = BNXT_ULP_ACT_HID_08e6,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -622,7 +626,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[62] = {
+	[63] = {
 	.act_hid = BNXT_ULP_ACT_HID_07cf,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -633,7 +637,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[63] = {
+	[64] = {
 	.act_hid = BNXT_ULP_ACT_HID_03fb,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -642,7 +646,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[64] = {
+	[65] = {
 	.act_hid = BNXT_ULP_ACT_HID_05fd,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -652,7 +656,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[65] = {
+	[66] = {
 	.act_hid = BNXT_ULP_ACT_HID_02e4,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -661,7 +665,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[66] = {
+	[67] = {
 	.act_hid = BNXT_ULP_ACT_HID_08ea,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -672,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[67] = {
+	[68] = {
 	.act_hid = BNXT_ULP_ACT_HID_07d3,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -684,20 +688,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[68] = {
+	[69] = {
 	.act_hid = BNXT_ULP_ACT_HID_040d,
 	.act_sig = { .bits =
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[69] = {
+	[70] = {
 	.act_hid = BNXT_ULP_ACT_HID_040f,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[70] = {
+	[71] = {
 	.act_hid = BNXT_ULP_ACT_HID_0413,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DROP |
@@ -705,13 +709,6 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[71] = {
-	.act_hid = BNXT_ULP_ACT_HID_0c0d,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
 	[72] = {
 	.act_hid = BNXT_ULP_ACT_HID_0567,
 	.act_sig = { .bits =
@@ -737,14 +734,6 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 6
 	},
 	[75] = {
-	.act_hid = BNXT_ULP_ACT_HID_0d0e,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_DEC_TTL |
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
-	[76] = {
 	.act_hid = BNXT_ULP_ACT_HID_0668,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -754,7 +743,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[77] = {
+	[76] = {
 	.act_hid = BNXT_ULP_ACT_HID_0b4a,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -763,14 +752,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[78] = {
+	[77] = {
 	.act_hid = BNXT_ULP_ACT_HID_0411,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[79] = {
+	[78] = {
 	.act_hid = BNXT_ULP_ACT_HID_056b,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -780,7 +769,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[80] = {
+	[79] = {
 	.act_hid = BNXT_ULP_ACT_HID_0a4d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -789,15 +778,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[81] = {
-	.act_hid = BNXT_ULP_ACT_HID_0c11,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_COUNT |
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
-	[82] = {
+	[80] = {
 	.act_hid = BNXT_ULP_ACT_HID_0512,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -805,16 +786,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[83] = {
-	.act_hid = BNXT_ULP_ACT_HID_0d12,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_COUNT |
-		BNXT_ULP_ACTION_BIT_DEC_TTL |
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
-	[84] = {
+	[81] = {
 	.act_hid = BNXT_ULP_ACT_HID_066c,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -825,7 +797,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[85] = {
+	[82] = {
 	.act_hid = BNXT_ULP_ACT_HID_0b4e,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -1064,7 +1036,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET,
@@ -1462,11 +1434,21 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {
-		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
+	.result_operand = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -2364,11 +2346,21 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {
-		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
+	.result_operand = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -2593,17 +2585,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT,
-	.result_operand = {
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index 1f650e0d7..3d133d2ff 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -11,36 +11,36 @@
 uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_CLASS_HID_0138] = 1,
 	[BNXT_ULP_CLASS_HID_03f0] = 2,
-	[BNXT_ULP_CLASS_HID_0134] = 3,
-	[BNXT_ULP_CLASS_HID_03fc] = 4,
-	[BNXT_ULP_CLASS_HID_0139] = 5,
-	[BNXT_ULP_CLASS_HID_03f1] = 6,
-	[BNXT_ULP_CLASS_HID_068b] = 7,
-	[BNXT_ULP_CLASS_HID_0143] = 8,
-	[BNXT_ULP_CLASS_HID_0135] = 9,
-	[BNXT_ULP_CLASS_HID_03fd] = 10,
-	[BNXT_ULP_CLASS_HID_0687] = 11,
-	[BNXT_ULP_CLASS_HID_014f] = 12,
-	[BNXT_ULP_CLASS_HID_0118] = 13,
-	[BNXT_ULP_CLASS_HID_03d0] = 14,
-	[BNXT_ULP_CLASS_HID_0114] = 15,
-	[BNXT_ULP_CLASS_HID_03dc] = 16,
-	[BNXT_ULP_CLASS_HID_0119] = 17,
-	[BNXT_ULP_CLASS_HID_03d1] = 18,
-	[BNXT_ULP_CLASS_HID_06ab] = 19,
-	[BNXT_ULP_CLASS_HID_0163] = 20,
-	[BNXT_ULP_CLASS_HID_0115] = 21,
-	[BNXT_ULP_CLASS_HID_03dd] = 22,
-	[BNXT_ULP_CLASS_HID_06a7] = 23,
-	[BNXT_ULP_CLASS_HID_016f] = 24,
-	[BNXT_ULP_CLASS_HID_0128] = 25,
-	[BNXT_ULP_CLASS_HID_03e0] = 26,
-	[BNXT_ULP_CLASS_HID_0124] = 27,
-	[BNXT_ULP_CLASS_HID_03ec] = 28,
-	[BNXT_ULP_CLASS_HID_0129] = 29,
-	[BNXT_ULP_CLASS_HID_03e1] = 30,
-	[BNXT_ULP_CLASS_HID_069b] = 31,
-	[BNXT_ULP_CLASS_HID_0153] = 32,
+	[BNXT_ULP_CLASS_HID_0139] = 3,
+	[BNXT_ULP_CLASS_HID_03f1] = 4,
+	[BNXT_ULP_CLASS_HID_068b] = 5,
+	[BNXT_ULP_CLASS_HID_0143] = 6,
+	[BNXT_ULP_CLASS_HID_0118] = 7,
+	[BNXT_ULP_CLASS_HID_03d0] = 8,
+	[BNXT_ULP_CLASS_HID_0119] = 9,
+	[BNXT_ULP_CLASS_HID_03d1] = 10,
+	[BNXT_ULP_CLASS_HID_06ab] = 11,
+	[BNXT_ULP_CLASS_HID_0163] = 12,
+	[BNXT_ULP_CLASS_HID_0128] = 13,
+	[BNXT_ULP_CLASS_HID_03e0] = 14,
+	[BNXT_ULP_CLASS_HID_0129] = 15,
+	[BNXT_ULP_CLASS_HID_03e1] = 16,
+	[BNXT_ULP_CLASS_HID_069b] = 17,
+	[BNXT_ULP_CLASS_HID_0153] = 18,
+	[BNXT_ULP_CLASS_HID_0134] = 19,
+	[BNXT_ULP_CLASS_HID_03fc] = 20,
+	[BNXT_ULP_CLASS_HID_0135] = 21,
+	[BNXT_ULP_CLASS_HID_03fd] = 22,
+	[BNXT_ULP_CLASS_HID_0687] = 23,
+	[BNXT_ULP_CLASS_HID_014f] = 24,
+	[BNXT_ULP_CLASS_HID_0114] = 25,
+	[BNXT_ULP_CLASS_HID_03dc] = 26,
+	[BNXT_ULP_CLASS_HID_0115] = 27,
+	[BNXT_ULP_CLASS_HID_03dd] = 28,
+	[BNXT_ULP_CLASS_HID_06a7] = 29,
+	[BNXT_ULP_CLASS_HID_016f] = 30,
+	[BNXT_ULP_CLASS_HID_0124] = 31,
+	[BNXT_ULP_CLASS_HID_03ec] = 32,
 	[BNXT_ULP_CLASS_HID_0125] = 33,
 	[BNXT_ULP_CLASS_HID_03ed] = 34,
 	[BNXT_ULP_CLASS_HID_0697] = 35,
@@ -153,36 +153,36 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_CLASS_HID_077f] = 142,
 	[BNXT_ULP_CLASS_HID_01e1] = 143,
 	[BNXT_ULP_CLASS_HID_0329] = 144,
-	[BNXT_ULP_CLASS_HID_01dd] = 145,
-	[BNXT_ULP_CLASS_HID_0315] = 146,
-	[BNXT_ULP_CLASS_HID_01c1] = 147,
-	[BNXT_ULP_CLASS_HID_0309] = 148,
-	[BNXT_ULP_CLASS_HID_003d] = 149,
-	[BNXT_ULP_CLASS_HID_02f5] = 150,
-	[BNXT_ULP_CLASS_HID_01d1] = 151,
-	[BNXT_ULP_CLASS_HID_0319] = 152,
-	[BNXT_ULP_CLASS_HID_01cd] = 153,
-	[BNXT_ULP_CLASS_HID_0305] = 154,
-	[BNXT_ULP_CLASS_HID_01e2] = 155,
-	[BNXT_ULP_CLASS_HID_032a] = 156,
-	[BNXT_ULP_CLASS_HID_0650] = 157,
-	[BNXT_ULP_CLASS_HID_0198] = 158,
-	[BNXT_ULP_CLASS_HID_01de] = 159,
-	[BNXT_ULP_CLASS_HID_0316] = 160,
-	[BNXT_ULP_CLASS_HID_066c] = 161,
-	[BNXT_ULP_CLASS_HID_01a4] = 162,
-	[BNXT_ULP_CLASS_HID_01c2] = 163,
-	[BNXT_ULP_CLASS_HID_030a] = 164,
-	[BNXT_ULP_CLASS_HID_0670] = 165,
-	[BNXT_ULP_CLASS_HID_01b8] = 166,
-	[BNXT_ULP_CLASS_HID_003e] = 167,
-	[BNXT_ULP_CLASS_HID_02f6] = 168,
-	[BNXT_ULP_CLASS_HID_078c] = 169,
-	[BNXT_ULP_CLASS_HID_0044] = 170,
-	[BNXT_ULP_CLASS_HID_01d2] = 171,
-	[BNXT_ULP_CLASS_HID_031a] = 172,
-	[BNXT_ULP_CLASS_HID_0660] = 173,
-	[BNXT_ULP_CLASS_HID_01a8] = 174,
+	[BNXT_ULP_CLASS_HID_01c1] = 145,
+	[BNXT_ULP_CLASS_HID_0309] = 146,
+	[BNXT_ULP_CLASS_HID_01d1] = 147,
+	[BNXT_ULP_CLASS_HID_0319] = 148,
+	[BNXT_ULP_CLASS_HID_01e2] = 149,
+	[BNXT_ULP_CLASS_HID_032a] = 150,
+	[BNXT_ULP_CLASS_HID_0650] = 151,
+	[BNXT_ULP_CLASS_HID_0198] = 152,
+	[BNXT_ULP_CLASS_HID_01c2] = 153,
+	[BNXT_ULP_CLASS_HID_030a] = 154,
+	[BNXT_ULP_CLASS_HID_0670] = 155,
+	[BNXT_ULP_CLASS_HID_01b8] = 156,
+	[BNXT_ULP_CLASS_HID_01d2] = 157,
+	[BNXT_ULP_CLASS_HID_031a] = 158,
+	[BNXT_ULP_CLASS_HID_0660] = 159,
+	[BNXT_ULP_CLASS_HID_01a8] = 160,
+	[BNXT_ULP_CLASS_HID_01dd] = 161,
+	[BNXT_ULP_CLASS_HID_0315] = 162,
+	[BNXT_ULP_CLASS_HID_003d] = 163,
+	[BNXT_ULP_CLASS_HID_02f5] = 164,
+	[BNXT_ULP_CLASS_HID_01cd] = 165,
+	[BNXT_ULP_CLASS_HID_0305] = 166,
+	[BNXT_ULP_CLASS_HID_01de] = 167,
+	[BNXT_ULP_CLASS_HID_0316] = 168,
+	[BNXT_ULP_CLASS_HID_066c] = 169,
+	[BNXT_ULP_CLASS_HID_01a4] = 170,
+	[BNXT_ULP_CLASS_HID_003e] = 171,
+	[BNXT_ULP_CLASS_HID_02f6] = 172,
+	[BNXT_ULP_CLASS_HID_078c] = 173,
+	[BNXT_ULP_CLASS_HID_0044] = 174,
 	[BNXT_ULP_CLASS_HID_01ce] = 175,
 	[BNXT_ULP_CLASS_HID_0306] = 176,
 	[BNXT_ULP_CLASS_HID_067c] = 177,
@@ -218,10 +218,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 1
 	},
 	[3] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0134,
+	.class_hid = BNXT_ULP_CLASS_HID_0139,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -232,10 +233,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 2
 	},
 	[4] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03fc,
+	.class_hid = BNXT_ULP_CLASS_HID_03f1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -245,7 +247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 3
 	},
 	[5] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0139,
+	.class_hid = BNXT_ULP_CLASS_HID_068b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
@@ -255,12 +257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 4
 	},
 	[6] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03f1,
+	.class_hid = BNXT_ULP_CLASS_HID_0143,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
@@ -269,47 +272,47 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 5
 	},
 	[7] = {
-	.class_hid = BNXT_ULP_CLASS_HID_068b,
+	.class_hid = BNXT_ULP_CLASS_HID_0118,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 6
 	},
 	[8] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0143,
+	.class_hid = BNXT_ULP_CLASS_HID_03d0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 7
 	},
 	[9] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0135,
+	.class_hid = BNXT_ULP_CLASS_HID_0119,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -320,11 +323,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 8
 	},
 	[10] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03fd,
+	.class_hid = BNXT_ULP_CLASS_HID_03d1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -334,11 +338,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 9
 	},
 	[11] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0687,
+	.class_hid = BNXT_ULP_CLASS_HID_06ab,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -350,11 +355,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 10
 	},
 	[12] = {
-	.class_hid = BNXT_ULP_CLASS_HID_014f,
+	.class_hid = BNXT_ULP_CLASS_HID_0163,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -365,11 +371,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 11
 	},
 	[13] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0118,
+	.class_hid = BNXT_ULP_CLASS_HID_0128,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -380,11 +386,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 12
 	},
 	[14] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03d0,
+	.class_hid = BNXT_ULP_CLASS_HID_03e0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -394,11 +400,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 13
 	},
 	[15] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0114,
+	.class_hid = BNXT_ULP_CLASS_HID_0129,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -409,11 +416,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 14
 	},
 	[16] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03dc,
+	.class_hid = BNXT_ULP_CLASS_HID_03e1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -423,254 +431,246 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 15
 	},
 	[17] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0119,
+	.class_hid = BNXT_ULP_CLASS_HID_069b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 16
 	},
 	[18] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03d1,
+	.class_hid = BNXT_ULP_CLASS_HID_0153,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 17
 	},
 	[19] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06ab,
+	.class_hid = BNXT_ULP_CLASS_HID_0134,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 18
+	.class_tid = 7,
+	.wc_pri = 0
 	},
 	[20] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0163,
+	.class_hid = BNXT_ULP_CLASS_HID_03fc,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 19
+	.class_tid = 7,
+	.wc_pri = 1
 	},
 	[21] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0115,
+	.class_hid = BNXT_ULP_CLASS_HID_0135,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 20
+	.class_tid = 7,
+	.wc_pri = 2
 	},
 	[22] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03dd,
+	.class_hid = BNXT_ULP_CLASS_HID_03fd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 21
+	.class_tid = 7,
+	.wc_pri = 3
 	},
 	[23] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06a7,
+	.class_hid = BNXT_ULP_CLASS_HID_0687,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 22
+	.class_tid = 7,
+	.wc_pri = 4
 	},
 	[24] = {
-	.class_hid = BNXT_ULP_CLASS_HID_016f,
+	.class_hid = BNXT_ULP_CLASS_HID_014f,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 23
+	.class_tid = 7,
+	.wc_pri = 5
 	},
 	[25] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0128,
+	.class_hid = BNXT_ULP_CLASS_HID_0114,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 24
+	.class_tid = 7,
+	.wc_pri = 6
 	},
 	[26] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03e0,
+	.class_hid = BNXT_ULP_CLASS_HID_03dc,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 25
+	.class_tid = 7,
+	.wc_pri = 7
 	},
 	[27] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0124,
+	.class_hid = BNXT_ULP_CLASS_HID_0115,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 26
+	.class_tid = 7,
+	.wc_pri = 8
 	},
 	[28] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03ec,
+	.class_hid = BNXT_ULP_CLASS_HID_03dd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 27
+	.class_tid = 7,
+	.wc_pri = 9
 	},
 	[29] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0129,
+	.class_hid = BNXT_ULP_CLASS_HID_06a7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 28
+	.class_tid = 7,
+	.wc_pri = 10
 	},
 	[30] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03e1,
+	.class_hid = BNXT_ULP_CLASS_HID_016f,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 29
+	.class_tid = 7,
+	.wc_pri = 11
 	},
 	[31] = {
-	.class_hid = BNXT_ULP_CLASS_HID_069b,
+	.class_hid = BNXT_ULP_CLASS_HID_0124,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 30
+	.class_tid = 7,
+	.wc_pri = 12
 	},
 	[32] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0153,
+	.class_hid = BNXT_ULP_CLASS_HID_03ec,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 31
+	.class_tid = 7,
+	.wc_pri = 13
 	},
 	[33] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0125,
@@ -681,12 +681,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 32
+	.class_tid = 7,
+	.wc_pri = 14
 	},
 	[34] = {
 	.class_hid = BNXT_ULP_CLASS_HID_03ed,
@@ -697,11 +697,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 33
+	.class_tid = 7,
+	.wc_pri = 15
 	},
 	[35] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0697,
@@ -712,13 +712,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 34
+	.class_tid = 7,
+	.wc_pri = 16
 	},
 	[36] = {
 	.class_hid = BNXT_ULP_CLASS_HID_015f,
@@ -729,12 +729,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 35
+	.class_tid = 7,
+	.wc_pri = 17
 	},
 	[37] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0452,
@@ -744,14 +744,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 0
 	},
 	[38] = {
@@ -762,13 +762,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 1
 	},
 	[39] = {
@@ -779,13 +779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 2
 	},
 	[40] = {
@@ -796,12 +796,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 3
 	},
 	[41] = {
@@ -812,14 +812,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 0
 	},
 	[42] = {
@@ -830,13 +830,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 1
 	},
 	[43] = {
@@ -847,13 +847,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 2
 	},
 	[44] = {
@@ -864,12 +864,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 3
 	},
 	[45] = {
@@ -880,14 +880,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 0
 	},
 	[46] = {
@@ -898,13 +898,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 1
 	},
 	[47] = {
@@ -915,13 +915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 2
 	},
 	[48] = {
@@ -932,12 +932,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 3
 	},
 	[49] = {
@@ -948,14 +948,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 0
 	},
 	[50] = {
@@ -966,13 +966,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 1
 	},
 	[51] = {
@@ -983,13 +983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 2
 	},
 	[52] = {
@@ -1000,12 +1000,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 3
 	},
 	[53] = {
@@ -1016,15 +1016,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 0
 	},
 	[54] = {
@@ -1035,14 +1035,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 1
 	},
 	[55] = {
@@ -1053,14 +1053,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 2
 	},
 	[56] = {
@@ -1071,13 +1071,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 3
 	},
 	[57] = {
@@ -1089,16 +1089,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 4
 	},
 	[58] = {
@@ -1110,15 +1110,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 5
 	},
 	[59] = {
@@ -1130,15 +1130,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 6
 	},
 	[60] = {
@@ -1150,14 +1150,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 7
 	},
 	[61] = {
@@ -1169,15 +1169,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 8
 	},
 	[62] = {
@@ -1189,14 +1189,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 9
 	},
 	[63] = {
@@ -1208,14 +1208,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 10
 	},
 	[64] = {
@@ -1227,13 +1227,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 11
 	},
 	[65] = {
@@ -1244,15 +1244,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 0
 	},
 	[66] = {
@@ -1263,14 +1263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 1
 	},
 	[67] = {
@@ -1281,14 +1281,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 2
 	},
 	[68] = {
@@ -1299,13 +1299,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 3
 	},
 	[69] = {
@@ -1317,16 +1317,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 4
 	},
 	[70] = {
@@ -1338,15 +1338,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 5
 	},
 	[71] = {
@@ -1358,15 +1358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 6
 	},
 	[72] = {
@@ -1378,14 +1378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 7
 	},
 	[73] = {
@@ -1397,15 +1397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 8
 	},
 	[74] = {
@@ -1417,14 +1417,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 9
 	},
 	[75] = {
@@ -1436,14 +1436,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 10
 	},
 	[76] = {
@@ -1455,13 +1455,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 11
 	},
 	[77] = {
@@ -1472,15 +1472,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 0
 	},
 	[78] = {
@@ -1491,14 +1491,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 1
 	},
 	[79] = {
@@ -1509,14 +1509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 2
 	},
 	[80] = {
@@ -1527,13 +1527,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 3
 	},
 	[81] = {
@@ -1545,16 +1545,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 4
 	},
 	[82] = {
@@ -1566,15 +1566,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 5
 	},
 	[83] = {
@@ -1586,15 +1586,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 6
 	},
 	[84] = {
@@ -1606,14 +1606,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 7
 	},
 	[85] = {
@@ -1625,15 +1625,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 8
 	},
 	[86] = {
@@ -1645,14 +1645,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 9
 	},
 	[87] = {
@@ -1664,14 +1664,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 10
 	},
 	[88] = {
@@ -1683,13 +1683,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 11
 	},
 	[89] = {
@@ -1700,15 +1700,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 0
 	},
 	[90] = {
@@ -1719,14 +1719,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 1
 	},
 	[91] = {
@@ -1737,14 +1737,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 2
 	},
 	[92] = {
@@ -1755,13 +1755,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 3
 	},
 	[93] = {
@@ -1773,16 +1773,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 4
 	},
 	[94] = {
@@ -1794,15 +1794,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 5
 	},
 	[95] = {
@@ -1814,15 +1814,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 6
 	},
 	[96] = {
@@ -1834,14 +1834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 7
 	},
 	[97] = {
@@ -1853,15 +1853,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 8
 	},
 	[98] = {
@@ -1873,14 +1873,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 9
 	},
 	[99] = {
@@ -1892,14 +1892,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 10
 	},
 	[100] = {
@@ -1911,13 +1911,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 11
 	},
 	[101] = {
@@ -1932,19 +1932,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_I_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF15_BITMASK_I_ETH_TYPE |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT |
-		BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF16_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
+		BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 15,
+	.class_tid = 16,
 	.wc_pri = 0
 	},
 	[102] = {
@@ -1959,17 +1959,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_I_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT |
-		BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
+		BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 15,
+	.class_tid = 16,
 	.wc_pri = 1
 	},
 	[103] = {
@@ -1981,14 +1981,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 0
 	},
 	[104] = {
@@ -2000,13 +2000,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 1
 	},
 	[105] = {
@@ -2018,13 +2018,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 2
 	},
 	[106] = {
@@ -2036,12 +2036,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 3
 	},
 	[107] = {
@@ -2053,13 +2053,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 4
 	},
 	[108] = {
@@ -2071,12 +2071,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 5
 	},
 	[109] = {
@@ -2088,12 +2088,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 6
 	},
 	[110] = {
@@ -2105,11 +2105,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 7
 	},
 	[111] = {
@@ -2122,15 +2122,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 8
 	},
 	[112] = {
@@ -2143,14 +2143,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 9
 	},
 	[113] = {
@@ -2163,14 +2163,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 10
 	},
 	[114] = {
@@ -2183,13 +2183,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 11
 	},
 	[115] = {
@@ -2202,14 +2202,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 12
 	},
 	[116] = {
@@ -2222,13 +2222,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 13
 	},
 	[117] = {
@@ -2241,13 +2241,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 14
 	},
 	[118] = {
@@ -2260,12 +2260,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 15
 	},
 	[119] = {
@@ -2278,14 +2278,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 16
 	},
 	[120] = {
@@ -2298,13 +2298,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 17
 	},
 	[121] = {
@@ -2317,13 +2317,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 18
 	},
 	[122] = {
@@ -2336,12 +2336,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 19
 	},
 	[123] = {
@@ -2354,13 +2354,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 20
 	},
 	[124] = {
@@ -2373,12 +2373,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 21
 	},
 	[125] = {
@@ -2391,12 +2391,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 22
 	},
 	[126] = {
@@ -2409,11 +2409,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 23
 	},
 	[127] = {
@@ -2424,14 +2424,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 0
 	},
 	[128] = {
@@ -2442,13 +2442,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 1
 	},
 	[129] = {
@@ -2459,13 +2459,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 2
 	},
 	[130] = {
@@ -2476,12 +2476,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 3
 	},
 	[131] = {
@@ -2492,14 +2492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 0
 	},
 	[132] = {
@@ -2510,13 +2510,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 1
 	},
 	[133] = {
@@ -2527,13 +2527,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 2
 	},
 	[134] = {
@@ -2544,12 +2544,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 3
 	},
 	[135] = {
@@ -2560,14 +2560,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 0
 	},
 	[136] = {
@@ -2578,13 +2578,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 1
 	},
 	[137] = {
@@ -2595,13 +2595,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 2
 	},
 	[138] = {
@@ -2612,12 +2612,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 3
 	},
 	[139] = {
@@ -2628,14 +2628,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 0
 	},
 	[140] = {
@@ -2646,13 +2646,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 1
 	},
 	[141] = {
@@ -2663,13 +2663,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 2
 	},
 	[142] = {
@@ -2680,12 +2680,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 3
 	},
 	[143] = {
@@ -2695,11 +2695,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 0
 	},
 	[144] = {
@@ -2709,466 +2709,466 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 1
 	},
 	[145] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01dd,
+	.class_hid = BNXT_ULP_CLASS_HID_01c1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 2
 	},
 	[146] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0315,
+	.class_hid = BNXT_ULP_CLASS_HID_0309,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 3
 	},
 	[147] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01c1,
+	.class_hid = BNXT_ULP_CLASS_HID_01d1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 4
 	},
 	[148] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0309,
+	.class_hid = BNXT_ULP_CLASS_HID_0319,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 5
 	},
 	[149] = {
-	.class_hid = BNXT_ULP_CLASS_HID_003d,
+	.class_hid = BNXT_ULP_CLASS_HID_01e2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 6
 	},
 	[150] = {
-	.class_hid = BNXT_ULP_CLASS_HID_02f5,
+	.class_hid = BNXT_ULP_CLASS_HID_032a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 7
 	},
 	[151] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01d1,
+	.class_hid = BNXT_ULP_CLASS_HID_0650,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 8
 	},
 	[152] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0319,
+	.class_hid = BNXT_ULP_CLASS_HID_0198,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 9
 	},
 	[153] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01cd,
+	.class_hid = BNXT_ULP_CLASS_HID_01c2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 10
 	},
 	[154] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0305,
+	.class_hid = BNXT_ULP_CLASS_HID_030a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 11
 	},
 	[155] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01e2,
+	.class_hid = BNXT_ULP_CLASS_HID_0670,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 12
 	},
 	[156] = {
-	.class_hid = BNXT_ULP_CLASS_HID_032a,
+	.class_hid = BNXT_ULP_CLASS_HID_01b8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 13
 	},
 	[157] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0650,
+	.class_hid = BNXT_ULP_CLASS_HID_01d2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 14
 	},
 	[158] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0198,
+	.class_hid = BNXT_ULP_CLASS_HID_031a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 15
 	},
 	[159] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01de,
+	.class_hid = BNXT_ULP_CLASS_HID_0660,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 16
 	},
 	[160] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0316,
+	.class_hid = BNXT_ULP_CLASS_HID_01a8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 17
 	},
 	[161] = {
-	.class_hid = BNXT_ULP_CLASS_HID_066c,
+	.class_hid = BNXT_ULP_CLASS_HID_01dd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 18
+	.class_tid = 23,
+	.wc_pri = 0
 	},
 	[162] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01a4,
+	.class_hid = BNXT_ULP_CLASS_HID_0315,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 19
+	.class_tid = 23,
+	.wc_pri = 1
 	},
 	[163] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01c2,
+	.class_hid = BNXT_ULP_CLASS_HID_003d,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 20
+	.class_tid = 23,
+	.wc_pri = 2
 	},
 	[164] = {
-	.class_hid = BNXT_ULP_CLASS_HID_030a,
+	.class_hid = BNXT_ULP_CLASS_HID_02f5,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 21
+	.class_tid = 23,
+	.wc_pri = 3
 	},
 	[165] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0670,
+	.class_hid = BNXT_ULP_CLASS_HID_01cd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 22
+	.class_tid = 23,
+	.wc_pri = 4
 	},
 	[166] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01b8,
+	.class_hid = BNXT_ULP_CLASS_HID_0305,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 23
+	.class_tid = 23,
+	.wc_pri = 5
 	},
 	[167] = {
-	.class_hid = BNXT_ULP_CLASS_HID_003e,
+	.class_hid = BNXT_ULP_CLASS_HID_01de,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 24
+	.class_tid = 23,
+	.wc_pri = 6
 	},
 	[168] = {
-	.class_hid = BNXT_ULP_CLASS_HID_02f6,
+	.class_hid = BNXT_ULP_CLASS_HID_0316,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 25
+	.class_tid = 23,
+	.wc_pri = 7
 	},
 	[169] = {
-	.class_hid = BNXT_ULP_CLASS_HID_078c,
+	.class_hid = BNXT_ULP_CLASS_HID_066c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 26
+	.class_tid = 23,
+	.wc_pri = 8
 	},
 	[170] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0044,
+	.class_hid = BNXT_ULP_CLASS_HID_01a4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 27
+	.class_tid = 23,
+	.wc_pri = 9
 	},
 	[171] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01d2,
+	.class_hid = BNXT_ULP_CLASS_HID_003e,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 28
+	.class_tid = 23,
+	.wc_pri = 10
 	},
 	[172] = {
-	.class_hid = BNXT_ULP_CLASS_HID_031a,
+	.class_hid = BNXT_ULP_CLASS_HID_02f6,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 29
+	.class_tid = 23,
+	.wc_pri = 11
 	},
 	[173] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0660,
+	.class_hid = BNXT_ULP_CLASS_HID_078c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 30
+	.class_tid = 23,
+	.wc_pri = 12
 	},
 	[174] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01a8,
+	.class_hid = BNXT_ULP_CLASS_HID_0044,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 31
+	.class_tid = 23,
+	.wc_pri = 13
 	},
 	[175] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01ce,
@@ -3179,12 +3179,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 32
+	.class_tid = 23,
+	.wc_pri = 14
 	},
 	[176] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0306,
@@ -3195,11 +3195,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 33
+	.class_tid = 23,
+	.wc_pri = 15
 	},
 	[177] = {
 	.class_hid = BNXT_ULP_CLASS_HID_067c,
@@ -3210,13 +3210,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 34
+	.class_tid = 23,
+	.wc_pri = 16
 	},
 	[178] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b4,
@@ -3227,12 +3227,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 35
+	.class_tid = 23,
+	.wc_pri = 17
 	}
 };
 
@@ -3282,7 +3282,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 	[((7 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 5,
+	.num_tbls = 4,
 	.start_tbl_idx = 32,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
@@ -3290,28 +3290,28 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 37,
+	.start_tbl_idx = 36,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((9 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 42,
+	.start_tbl_idx = 41,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((10 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 47,
+	.start_tbl_idx = 46,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((11 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 4,
-	.start_tbl_idx = 52,
+	.num_tbls = 5,
+	.start_tbl_idx = 51,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((12 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
@@ -3352,7 +3352,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 	[((17 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 5,
+	.num_tbls = 4,
 	.start_tbl_idx = 76,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
@@ -3360,28 +3360,42 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 81,
+	.start_tbl_idx = 80,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((19 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 86,
+	.start_tbl_idx = 85,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((20 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 91,
+	.start_tbl_idx = 90,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((21 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 5,
+	.start_tbl_idx = 95,
+	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
+	},
+	[((22 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 4,
+	.start_tbl_idx = 100,
+	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
+	},
+	[((23 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 96,
+	.start_tbl_idx = 104,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	}
 };
@@ -3580,7 +3594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+	.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_TX,
@@ -3883,38 +3897,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.key_start_idx = 177,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
 	.result_start_idx = 315,
-	.result_bit_size = 10,
-	.result_num_fields = 1,
-	.encap_num_fields = 0,
-	.ident_start_idx = 5,
-	.ident_nums = 1
-	},
-	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 178,
-	.blob_key_bit_size = 167,
-	.key_bit_size = 167,
-	.key_num_fields = 13,
-	.result_start_idx = 316,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 6,
-	.ident_nums = 0,
+	.ident_start_idx = 5,
+	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -3924,11 +3921,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 191,
+	.key_start_idx = 190,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 329,
+	.result_start_idx = 328,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3939,13 +3936,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 194,
+	.key_start_idx = 193,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 330,
+	.result_start_idx = 329,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -3958,11 +3955,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 236,
+	.key_start_idx = 235,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 338,
+	.result_start_idx = 337,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -3977,11 +3974,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 247,
+	.key_start_idx = 246,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 347,
+	.result_start_idx = 346,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3994,11 +3991,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 248,
+	.key_start_idx = 247,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 348,
+	.result_start_idx = 347,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4013,11 +4010,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 261,
+	.key_start_idx = 260,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 361,
+	.result_start_idx = 360,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4030,11 +4027,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 264,
+	.key_start_idx = 263,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 362,
+	.result_start_idx = 361,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4047,11 +4044,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 306,
+	.key_start_idx = 305,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 370,
+	.result_start_idx = 369,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4066,11 +4063,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 317,
+	.key_start_idx = 316,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 379,
+	.result_start_idx = 378,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4083,11 +4080,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 318,
+	.key_start_idx = 317,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 380,
+	.result_start_idx = 379,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4102,11 +4099,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 331,
+	.key_start_idx = 330,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 393,
+	.result_start_idx = 392,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4119,11 +4116,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 334,
+	.key_start_idx = 333,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 394,
+	.result_start_idx = 393,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4136,11 +4133,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 376,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.key_start_idx = 375,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 402,
+	.result_start_idx = 401,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4155,11 +4152,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 387,
+	.key_start_idx = 386,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 411,
+	.result_start_idx = 410,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4172,11 +4169,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 388,
+	.key_start_idx = 387,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 412,
+	.result_start_idx = 411,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4191,11 +4188,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 401,
+	.key_start_idx = 400,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 425,
+	.result_start_idx = 424,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4208,11 +4205,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 404,
+	.key_start_idx = 403,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 426,
+	.result_start_idx = 425,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4225,11 +4222,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 446,
+	.key_start_idx = 445,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 434,
+	.result_start_idx = 433,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4239,11 +4236,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 456,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 442,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 13,
+	.ident_nums = 1
+	},
+	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.key_start_idx = 457,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -4252,8 +4266,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 13,
-	.ident_nums = 1,
+	.ident_start_idx = 14,
+	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -4298,8 +4312,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 515,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 465,
 	.result_bit_size = 64,
@@ -4514,8 +4528,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 722,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 558,
 	.result_bit_size = 64,
@@ -4531,7 +4545,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.key_start_idx = 733,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -4586,8 +4600,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 791,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 589,
 	.result_bit_size = 64,
@@ -4603,7 +4617,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.key_start_idx = 802,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -4671,38 +4685,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 871,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
-	.result_start_idx = 629,
-	.result_bit_size = 10,
-	.result_num_fields = 1,
-	.encap_num_fields = 0,
-	.ident_start_idx = 25,
-	.ident_nums = 1
-	},
-	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_TX,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 872,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.key_start_idx = 871,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 630,
+	.result_start_idx = 629,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 26,
-	.ident_nums = 0,
+	.ident_start_idx = 25,
+	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -4711,12 +4708,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 885,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 884,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 643,
+	.result_start_idx = 642,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4726,14 +4723,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-	.direction = TF_DIR_TX,
+	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 888,
+	.key_start_idx = 887,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 644,
+	.result_start_idx = 643,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4745,12 +4742,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 930,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 929,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 652,
+	.result_start_idx = 651,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4765,11 +4762,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 941,
+	.key_start_idx = 940,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 661,
+	.result_start_idx = 660,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4782,11 +4779,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 942,
+	.key_start_idx = 941,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 662,
+	.result_start_idx = 661,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4801,11 +4798,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 955,
+	.key_start_idx = 954,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 675,
+	.result_start_idx = 674,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4818,11 +4815,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 958,
+	.key_start_idx = 957,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 676,
+	.result_start_idx = 675,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4835,11 +4832,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1000,
+	.key_start_idx = 999,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 684,
+	.result_start_idx = 683,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4854,11 +4851,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1011,
+	.key_start_idx = 1010,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 693,
+	.result_start_idx = 692,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4871,11 +4868,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1012,
+	.key_start_idx = 1011,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 694,
+	.result_start_idx = 693,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4890,11 +4887,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1025,
+	.key_start_idx = 1024,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 707,
+	.result_start_idx = 706,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4907,11 +4904,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1028,
+	.key_start_idx = 1027,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 708,
+	.result_start_idx = 707,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4924,11 +4921,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1070,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.key_start_idx = 1069,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 716,
+	.result_start_idx = 715,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4943,11 +4940,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1081,
+	.key_start_idx = 1080,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 725,
+	.result_start_idx = 724,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4960,11 +4957,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1082,
+	.key_start_idx = 1081,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 726,
+	.result_start_idx = 725,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4979,11 +4976,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1095,
+	.key_start_idx = 1094,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 739,
+	.result_start_idx = 738,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4996,11 +4993,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1098,
+	.key_start_idx = 1097,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 740,
+	.result_start_idx = 739,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -5013,11 +5010,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1140,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.key_start_idx = 1139,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 748,
+	.result_start_idx = 747,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -5027,11 +5024,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1150,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 756,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 33,
+	.ident_nums = 1
+	},
+	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.key_start_idx = 1151,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -5040,8 +5054,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
-	.ident_nums = 1,
+	.ident_start_idx = 34,
+	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -5086,50 +5100,194 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
 	.key_start_idx = 1209,
-	.blob_key_bit_size = 104,
-	.key_bit_size = 104,
-	.key_num_fields = 7,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
+	.key_num_fields = 11,
 	.result_start_idx = 779,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
 	.ident_start_idx = 35,
 	.ident_nums = 0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
-	}
-};
-
-struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+	},
 	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_TX,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
+	.key_start_idx = 1220,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 788,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 35,
+	.ident_nums = 1,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
 	{
-	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1233,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 801,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 36,
+	.ident_nums = 1
 	},
 	{
-	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_TX,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.key_start_idx = 1236,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 42,
+	.result_start_idx = 802,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 37,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
 	{
-	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
+	.resource_type = TF_MEM_INTERNAL,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1278,
+	.blob_key_bit_size = 104,
+	.key_bit_size = 104,
+	.key_num_fields = 7,
+	.result_start_idx = 810,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 37,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_TX,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
+	.key_start_idx = 1285,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 819,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 37,
+	.ident_nums = 1,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1298,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 832,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 38,
+	.ident_nums = 1
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_TX,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.key_start_idx = 1301,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 42,
+	.result_start_idx = 833,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
+	.resource_type = TF_MEM_INTERNAL,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1343,
+	.blob_key_bit_size = 104,
+	.key_bit_size = 104,
+	.key_num_fields = 7,
+	.result_start_idx = 841,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	}
+};
+
+struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
 	.spec_operand = {
@@ -5947,19 +6105,930 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 1,
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L2_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 9,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF6_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF6_IDX_O_ETH_SMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF7_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF7_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF7_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF7_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF7_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF7_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF7_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF7_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L2_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 9,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF7_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF7_IDX_O_ETH_SMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L3_HDR_ISIP_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-	},
-	{
-	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -6142,8 +7211,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6188,39 +7257,58 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF8_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF8_IDX_O_UDP_DST_PORT & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF6_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF6_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
@@ -6250,8 +7338,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6274,14 +7362,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6369,11 +7457,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -6643,8 +7727,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF7_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF7_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF9_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF9_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6653,8 +7737,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF7_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF7_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6663,7 +7747,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		BNXT_ULP_SYM_IP_PROTO_TCP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6672,8 +7756,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF7_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF7_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6682,8 +7766,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF7_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF7_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6722,8 +7806,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6746,14 +7830,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -6841,7 +7925,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -6881,7 +7969,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -7111,8 +8203,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF8_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF8_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF10_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF10_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7121,8 +8213,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF8_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF8_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7131,27 +8223,27 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_TCP,
+		BNXT_ULP_SYM_IP_PROTO_UDP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7190,8 +8282,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7214,14 +8306,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7309,11 +8401,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -7587,8 +8675,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF9_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF9_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF11_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF11_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7597,8 +8685,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7607,7 +8695,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		BNXT_ULP_SYM_IP_PROTO_TCP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7616,8 +8704,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF9_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF9_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7626,8 +8714,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF9_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF9_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7662,12 +8750,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7677,27 +8770,32 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7723,8 +8821,15 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 2,
@@ -7738,7 +8843,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -7760,8 +8867,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -7785,7 +8892,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -7825,11 +8936,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -8011,8 +9118,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8059,8 +9166,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF10_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF10_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF12_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8069,8 +9176,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF10_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF10_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8079,27 +9186,27 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_TCP,
+		BNXT_ULP_SYM_IP_PROTO_UDP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8137,14 +9244,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF11_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF11_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8157,14 +9264,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF11_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF11_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8172,14 +9279,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8276,11 +9383,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -8550,8 +9653,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF11_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF13_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8560,8 +9663,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF11_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8570,7 +9673,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		BNXT_ULP_SYM_IP_PROTO_TCP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8579,8 +9682,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF11_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8589,8 +9692,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF11_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF11_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8628,14 +9731,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8648,14 +9751,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8663,14 +9766,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -8767,7 +9870,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -8807,7 +9914,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -9037,8 +10148,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF12_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF14_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9047,8 +10158,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF12_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9057,27 +10168,27 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_TCP,
+		BNXT_ULP_SYM_IP_PROTO_UDP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9115,14 +10226,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF15_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF15_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9135,14 +10246,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9150,14 +10261,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9254,11 +10365,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -9532,8 +10639,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF13_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF15_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9542,8 +10649,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF13_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9552,27 +10659,27 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		BNXT_ULP_SYM_IP_PROTO_TCP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF13_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF13_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF13_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9608,18 +10715,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.mask_operand = {
-		(BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 12,
@@ -9630,14 +10727,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9645,14 +10742,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9678,15 +10775,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
@@ -9695,7 +10785,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -9724,8 +10816,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9749,7 +10841,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -9789,11 +10885,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -9820,7 +10912,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -9862,12 +10956,16 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -9875,7 +10973,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -9884,12 +10986,20 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -9897,7 +11007,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -9916,12 +11030,16 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -9929,7 +11047,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -9938,17 +11060,23 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -9956,7 +11084,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -9975,8 +11107,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10023,8 +11155,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF14_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF16_IDX_I_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_I_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10033,27 +11165,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF14_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_TCP,
+		(BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10062,8 +11195,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10075,7 +11208,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF16_IDX_T_VXLAN_VNI >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_T_VXLAN_VNI & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 10,
@@ -10109,16 +11247,13 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.mask_operand = {
-		(BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10126,14 +11261,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10144,8 +11279,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -10163,9 +11308,16 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 4,
@@ -10176,9 +11328,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -10200,8 +11350,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10222,32 +11372,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -10266,28 +11402,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L3_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -10296,42 +11422,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L2_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 3,
@@ -10444,9 +11556,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -10491,8 +11601,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10537,52 +11647,36 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_I_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_I_UDP_DST_PORT & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_I_UDP_SRC_PORT & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_I_IPV4_PROTO_ID >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_I_IPV4_PROTO_ID & 0xff,
+		BNXT_ULP_SYM_IP_PROTO_UDP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_I_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_I_IPV4_SRC_ADDR & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 48,
@@ -10592,12 +11686,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF15_IDX_T_VXLAN_VNI >> 8) & 0xff,
-		BNXT_ULP_HF15_IDX_T_VXLAN_VNI & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 10,
@@ -10620,6 +11709,16 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
@@ -10631,28 +11730,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10668,18 +11760,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.mask_operand = {
-		(BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 48,
@@ -10693,22 +11775,19 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 2,
@@ -10734,8 +11813,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10756,18 +11835,32 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -10786,18 +11879,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -10816,26 +11919,6 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 3,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -10855,43 +11938,49 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+		BNXT_ULP_SYM_L2_HDR_VALID_YES,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 1,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_TL4_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -10910,28 +11999,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_TL3_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -10945,28 +12024,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_TL2_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -10985,8 +12054,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11031,12 +12100,22 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_O_UDP_DST_PORT & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 8,
@@ -11052,15 +12131,20 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 48,
@@ -11097,8 +12181,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11121,14 +12205,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11222,11 +12306,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -11486,8 +12566,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF19_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11496,8 +12576,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11506,7 +12586,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		BNXT_ULP_SYM_IP_PROTO_TCP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11515,8 +12595,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11525,8 +12605,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11565,8 +12645,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11589,14 +12669,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11690,7 +12770,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -11730,7 +12814,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -11950,8 +13038,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11960,8 +13048,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11970,27 +13058,27 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_TCP,
+		BNXT_ULP_SYM_IP_PROTO_UDP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12029,8 +13117,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12053,14 +13141,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12154,11 +13242,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -12422,8 +13506,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12432,28 +13516,27 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV6_PROTO_ID >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV6_PROTO_ID & 0xff,
+		BNXT_ULP_SYM_IP_PROTO_TCP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12462,8 +13545,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12498,12 +13581,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF22_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12513,27 +13601,32 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF22_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_ETH_SMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF22_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_ETH_SMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12559,8 +13652,15 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 2,
@@ -12580,8 +13680,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -12602,8 +13706,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12624,28 +13728,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -12667,11 +13761,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -12703,7 +13793,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -12748,7 +13840,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -12768,7 +13862,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -12798,7 +13894,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -12823,7 +13921,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -12843,8 +13943,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12877,7 +13977,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 3,
+	.field_bit_size = 7,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -12889,63 +13989,24 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_TCP_DST_PORT & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-	},
-	{
-	.field_bit_size = 16,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_TCP_SRC_PORT & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-	},
-	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_TCP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 24,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 10,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
@@ -12969,14 +14030,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF21_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF23_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF23_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12989,14 +14050,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF21_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF23_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF23_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -13004,14 +14065,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -13138,21 +14199,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		BNXT_ULP_SYM_L3_HDR_ISIP_YES,
+		BNXT_ULP_SYM_L3_HDR_TYPE_IPV6,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 1,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -13390,8 +14451,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF23_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -13966,7 +15027,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 80,
+	.field_bit_size = 16,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -14738,16 +15799,192 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 1,
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.result_operand = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 6,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x0005 >> 8) & 0xff,
+		0x0005 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 33,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 11,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 1,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -14755,7 +15992,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 10,
@@ -16141,7 +17380,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16192,8 +17431,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16319,7 +17558,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16370,8 +17609,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17483,7 +18722,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17534,8 +18773,201 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 11,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF,
+	.result_operand = {
+		(BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_true = {
+		(BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_false = {
+		(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 6,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x0003 >> 8) & 0xff,
+		0x0003 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 33,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x0061 >> 8) & 0xff,
+		0x0061 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17999,5 +19431,33 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
 	.regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
 	.ident_bit_size = 10,
 	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
 	}
 };
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index f5c43a9f8..51758868a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -18,7 +18,7 @@
 #define BNXT_ULP_CLASS_HID_SHFTL 31
 #define BNXT_ULP_CLASS_HID_MASK 2047
 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 4096
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 83
 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
 #define BNXT_ULP_ACT_HID_HIGH_PRIME 4721
 #define BNXT_ULP_ACT_HID_SHFTR 23
@@ -218,7 +218,8 @@ enum bnxt_ulp_mapper_opc {
 	BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9,
 	BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10,
 	BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11,
-	BNXT_ULP_MAPPER_OPC_LAST = 12
+	BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12,
+	BNXT_ULP_MAPPER_OPC_LAST = 13
 };
 
 enum bnxt_ulp_mark_db_opcode {
@@ -632,36 +633,36 @@ enum bnxt_ulp_act_prop_idx {
 enum bnxt_ulp_class_hid {
 	BNXT_ULP_CLASS_HID_0138 = 0x0138,
 	BNXT_ULP_CLASS_HID_03f0 = 0x03f0,
-	BNXT_ULP_CLASS_HID_0134 = 0x0134,
-	BNXT_ULP_CLASS_HID_03fc = 0x03fc,
 	BNXT_ULP_CLASS_HID_0139 = 0x0139,
 	BNXT_ULP_CLASS_HID_03f1 = 0x03f1,
 	BNXT_ULP_CLASS_HID_068b = 0x068b,
 	BNXT_ULP_CLASS_HID_0143 = 0x0143,
-	BNXT_ULP_CLASS_HID_0135 = 0x0135,
-	BNXT_ULP_CLASS_HID_03fd = 0x03fd,
-	BNXT_ULP_CLASS_HID_0687 = 0x0687,
-	BNXT_ULP_CLASS_HID_014f = 0x014f,
 	BNXT_ULP_CLASS_HID_0118 = 0x0118,
 	BNXT_ULP_CLASS_HID_03d0 = 0x03d0,
-	BNXT_ULP_CLASS_HID_0114 = 0x0114,
-	BNXT_ULP_CLASS_HID_03dc = 0x03dc,
 	BNXT_ULP_CLASS_HID_0119 = 0x0119,
 	BNXT_ULP_CLASS_HID_03d1 = 0x03d1,
 	BNXT_ULP_CLASS_HID_06ab = 0x06ab,
 	BNXT_ULP_CLASS_HID_0163 = 0x0163,
-	BNXT_ULP_CLASS_HID_0115 = 0x0115,
-	BNXT_ULP_CLASS_HID_03dd = 0x03dd,
-	BNXT_ULP_CLASS_HID_06a7 = 0x06a7,
-	BNXT_ULP_CLASS_HID_016f = 0x016f,
 	BNXT_ULP_CLASS_HID_0128 = 0x0128,
 	BNXT_ULP_CLASS_HID_03e0 = 0x03e0,
-	BNXT_ULP_CLASS_HID_0124 = 0x0124,
-	BNXT_ULP_CLASS_HID_03ec = 0x03ec,
 	BNXT_ULP_CLASS_HID_0129 = 0x0129,
 	BNXT_ULP_CLASS_HID_03e1 = 0x03e1,
 	BNXT_ULP_CLASS_HID_069b = 0x069b,
 	BNXT_ULP_CLASS_HID_0153 = 0x0153,
+	BNXT_ULP_CLASS_HID_0134 = 0x0134,
+	BNXT_ULP_CLASS_HID_03fc = 0x03fc,
+	BNXT_ULP_CLASS_HID_0135 = 0x0135,
+	BNXT_ULP_CLASS_HID_03fd = 0x03fd,
+	BNXT_ULP_CLASS_HID_0687 = 0x0687,
+	BNXT_ULP_CLASS_HID_014f = 0x014f,
+	BNXT_ULP_CLASS_HID_0114 = 0x0114,
+	BNXT_ULP_CLASS_HID_03dc = 0x03dc,
+	BNXT_ULP_CLASS_HID_0115 = 0x0115,
+	BNXT_ULP_CLASS_HID_03dd = 0x03dd,
+	BNXT_ULP_CLASS_HID_06a7 = 0x06a7,
+	BNXT_ULP_CLASS_HID_016f = 0x016f,
+	BNXT_ULP_CLASS_HID_0124 = 0x0124,
+	BNXT_ULP_CLASS_HID_03ec = 0x03ec,
 	BNXT_ULP_CLASS_HID_0125 = 0x0125,
 	BNXT_ULP_CLASS_HID_03ed = 0x03ed,
 	BNXT_ULP_CLASS_HID_0697 = 0x0697,
@@ -774,36 +775,36 @@ enum bnxt_ulp_class_hid {
 	BNXT_ULP_CLASS_HID_077f = 0x077f,
 	BNXT_ULP_CLASS_HID_01e1 = 0x01e1,
 	BNXT_ULP_CLASS_HID_0329 = 0x0329,
-	BNXT_ULP_CLASS_HID_01dd = 0x01dd,
-	BNXT_ULP_CLASS_HID_0315 = 0x0315,
 	BNXT_ULP_CLASS_HID_01c1 = 0x01c1,
 	BNXT_ULP_CLASS_HID_0309 = 0x0309,
-	BNXT_ULP_CLASS_HID_003d = 0x003d,
-	BNXT_ULP_CLASS_HID_02f5 = 0x02f5,
 	BNXT_ULP_CLASS_HID_01d1 = 0x01d1,
 	BNXT_ULP_CLASS_HID_0319 = 0x0319,
-	BNXT_ULP_CLASS_HID_01cd = 0x01cd,
-	BNXT_ULP_CLASS_HID_0305 = 0x0305,
 	BNXT_ULP_CLASS_HID_01e2 = 0x01e2,
 	BNXT_ULP_CLASS_HID_032a = 0x032a,
 	BNXT_ULP_CLASS_HID_0650 = 0x0650,
 	BNXT_ULP_CLASS_HID_0198 = 0x0198,
-	BNXT_ULP_CLASS_HID_01de = 0x01de,
-	BNXT_ULP_CLASS_HID_0316 = 0x0316,
-	BNXT_ULP_CLASS_HID_066c = 0x066c,
-	BNXT_ULP_CLASS_HID_01a4 = 0x01a4,
 	BNXT_ULP_CLASS_HID_01c2 = 0x01c2,
 	BNXT_ULP_CLASS_HID_030a = 0x030a,
 	BNXT_ULP_CLASS_HID_0670 = 0x0670,
 	BNXT_ULP_CLASS_HID_01b8 = 0x01b8,
-	BNXT_ULP_CLASS_HID_003e = 0x003e,
-	BNXT_ULP_CLASS_HID_02f6 = 0x02f6,
-	BNXT_ULP_CLASS_HID_078c = 0x078c,
-	BNXT_ULP_CLASS_HID_0044 = 0x0044,
 	BNXT_ULP_CLASS_HID_01d2 = 0x01d2,
 	BNXT_ULP_CLASS_HID_031a = 0x031a,
 	BNXT_ULP_CLASS_HID_0660 = 0x0660,
 	BNXT_ULP_CLASS_HID_01a8 = 0x01a8,
+	BNXT_ULP_CLASS_HID_01dd = 0x01dd,
+	BNXT_ULP_CLASS_HID_0315 = 0x0315,
+	BNXT_ULP_CLASS_HID_003d = 0x003d,
+	BNXT_ULP_CLASS_HID_02f5 = 0x02f5,
+	BNXT_ULP_CLASS_HID_01cd = 0x01cd,
+	BNXT_ULP_CLASS_HID_0305 = 0x0305,
+	BNXT_ULP_CLASS_HID_01de = 0x01de,
+	BNXT_ULP_CLASS_HID_0316 = 0x0316,
+	BNXT_ULP_CLASS_HID_066c = 0x066c,
+	BNXT_ULP_CLASS_HID_01a4 = 0x01a4,
+	BNXT_ULP_CLASS_HID_003e = 0x003e,
+	BNXT_ULP_CLASS_HID_02f6 = 0x02f6,
+	BNXT_ULP_CLASS_HID_078c = 0x078c,
+	BNXT_ULP_CLASS_HID_0044 = 0x0044,
 	BNXT_ULP_CLASS_HID_01ce = 0x01ce,
 	BNXT_ULP_CLASS_HID_0306 = 0x0306,
 	BNXT_ULP_CLASS_HID_067c = 0x067c,
@@ -838,6 +839,7 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_0020 = 0x0020,
 	BNXT_ULP_ACT_HID_0901 = 0x0901,
 	BNXT_ULP_ACT_HID_0121 = 0x0121,
+	BNXT_ULP_ACT_HID_0004 = 0x0004,
 	BNXT_ULP_ACT_HID_0006 = 0x0006,
 	BNXT_ULP_ACT_HID_0804 = 0x0804,
 	BNXT_ULP_ACT_HID_0105 = 0x0105,
@@ -881,19 +883,15 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_040d = 0x040d,
 	BNXT_ULP_ACT_HID_040f = 0x040f,
 	BNXT_ULP_ACT_HID_0413 = 0x0413,
-	BNXT_ULP_ACT_HID_0c0d = 0x0c0d,
 	BNXT_ULP_ACT_HID_0567 = 0x0567,
 	BNXT_ULP_ACT_HID_0a49 = 0x0a49,
 	BNXT_ULP_ACT_HID_050e = 0x050e,
-	BNXT_ULP_ACT_HID_0d0e = 0x0d0e,
 	BNXT_ULP_ACT_HID_0668 = 0x0668,
 	BNXT_ULP_ACT_HID_0b4a = 0x0b4a,
 	BNXT_ULP_ACT_HID_0411 = 0x0411,
 	BNXT_ULP_ACT_HID_056b = 0x056b,
 	BNXT_ULP_ACT_HID_0a4d = 0x0a4d,
-	BNXT_ULP_ACT_HID_0c11 = 0x0c11,
 	BNXT_ULP_ACT_HID_0512 = 0x0512,
-	BNXT_ULP_ACT_HID_0d12 = 0x0d12,
 	BNXT_ULP_ACT_HID_066c = 0x066c,
 	BNXT_ULP_ACT_HID_0b4e = 0x0b4e
 };
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index a5bd3f646..79fcdeee8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -60,20 +60,14 @@ enum bnxt_ulp_hf7 {
 	BNXT_ULP_HF7_IDX_OI_VLAN_CFI_PRI         = 7,
 	BNXT_ULP_HF7_IDX_OI_VLAN_VID             = 8,
 	BNXT_ULP_HF7_IDX_OI_VLAN_TYPE            = 9,
-	BNXT_ULP_HF7_IDX_O_IPV4_VER              = 10,
-	BNXT_ULP_HF7_IDX_O_IPV4_TOS              = 11,
-	BNXT_ULP_HF7_IDX_O_IPV4_LEN              = 12,
-	BNXT_ULP_HF7_IDX_O_IPV4_FRAG_ID          = 13,
-	BNXT_ULP_HF7_IDX_O_IPV4_FRAG_OFF         = 14,
-	BNXT_ULP_HF7_IDX_O_IPV4_TTL              = 15,
-	BNXT_ULP_HF7_IDX_O_IPV4_PROTO_ID         = 16,
-	BNXT_ULP_HF7_IDX_O_IPV4_CSUM             = 17,
-	BNXT_ULP_HF7_IDX_O_IPV4_SRC_ADDR         = 18,
-	BNXT_ULP_HF7_IDX_O_IPV4_DST_ADDR         = 19,
-	BNXT_ULP_HF7_IDX_O_UDP_SRC_PORT          = 20,
-	BNXT_ULP_HF7_IDX_O_UDP_DST_PORT          = 21,
-	BNXT_ULP_HF7_IDX_O_UDP_LENGTH            = 22,
-	BNXT_ULP_HF7_IDX_O_UDP_CSUM              = 23
+	BNXT_ULP_HF7_IDX_O_IPV6_VER              = 10,
+	BNXT_ULP_HF7_IDX_O_IPV6_TC               = 11,
+	BNXT_ULP_HF7_IDX_O_IPV6_FLOW_LABEL       = 12,
+	BNXT_ULP_HF7_IDX_O_IPV6_PAYLOAD_LEN      = 13,
+	BNXT_ULP_HF7_IDX_O_IPV6_PROTO_ID         = 14,
+	BNXT_ULP_HF7_IDX_O_IPV6_TTL              = 15,
+	BNXT_ULP_HF7_IDX_O_IPV6_SRC_ADDR         = 16,
+	BNXT_ULP_HF7_IDX_O_IPV6_DST_ADDR         = 17
 };
 
 enum bnxt_ulp_hf8 {
@@ -97,15 +91,10 @@ enum bnxt_ulp_hf8 {
 	BNXT_ULP_HF8_IDX_O_IPV4_CSUM             = 17,
 	BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR         = 18,
 	BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR         = 19,
-	BNXT_ULP_HF8_IDX_O_TCP_SRC_PORT          = 20,
-	BNXT_ULP_HF8_IDX_O_TCP_DST_PORT          = 21,
-	BNXT_ULP_HF8_IDX_O_TCP_SENT_SEQ          = 22,
-	BNXT_ULP_HF8_IDX_O_TCP_RECV_ACK          = 23,
-	BNXT_ULP_HF8_IDX_O_TCP_DATA_OFF          = 24,
-	BNXT_ULP_HF8_IDX_O_TCP_TCP_FLAGS         = 25,
-	BNXT_ULP_HF8_IDX_O_TCP_RX_WIN            = 26,
-	BNXT_ULP_HF8_IDX_O_TCP_CSUM              = 27,
-	BNXT_ULP_HF8_IDX_O_TCP_URP               = 28
+	BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT          = 20,
+	BNXT_ULP_HF8_IDX_O_UDP_DST_PORT          = 21,
+	BNXT_ULP_HF8_IDX_O_UDP_LENGTH            = 22,
+	BNXT_ULP_HF8_IDX_O_UDP_CSUM              = 23
 };
 
 enum bnxt_ulp_hf9 {
@@ -119,18 +108,25 @@ enum bnxt_ulp_hf9 {
 	BNXT_ULP_HF9_IDX_OI_VLAN_CFI_PRI         = 7,
 	BNXT_ULP_HF9_IDX_OI_VLAN_VID             = 8,
 	BNXT_ULP_HF9_IDX_OI_VLAN_TYPE            = 9,
-	BNXT_ULP_HF9_IDX_O_IPV6_VER              = 10,
-	BNXT_ULP_HF9_IDX_O_IPV6_TC               = 11,
-	BNXT_ULP_HF9_IDX_O_IPV6_FLOW_LABEL       = 12,
-	BNXT_ULP_HF9_IDX_O_IPV6_PAYLOAD_LEN      = 13,
-	BNXT_ULP_HF9_IDX_O_IPV6_PROTO_ID         = 14,
-	BNXT_ULP_HF9_IDX_O_IPV6_TTL              = 15,
-	BNXT_ULP_HF9_IDX_O_IPV6_SRC_ADDR         = 16,
-	BNXT_ULP_HF9_IDX_O_IPV6_DST_ADDR         = 17,
-	BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT          = 18,
-	BNXT_ULP_HF9_IDX_O_UDP_DST_PORT          = 19,
-	BNXT_ULP_HF9_IDX_O_UDP_LENGTH            = 20,
-	BNXT_ULP_HF9_IDX_O_UDP_CSUM              = 21
+	BNXT_ULP_HF9_IDX_O_IPV4_VER              = 10,
+	BNXT_ULP_HF9_IDX_O_IPV4_TOS              = 11,
+	BNXT_ULP_HF9_IDX_O_IPV4_LEN              = 12,
+	BNXT_ULP_HF9_IDX_O_IPV4_FRAG_ID          = 13,
+	BNXT_ULP_HF9_IDX_O_IPV4_FRAG_OFF         = 14,
+	BNXT_ULP_HF9_IDX_O_IPV4_TTL              = 15,
+	BNXT_ULP_HF9_IDX_O_IPV4_PROTO_ID         = 16,
+	BNXT_ULP_HF9_IDX_O_IPV4_CSUM             = 17,
+	BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR         = 18,
+	BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR         = 19,
+	BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT          = 20,
+	BNXT_ULP_HF9_IDX_O_TCP_DST_PORT          = 21,
+	BNXT_ULP_HF9_IDX_O_TCP_SENT_SEQ          = 22,
+	BNXT_ULP_HF9_IDX_O_TCP_RECV_ACK          = 23,
+	BNXT_ULP_HF9_IDX_O_TCP_DATA_OFF          = 24,
+	BNXT_ULP_HF9_IDX_O_TCP_TCP_FLAGS         = 25,
+	BNXT_ULP_HF9_IDX_O_TCP_RX_WIN            = 26,
+	BNXT_ULP_HF9_IDX_O_TCP_CSUM              = 27,
+	BNXT_ULP_HF9_IDX_O_TCP_URP               = 28
 };
 
 enum bnxt_ulp_hf10 {
@@ -152,15 +148,10 @@ enum bnxt_ulp_hf10 {
 	BNXT_ULP_HF10_IDX_O_IPV6_TTL             = 15,
 	BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR        = 16,
 	BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF10_IDX_O_TCP_SRC_PORT         = 18,
-	BNXT_ULP_HF10_IDX_O_TCP_DST_PORT         = 19,
-	BNXT_ULP_HF10_IDX_O_TCP_SENT_SEQ         = 20,
-	BNXT_ULP_HF10_IDX_O_TCP_RECV_ACK         = 21,
-	BNXT_ULP_HF10_IDX_O_TCP_DATA_OFF         = 22,
-	BNXT_ULP_HF10_IDX_O_TCP_TCP_FLAGS        = 23,
-	BNXT_ULP_HF10_IDX_O_TCP_RX_WIN           = 24,
-	BNXT_ULP_HF10_IDX_O_TCP_CSUM             = 25,
-	BNXT_ULP_HF10_IDX_O_TCP_URP              = 26
+	BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT         = 18,
+	BNXT_ULP_HF10_IDX_O_UDP_DST_PORT         = 19,
+	BNXT_ULP_HF10_IDX_O_UDP_LENGTH           = 20,
+	BNXT_ULP_HF10_IDX_O_UDP_CSUM             = 21
 };
 
 enum bnxt_ulp_hf11 {
@@ -174,20 +165,23 @@ enum bnxt_ulp_hf11 {
 	BNXT_ULP_HF11_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF11_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF11_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF11_IDX_O_IPV4_VER             = 10,
-	BNXT_ULP_HF11_IDX_O_IPV4_TOS             = 11,
-	BNXT_ULP_HF11_IDX_O_IPV4_LEN             = 12,
-	BNXT_ULP_HF11_IDX_O_IPV4_FRAG_ID         = 13,
-	BNXT_ULP_HF11_IDX_O_IPV4_FRAG_OFF        = 14,
-	BNXT_ULP_HF11_IDX_O_IPV4_TTL             = 15,
-	BNXT_ULP_HF11_IDX_O_IPV4_PROTO_ID        = 16,
-	BNXT_ULP_HF11_IDX_O_IPV4_CSUM            = 17,
-	BNXT_ULP_HF11_IDX_O_IPV4_SRC_ADDR        = 18,
-	BNXT_ULP_HF11_IDX_O_IPV4_DST_ADDR        = 19,
-	BNXT_ULP_HF11_IDX_O_UDP_SRC_PORT         = 20,
-	BNXT_ULP_HF11_IDX_O_UDP_DST_PORT         = 21,
-	BNXT_ULP_HF11_IDX_O_UDP_LENGTH           = 22,
-	BNXT_ULP_HF11_IDX_O_UDP_CSUM             = 23
+	BNXT_ULP_HF11_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF11_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF11_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF11_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF11_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF11_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT         = 18,
+	BNXT_ULP_HF11_IDX_O_TCP_DST_PORT         = 19,
+	BNXT_ULP_HF11_IDX_O_TCP_SENT_SEQ         = 20,
+	BNXT_ULP_HF11_IDX_O_TCP_RECV_ACK         = 21,
+	BNXT_ULP_HF11_IDX_O_TCP_DATA_OFF         = 22,
+	BNXT_ULP_HF11_IDX_O_TCP_TCP_FLAGS        = 23,
+	BNXT_ULP_HF11_IDX_O_TCP_RX_WIN           = 24,
+	BNXT_ULP_HF11_IDX_O_TCP_CSUM             = 25,
+	BNXT_ULP_HF11_IDX_O_TCP_URP              = 26
 };
 
 enum bnxt_ulp_hf12 {
@@ -211,15 +205,10 @@ enum bnxt_ulp_hf12 {
 	BNXT_ULP_HF12_IDX_O_IPV4_CSUM            = 17,
 	BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR        = 18,
 	BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR        = 19,
-	BNXT_ULP_HF12_IDX_O_TCP_SRC_PORT         = 20,
-	BNXT_ULP_HF12_IDX_O_TCP_DST_PORT         = 21,
-	BNXT_ULP_HF12_IDX_O_TCP_SENT_SEQ         = 22,
-	BNXT_ULP_HF12_IDX_O_TCP_RECV_ACK         = 23,
-	BNXT_ULP_HF12_IDX_O_TCP_DATA_OFF         = 24,
-	BNXT_ULP_HF12_IDX_O_TCP_TCP_FLAGS        = 25,
-	BNXT_ULP_HF12_IDX_O_TCP_RX_WIN           = 26,
-	BNXT_ULP_HF12_IDX_O_TCP_CSUM             = 27,
-	BNXT_ULP_HF12_IDX_O_TCP_URP              = 28
+	BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT         = 20,
+	BNXT_ULP_HF12_IDX_O_UDP_DST_PORT         = 21,
+	BNXT_ULP_HF12_IDX_O_UDP_LENGTH           = 22,
+	BNXT_ULP_HF12_IDX_O_UDP_CSUM             = 23
 };
 
 enum bnxt_ulp_hf13 {
@@ -233,18 +222,25 @@ enum bnxt_ulp_hf13 {
 	BNXT_ULP_HF13_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF13_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF13_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF13_IDX_O_IPV6_VER             = 10,
-	BNXT_ULP_HF13_IDX_O_IPV6_TC              = 11,
-	BNXT_ULP_HF13_IDX_O_IPV6_FLOW_LABEL      = 12,
-	BNXT_ULP_HF13_IDX_O_IPV6_PAYLOAD_LEN     = 13,
-	BNXT_ULP_HF13_IDX_O_IPV6_PROTO_ID        = 14,
-	BNXT_ULP_HF13_IDX_O_IPV6_TTL             = 15,
-	BNXT_ULP_HF13_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF13_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF13_IDX_O_UDP_SRC_PORT         = 18,
-	BNXT_ULP_HF13_IDX_O_UDP_DST_PORT         = 19,
-	BNXT_ULP_HF13_IDX_O_UDP_LENGTH           = 20,
-	BNXT_ULP_HF13_IDX_O_UDP_CSUM             = 21
+	BNXT_ULP_HF13_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF13_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF13_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF13_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF13_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF13_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF13_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF13_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR        = 19,
+	BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT         = 20,
+	BNXT_ULP_HF13_IDX_O_TCP_DST_PORT         = 21,
+	BNXT_ULP_HF13_IDX_O_TCP_SENT_SEQ         = 22,
+	BNXT_ULP_HF13_IDX_O_TCP_RECV_ACK         = 23,
+	BNXT_ULP_HF13_IDX_O_TCP_DATA_OFF         = 24,
+	BNXT_ULP_HF13_IDX_O_TCP_TCP_FLAGS        = 25,
+	BNXT_ULP_HF13_IDX_O_TCP_RX_WIN           = 26,
+	BNXT_ULP_HF13_IDX_O_TCP_CSUM             = 27,
+	BNXT_ULP_HF13_IDX_O_TCP_URP              = 28
 };
 
 enum bnxt_ulp_hf14 {
@@ -266,15 +262,10 @@ enum bnxt_ulp_hf14 {
 	BNXT_ULP_HF14_IDX_O_IPV6_TTL             = 15,
 	BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR        = 16,
 	BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF14_IDX_O_TCP_SRC_PORT         = 18,
-	BNXT_ULP_HF14_IDX_O_TCP_DST_PORT         = 19,
-	BNXT_ULP_HF14_IDX_O_TCP_SENT_SEQ         = 20,
-	BNXT_ULP_HF14_IDX_O_TCP_RECV_ACK         = 21,
-	BNXT_ULP_HF14_IDX_O_TCP_DATA_OFF         = 22,
-	BNXT_ULP_HF14_IDX_O_TCP_TCP_FLAGS        = 23,
-	BNXT_ULP_HF14_IDX_O_TCP_RX_WIN           = 24,
-	BNXT_ULP_HF14_IDX_O_TCP_CSUM             = 25,
-	BNXT_ULP_HF14_IDX_O_TCP_URP              = 26
+	BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT         = 18,
+	BNXT_ULP_HF14_IDX_O_UDP_DST_PORT         = 19,
+	BNXT_ULP_HF14_IDX_O_UDP_LENGTH           = 20,
+	BNXT_ULP_HF14_IDX_O_UDP_CSUM             = 21
 };
 
 enum bnxt_ulp_hf15 {
@@ -288,47 +279,23 @@ enum bnxt_ulp_hf15 {
 	BNXT_ULP_HF15_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF15_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF15_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF15_IDX_O_IPV4_VER             = 10,
-	BNXT_ULP_HF15_IDX_O_IPV4_TOS             = 11,
-	BNXT_ULP_HF15_IDX_O_IPV4_LEN             = 12,
-	BNXT_ULP_HF15_IDX_O_IPV4_FRAG_ID         = 13,
-	BNXT_ULP_HF15_IDX_O_IPV4_FRAG_OFF        = 14,
-	BNXT_ULP_HF15_IDX_O_IPV4_TTL             = 15,
-	BNXT_ULP_HF15_IDX_O_IPV4_PROTO_ID        = 16,
-	BNXT_ULP_HF15_IDX_O_IPV4_CSUM            = 17,
-	BNXT_ULP_HF15_IDX_O_IPV4_SRC_ADDR        = 18,
-	BNXT_ULP_HF15_IDX_O_IPV4_DST_ADDR        = 19,
-	BNXT_ULP_HF15_IDX_O_UDP_SRC_PORT         = 20,
-	BNXT_ULP_HF15_IDX_O_UDP_DST_PORT         = 21,
-	BNXT_ULP_HF15_IDX_O_UDP_LENGTH           = 22,
-	BNXT_ULP_HF15_IDX_O_UDP_CSUM             = 23,
-	BNXT_ULP_HF15_IDX_T_VXLAN_FLAGS          = 24,
-	BNXT_ULP_HF15_IDX_T_VXLAN_RSVD0          = 25,
-	BNXT_ULP_HF15_IDX_T_VXLAN_VNI            = 26,
-	BNXT_ULP_HF15_IDX_T_VXLAN_RSVD1          = 27,
-	BNXT_ULP_HF15_IDX_I_ETH_DMAC             = 28,
-	BNXT_ULP_HF15_IDX_I_ETH_SMAC             = 29,
-	BNXT_ULP_HF15_IDX_I_ETH_TYPE             = 30,
-	BNXT_ULP_HF15_IDX_IO_VLAN_CFI_PRI        = 31,
-	BNXT_ULP_HF15_IDX_IO_VLAN_VID            = 32,
-	BNXT_ULP_HF15_IDX_IO_VLAN_TYPE           = 33,
-	BNXT_ULP_HF15_IDX_II_VLAN_CFI_PRI        = 34,
-	BNXT_ULP_HF15_IDX_II_VLAN_VID            = 35,
-	BNXT_ULP_HF15_IDX_II_VLAN_TYPE           = 36,
-	BNXT_ULP_HF15_IDX_I_IPV4_VER             = 37,
-	BNXT_ULP_HF15_IDX_I_IPV4_TOS             = 38,
-	BNXT_ULP_HF15_IDX_I_IPV4_LEN             = 39,
-	BNXT_ULP_HF15_IDX_I_IPV4_FRAG_ID         = 40,
-	BNXT_ULP_HF15_IDX_I_IPV4_FRAG_OFF        = 41,
-	BNXT_ULP_HF15_IDX_I_IPV4_TTL             = 42,
-	BNXT_ULP_HF15_IDX_I_IPV4_PROTO_ID        = 43,
-	BNXT_ULP_HF15_IDX_I_IPV4_CSUM            = 44,
-	BNXT_ULP_HF15_IDX_I_IPV4_SRC_ADDR        = 45,
-	BNXT_ULP_HF15_IDX_I_IPV4_DST_ADDR        = 46,
-	BNXT_ULP_HF15_IDX_I_UDP_SRC_PORT         = 47,
-	BNXT_ULP_HF15_IDX_I_UDP_DST_PORT         = 48,
-	BNXT_ULP_HF15_IDX_I_UDP_LENGTH           = 49,
-	BNXT_ULP_HF15_IDX_I_UDP_CSUM             = 50
+	BNXT_ULP_HF15_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF15_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF15_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF15_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF15_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF15_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT         = 18,
+	BNXT_ULP_HF15_IDX_O_TCP_DST_PORT         = 19,
+	BNXT_ULP_HF15_IDX_O_TCP_SENT_SEQ         = 20,
+	BNXT_ULP_HF15_IDX_O_TCP_RECV_ACK         = 21,
+	BNXT_ULP_HF15_IDX_O_TCP_DATA_OFF         = 22,
+	BNXT_ULP_HF15_IDX_O_TCP_TCP_FLAGS        = 23,
+	BNXT_ULP_HF15_IDX_O_TCP_RX_WIN           = 24,
+	BNXT_ULP_HF15_IDX_O_TCP_CSUM             = 25,
+	BNXT_ULP_HF15_IDX_O_TCP_URP              = 26
 };
 
 enum bnxt_ulp_hf16 {
@@ -359,7 +326,30 @@ enum bnxt_ulp_hf16 {
 	BNXT_ULP_HF16_IDX_T_VXLAN_FLAGS          = 24,
 	BNXT_ULP_HF16_IDX_T_VXLAN_RSVD0          = 25,
 	BNXT_ULP_HF16_IDX_T_VXLAN_VNI            = 26,
-	BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1          = 27
+	BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1          = 27,
+	BNXT_ULP_HF16_IDX_I_ETH_DMAC             = 28,
+	BNXT_ULP_HF16_IDX_I_ETH_SMAC             = 29,
+	BNXT_ULP_HF16_IDX_I_ETH_TYPE             = 30,
+	BNXT_ULP_HF16_IDX_IO_VLAN_CFI_PRI        = 31,
+	BNXT_ULP_HF16_IDX_IO_VLAN_VID            = 32,
+	BNXT_ULP_HF16_IDX_IO_VLAN_TYPE           = 33,
+	BNXT_ULP_HF16_IDX_II_VLAN_CFI_PRI        = 34,
+	BNXT_ULP_HF16_IDX_II_VLAN_VID            = 35,
+	BNXT_ULP_HF16_IDX_II_VLAN_TYPE           = 36,
+	BNXT_ULP_HF16_IDX_I_IPV4_VER             = 37,
+	BNXT_ULP_HF16_IDX_I_IPV4_TOS             = 38,
+	BNXT_ULP_HF16_IDX_I_IPV4_LEN             = 39,
+	BNXT_ULP_HF16_IDX_I_IPV4_FRAG_ID         = 40,
+	BNXT_ULP_HF16_IDX_I_IPV4_FRAG_OFF        = 41,
+	BNXT_ULP_HF16_IDX_I_IPV4_TTL             = 42,
+	BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID        = 43,
+	BNXT_ULP_HF16_IDX_I_IPV4_CSUM            = 44,
+	BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR        = 45,
+	BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR        = 46,
+	BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT         = 47,
+	BNXT_ULP_HF16_IDX_I_UDP_DST_PORT         = 48,
+	BNXT_ULP_HF16_IDX_I_UDP_LENGTH           = 49,
+	BNXT_ULP_HF16_IDX_I_UDP_CSUM             = 50
 };
 
 enum bnxt_ulp_hf17 {
@@ -386,7 +376,11 @@ enum bnxt_ulp_hf17 {
 	BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT         = 20,
 	BNXT_ULP_HF17_IDX_O_UDP_DST_PORT         = 21,
 	BNXT_ULP_HF17_IDX_O_UDP_LENGTH           = 22,
-	BNXT_ULP_HF17_IDX_O_UDP_CSUM             = 23
+	BNXT_ULP_HF17_IDX_O_UDP_CSUM             = 23,
+	BNXT_ULP_HF17_IDX_T_VXLAN_FLAGS          = 24,
+	BNXT_ULP_HF17_IDX_T_VXLAN_RSVD0          = 25,
+	BNXT_ULP_HF17_IDX_T_VXLAN_VNI            = 26,
+	BNXT_ULP_HF17_IDX_T_VXLAN_RSVD1          = 27
 };
 
 enum bnxt_ulp_hf18 {
@@ -410,15 +404,10 @@ enum bnxt_ulp_hf18 {
 	BNXT_ULP_HF18_IDX_O_IPV4_CSUM            = 17,
 	BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR        = 18,
 	BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR        = 19,
-	BNXT_ULP_HF18_IDX_O_TCP_SRC_PORT         = 20,
-	BNXT_ULP_HF18_IDX_O_TCP_DST_PORT         = 21,
-	BNXT_ULP_HF18_IDX_O_TCP_SENT_SEQ         = 22,
-	BNXT_ULP_HF18_IDX_O_TCP_RECV_ACK         = 23,
-	BNXT_ULP_HF18_IDX_O_TCP_DATA_OFF         = 24,
-	BNXT_ULP_HF18_IDX_O_TCP_TCP_FLAGS        = 25,
-	BNXT_ULP_HF18_IDX_O_TCP_RX_WIN           = 26,
-	BNXT_ULP_HF18_IDX_O_TCP_CSUM             = 27,
-	BNXT_ULP_HF18_IDX_O_TCP_URP              = 28
+	BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT         = 20,
+	BNXT_ULP_HF18_IDX_O_UDP_DST_PORT         = 21,
+	BNXT_ULP_HF18_IDX_O_UDP_LENGTH           = 22,
+	BNXT_ULP_HF18_IDX_O_UDP_CSUM             = 23
 };
 
 enum bnxt_ulp_hf19 {
@@ -432,18 +421,25 @@ enum bnxt_ulp_hf19 {
 	BNXT_ULP_HF19_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF19_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF19_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF19_IDX_O_IPV6_VER             = 10,
-	BNXT_ULP_HF19_IDX_O_IPV6_TC              = 11,
-	BNXT_ULP_HF19_IDX_O_IPV6_FLOW_LABEL      = 12,
-	BNXT_ULP_HF19_IDX_O_IPV6_PAYLOAD_LEN     = 13,
-	BNXT_ULP_HF19_IDX_O_IPV6_PROTO_ID        = 14,
-	BNXT_ULP_HF19_IDX_O_IPV6_TTL             = 15,
-	BNXT_ULP_HF19_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF19_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT         = 18,
-	BNXT_ULP_HF19_IDX_O_UDP_DST_PORT         = 19,
-	BNXT_ULP_HF19_IDX_O_UDP_LENGTH           = 20,
-	BNXT_ULP_HF19_IDX_O_UDP_CSUM             = 21
+	BNXT_ULP_HF19_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF19_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF19_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF19_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF19_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF19_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF19_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF19_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR        = 19,
+	BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT         = 20,
+	BNXT_ULP_HF19_IDX_O_TCP_DST_PORT         = 21,
+	BNXT_ULP_HF19_IDX_O_TCP_SENT_SEQ         = 22,
+	BNXT_ULP_HF19_IDX_O_TCP_RECV_ACK         = 23,
+	BNXT_ULP_HF19_IDX_O_TCP_DATA_OFF         = 24,
+	BNXT_ULP_HF19_IDX_O_TCP_TCP_FLAGS        = 25,
+	BNXT_ULP_HF19_IDX_O_TCP_RX_WIN           = 26,
+	BNXT_ULP_HF19_IDX_O_TCP_CSUM             = 27,
+	BNXT_ULP_HF19_IDX_O_TCP_URP              = 28
 };
 
 enum bnxt_ulp_hf20 {
@@ -465,15 +461,10 @@ enum bnxt_ulp_hf20 {
 	BNXT_ULP_HF20_IDX_O_IPV6_TTL             = 15,
 	BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR        = 16,
 	BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF20_IDX_O_TCP_SRC_PORT         = 18,
-	BNXT_ULP_HF20_IDX_O_TCP_DST_PORT         = 19,
-	BNXT_ULP_HF20_IDX_O_TCP_SENT_SEQ         = 20,
-	BNXT_ULP_HF20_IDX_O_TCP_RECV_ACK         = 21,
-	BNXT_ULP_HF20_IDX_O_TCP_DATA_OFF         = 22,
-	BNXT_ULP_HF20_IDX_O_TCP_TCP_FLAGS        = 23,
-	BNXT_ULP_HF20_IDX_O_TCP_RX_WIN           = 24,
-	BNXT_ULP_HF20_IDX_O_TCP_CSUM             = 25,
-	BNXT_ULP_HF20_IDX_O_TCP_URP              = 26
+	BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT         = 18,
+	BNXT_ULP_HF20_IDX_O_UDP_DST_PORT         = 19,
+	BNXT_ULP_HF20_IDX_O_UDP_LENGTH           = 20,
+	BNXT_ULP_HF20_IDX_O_UDP_CSUM             = 21
 };
 
 enum bnxt_ulp_hf21 {
@@ -487,16 +478,67 @@ enum bnxt_ulp_hf21 {
 	BNXT_ULP_HF21_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF21_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF21_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF21_IDX_O_IPV4_VER             = 10,
-	BNXT_ULP_HF21_IDX_O_IPV4_TOS             = 11,
-	BNXT_ULP_HF21_IDX_O_IPV4_LEN             = 12,
-	BNXT_ULP_HF21_IDX_O_IPV4_FRAG_ID         = 13,
-	BNXT_ULP_HF21_IDX_O_IPV4_FRAG_OFF        = 14,
-	BNXT_ULP_HF21_IDX_O_IPV4_TTL             = 15,
-	BNXT_ULP_HF21_IDX_O_IPV4_PROTO_ID        = 16,
-	BNXT_ULP_HF21_IDX_O_IPV4_CSUM            = 17,
-	BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR        = 18,
-	BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR        = 19
+	BNXT_ULP_HF21_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF21_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF21_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF21_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF21_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF21_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT         = 18,
+	BNXT_ULP_HF21_IDX_O_TCP_DST_PORT         = 19,
+	BNXT_ULP_HF21_IDX_O_TCP_SENT_SEQ         = 20,
+	BNXT_ULP_HF21_IDX_O_TCP_RECV_ACK         = 21,
+	BNXT_ULP_HF21_IDX_O_TCP_DATA_OFF         = 22,
+	BNXT_ULP_HF21_IDX_O_TCP_TCP_FLAGS        = 23,
+	BNXT_ULP_HF21_IDX_O_TCP_RX_WIN           = 24,
+	BNXT_ULP_HF21_IDX_O_TCP_CSUM             = 25,
+	BNXT_ULP_HF21_IDX_O_TCP_URP              = 26
+};
+
+enum bnxt_ulp_hf22 {
+	BNXT_ULP_HF22_IDX_SVIF_INDEX             = 0,
+	BNXT_ULP_HF22_IDX_O_ETH_DMAC             = 1,
+	BNXT_ULP_HF22_IDX_O_ETH_SMAC             = 2,
+	BNXT_ULP_HF22_IDX_O_ETH_TYPE             = 3,
+	BNXT_ULP_HF22_IDX_OO_VLAN_CFI_PRI        = 4,
+	BNXT_ULP_HF22_IDX_OO_VLAN_VID            = 5,
+	BNXT_ULP_HF22_IDX_OO_VLAN_TYPE           = 6,
+	BNXT_ULP_HF22_IDX_OI_VLAN_CFI_PRI        = 7,
+	BNXT_ULP_HF22_IDX_OI_VLAN_VID            = 8,
+	BNXT_ULP_HF22_IDX_OI_VLAN_TYPE           = 9,
+	BNXT_ULP_HF22_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF22_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF22_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF22_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF22_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF22_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF22_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF22_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF22_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF22_IDX_O_IPV4_DST_ADDR        = 19
+};
+
+enum bnxt_ulp_hf23 {
+	BNXT_ULP_HF23_IDX_SVIF_INDEX             = 0,
+	BNXT_ULP_HF23_IDX_O_ETH_DMAC             = 1,
+	BNXT_ULP_HF23_IDX_O_ETH_SMAC             = 2,
+	BNXT_ULP_HF23_IDX_O_ETH_TYPE             = 3,
+	BNXT_ULP_HF23_IDX_OO_VLAN_CFI_PRI        = 4,
+	BNXT_ULP_HF23_IDX_OO_VLAN_VID            = 5,
+	BNXT_ULP_HF23_IDX_OO_VLAN_TYPE           = 6,
+	BNXT_ULP_HF23_IDX_OI_VLAN_CFI_PRI        = 7,
+	BNXT_ULP_HF23_IDX_OI_VLAN_VID            = 8,
+	BNXT_ULP_HF23_IDX_OI_VLAN_TYPE           = 9,
+	BNXT_ULP_HF23_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF23_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF23_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF23_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF23_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF23_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR        = 17
 };
 
 enum bnxt_ulp_hf_bitmask1 {
@@ -553,20 +595,14 @@ enum bnxt_ulp_hf_bitmask7 {
 	BNXT_ULP_HF7_BITMASK_OI_VLAN_CFI_PRI     = 0x0100000000000000,
 	BNXT_ULP_HF7_BITMASK_OI_VLAN_VID         = 0x0080000000000000,
 	BNXT_ULP_HF7_BITMASK_OI_VLAN_TYPE        = 0x0040000000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_VER          = 0x0020000000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_TOS          = 0x0010000000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_LEN          = 0x0008000000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_FRAG_ID      = 0x0004000000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_FRAG_OFF     = 0x0002000000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_TTL          = 0x0001000000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID     = 0x0000800000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_CSUM         = 0x0000400000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR     = 0x0000200000000000,
-	BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR     = 0x0000100000000000,
-	BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT      = 0x0000080000000000,
-	BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT      = 0x0000040000000000,
-	BNXT_ULP_HF7_BITMASK_O_UDP_LENGTH        = 0x0000020000000000,
-	BNXT_ULP_HF7_BITMASK_O_UDP_CSUM          = 0x0000010000000000
+	BNXT_ULP_HF7_BITMASK_O_IPV6_VER          = 0x0020000000000000,
+	BNXT_ULP_HF7_BITMASK_O_IPV6_TC           = 0x0010000000000000,
+	BNXT_ULP_HF7_BITMASK_O_IPV6_FLOW_LABEL   = 0x0008000000000000,
+	BNXT_ULP_HF7_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0004000000000000,
+	BNXT_ULP_HF7_BITMASK_O_IPV6_PROTO_ID     = 0x0002000000000000,
+	BNXT_ULP_HF7_BITMASK_O_IPV6_TTL          = 0x0001000000000000,
+	BNXT_ULP_HF7_BITMASK_O_IPV6_SRC_ADDR     = 0x0000800000000000,
+	BNXT_ULP_HF7_BITMASK_O_IPV6_DST_ADDR     = 0x0000400000000000
 };
 
 enum bnxt_ulp_hf_bitmask8 {
@@ -590,15 +626,10 @@ enum bnxt_ulp_hf_bitmask8 {
 	BNXT_ULP_HF8_BITMASK_O_IPV4_CSUM         = 0x0000400000000000,
 	BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR     = 0x0000200000000000,
 	BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR     = 0x0000100000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT      = 0x0000080000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT      = 0x0000040000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_SENT_SEQ      = 0x0000020000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_RECV_ACK      = 0x0000010000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_DATA_OFF      = 0x0000008000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_TCP_FLAGS     = 0x0000004000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_RX_WIN        = 0x0000002000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_CSUM          = 0x0000001000000000,
-	BNXT_ULP_HF8_BITMASK_O_TCP_URP           = 0x0000000800000000
+	BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT      = 0x0000080000000000,
+	BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT      = 0x0000040000000000,
+	BNXT_ULP_HF8_BITMASK_O_UDP_LENGTH        = 0x0000020000000000,
+	BNXT_ULP_HF8_BITMASK_O_UDP_CSUM          = 0x0000010000000000
 };
 
 enum bnxt_ulp_hf_bitmask9 {
@@ -612,18 +643,25 @@ enum bnxt_ulp_hf_bitmask9 {
 	BNXT_ULP_HF9_BITMASK_OI_VLAN_CFI_PRI     = 0x0100000000000000,
 	BNXT_ULP_HF9_BITMASK_OI_VLAN_VID         = 0x0080000000000000,
 	BNXT_ULP_HF9_BITMASK_OI_VLAN_TYPE        = 0x0040000000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_VER          = 0x0020000000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_TC           = 0x0010000000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_FLOW_LABEL   = 0x0008000000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0004000000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID     = 0x0002000000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_TTL          = 0x0001000000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR     = 0x0000800000000000,
-	BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR     = 0x0000400000000000,
-	BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT      = 0x0000200000000000,
-	BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT      = 0x0000100000000000,
-	BNXT_ULP_HF9_BITMASK_O_UDP_LENGTH        = 0x0000080000000000,
-	BNXT_ULP_HF9_BITMASK_O_UDP_CSUM          = 0x0000040000000000
+	BNXT_ULP_HF9_BITMASK_O_IPV4_VER          = 0x0020000000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_TOS          = 0x0010000000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_LEN          = 0x0008000000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_ID      = 0x0004000000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_OFF     = 0x0002000000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_TTL          = 0x0001000000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID     = 0x0000800000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_CSUM         = 0x0000400000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR     = 0x0000200000000000,
+	BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR     = 0x0000100000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT      = 0x0000080000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT      = 0x0000040000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_SENT_SEQ      = 0x0000020000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_RECV_ACK      = 0x0000010000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_DATA_OFF      = 0x0000008000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_TCP_FLAGS     = 0x0000004000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_RX_WIN        = 0x0000002000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_CSUM          = 0x0000001000000000,
+	BNXT_ULP_HF9_BITMASK_O_TCP_URP           = 0x0000000800000000
 };
 
 enum bnxt_ulp_hf_bitmask10 {
@@ -645,15 +683,10 @@ enum bnxt_ulp_hf_bitmask10 {
 	BNXT_ULP_HF10_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
 	BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
 	BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-	BNXT_ULP_HF10_BITMASK_O_TCP_URP          = 0x0000002000000000
+	BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF10_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF10_BITMASK_O_UDP_CSUM         = 0x0000040000000000
 };
 
 enum bnxt_ulp_hf_bitmask11 {
@@ -667,20 +700,23 @@ enum bnxt_ulp_hf_bitmask11 {
 	BNXT_ULP_HF11_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF11_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF11_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_VER         = 0x0020000000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
-	BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
-	BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
-	BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
-	BNXT_ULP_HF11_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
-	BNXT_ULP_HF11_BITMASK_O_UDP_CSUM         = 0x0000010000000000
+	BNXT_ULP_HF11_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF11_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF11_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF11_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+	BNXT_ULP_HF11_BITMASK_O_TCP_URP          = 0x0000002000000000
 };
 
 enum bnxt_ulp_hf_bitmask12 {
@@ -704,15 +740,10 @@ enum bnxt_ulp_hf_bitmask12 {
 	BNXT_ULP_HF12_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
 	BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
 	BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
-	BNXT_ULP_HF12_BITMASK_O_TCP_URP          = 0x0000000800000000
+	BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF12_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
+	BNXT_ULP_HF12_BITMASK_O_UDP_CSUM         = 0x0000010000000000
 };
 
 enum bnxt_ulp_hf_bitmask13 {
@@ -726,18 +757,25 @@ enum bnxt_ulp_hf_bitmask13 {
 	BNXT_ULP_HF13_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF13_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF13_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_VER         = 0x0020000000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_TC          = 0x0010000000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF13_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
-	BNXT_ULP_HF13_BITMASK_O_UDP_CSUM         = 0x0000040000000000
+	BNXT_ULP_HF13_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
+	BNXT_ULP_HF13_BITMASK_O_TCP_URP          = 0x0000000800000000
 };
 
 enum bnxt_ulp_hf_bitmask14 {
@@ -759,15 +797,10 @@ enum bnxt_ulp_hf_bitmask14 {
 	BNXT_ULP_HF14_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
 	BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
 	BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-	BNXT_ULP_HF14_BITMASK_O_TCP_URP          = 0x0000002000000000
+	BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF14_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF14_BITMASK_O_UDP_CSUM         = 0x0000040000000000
 };
 
 enum bnxt_ulp_hf_bitmask15 {
@@ -781,47 +814,23 @@ enum bnxt_ulp_hf_bitmask15 {
 	BNXT_ULP_HF15_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF15_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF15_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_VER         = 0x0020000000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
-	BNXT_ULP_HF15_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
-	BNXT_ULP_HF15_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
-	BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
-	BNXT_ULP_HF15_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
-	BNXT_ULP_HF15_BITMASK_O_UDP_CSUM         = 0x0000010000000000,
-	BNXT_ULP_HF15_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
-	BNXT_ULP_HF15_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
-	BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
-	BNXT_ULP_HF15_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000,
-	BNXT_ULP_HF15_BITMASK_I_ETH_DMAC         = 0x0000000800000000,
-	BNXT_ULP_HF15_BITMASK_I_ETH_SMAC         = 0x0000000400000000,
-	BNXT_ULP_HF15_BITMASK_I_ETH_TYPE         = 0x0000000200000000,
-	BNXT_ULP_HF15_BITMASK_IO_VLAN_CFI_PRI    = 0x0000000100000000,
-	BNXT_ULP_HF15_BITMASK_IO_VLAN_VID        = 0x0000000080000000,
-	BNXT_ULP_HF15_BITMASK_IO_VLAN_TYPE       = 0x0000000040000000,
-	BNXT_ULP_HF15_BITMASK_II_VLAN_CFI_PRI    = 0x0000000020000000,
-	BNXT_ULP_HF15_BITMASK_II_VLAN_VID        = 0x0000000010000000,
-	BNXT_ULP_HF15_BITMASK_II_VLAN_TYPE       = 0x0000000008000000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_VER         = 0x0000000004000000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_TOS         = 0x0000000002000000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_LEN         = 0x0000000001000000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_FRAG_ID     = 0x0000000000800000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_FRAG_OFF    = 0x0000000000400000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_TTL         = 0x0000000000200000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID    = 0x0000000000100000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_CSUM        = 0x0000000000080000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR    = 0x0000000000040000,
-	BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR    = 0x0000000000020000,
-	BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT     = 0x0000000000010000,
-	BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT     = 0x0000000000008000,
-	BNXT_ULP_HF15_BITMASK_I_UDP_LENGTH       = 0x0000000000004000,
-	BNXT_ULP_HF15_BITMASK_I_UDP_CSUM         = 0x0000000000002000
+	BNXT_ULP_HF15_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF15_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF15_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF15_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF15_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+	BNXT_ULP_HF15_BITMASK_O_TCP_URP          = 0x0000002000000000
 };
 
 enum bnxt_ulp_hf_bitmask16 {
@@ -852,7 +861,30 @@ enum bnxt_ulp_hf_bitmask16 {
 	BNXT_ULP_HF16_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
 	BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
 	BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
-	BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000
+	BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000,
+	BNXT_ULP_HF16_BITMASK_I_ETH_DMAC         = 0x0000000800000000,
+	BNXT_ULP_HF16_BITMASK_I_ETH_SMAC         = 0x0000000400000000,
+	BNXT_ULP_HF16_BITMASK_I_ETH_TYPE         = 0x0000000200000000,
+	BNXT_ULP_HF16_BITMASK_IO_VLAN_CFI_PRI    = 0x0000000100000000,
+	BNXT_ULP_HF16_BITMASK_IO_VLAN_VID        = 0x0000000080000000,
+	BNXT_ULP_HF16_BITMASK_IO_VLAN_TYPE       = 0x0000000040000000,
+	BNXT_ULP_HF16_BITMASK_II_VLAN_CFI_PRI    = 0x0000000020000000,
+	BNXT_ULP_HF16_BITMASK_II_VLAN_VID        = 0x0000000010000000,
+	BNXT_ULP_HF16_BITMASK_II_VLAN_TYPE       = 0x0000000008000000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_VER         = 0x0000000004000000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_TOS         = 0x0000000002000000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_LEN         = 0x0000000001000000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_FRAG_ID     = 0x0000000000800000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_FRAG_OFF    = 0x0000000000400000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_TTL         = 0x0000000000200000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID    = 0x0000000000100000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_CSUM        = 0x0000000000080000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR    = 0x0000000000040000,
+	BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR    = 0x0000000000020000,
+	BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT     = 0x0000000000010000,
+	BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT     = 0x0000000000008000,
+	BNXT_ULP_HF16_BITMASK_I_UDP_LENGTH       = 0x0000000000004000,
+	BNXT_ULP_HF16_BITMASK_I_UDP_CSUM         = 0x0000000000002000
 };
 
 enum bnxt_ulp_hf_bitmask17 {
@@ -879,7 +911,11 @@ enum bnxt_ulp_hf_bitmask17 {
 	BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
 	BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
 	BNXT_ULP_HF17_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
-	BNXT_ULP_HF17_BITMASK_O_UDP_CSUM         = 0x0000010000000000
+	BNXT_ULP_HF17_BITMASK_O_UDP_CSUM         = 0x0000010000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000
 };
 
 enum bnxt_ulp_hf_bitmask18 {
@@ -903,15 +939,10 @@ enum bnxt_ulp_hf_bitmask18 {
 	BNXT_ULP_HF18_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
 	BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
 	BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
-	BNXT_ULP_HF18_BITMASK_O_TCP_URP          = 0x0000000800000000
+	BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF18_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
+	BNXT_ULP_HF18_BITMASK_O_UDP_CSUM         = 0x0000010000000000
 };
 
 enum bnxt_ulp_hf_bitmask19 {
@@ -925,18 +956,25 @@ enum bnxt_ulp_hf_bitmask19 {
 	BNXT_ULP_HF19_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF19_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF19_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_VER         = 0x0020000000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_TC          = 0x0010000000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF19_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
-	BNXT_ULP_HF19_BITMASK_O_UDP_CSUM         = 0x0000040000000000
+	BNXT_ULP_HF19_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
+	BNXT_ULP_HF19_BITMASK_O_TCP_URP          = 0x0000000800000000
 };
 
 enum bnxt_ulp_hf_bitmask20 {
@@ -958,15 +996,10 @@ enum bnxt_ulp_hf_bitmask20 {
 	BNXT_ULP_HF20_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
 	BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
 	BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-	BNXT_ULP_HF20_BITMASK_O_TCP_URP          = 0x0000002000000000
+	BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_CSUM         = 0x0000040000000000
 };
 
 enum bnxt_ulp_hf_bitmask21 {
@@ -980,16 +1013,66 @@ enum bnxt_ulp_hf_bitmask21 {
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_VER         = 0x0020000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000
+	BNXT_ULP_HF21_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_URP          = 0x0000002000000000
 };
 
+enum bnxt_ulp_hf_bitmask22 {
+	BNXT_ULP_HF22_BITMASK_SVIF_INDEX         = 0x8000000000000000,
+	BNXT_ULP_HF22_BITMASK_O_ETH_DMAC         = 0x4000000000000000,
+	BNXT_ULP_HF22_BITMASK_O_ETH_SMAC         = 0x2000000000000000,
+	BNXT_ULP_HF22_BITMASK_O_ETH_TYPE         = 0x1000000000000000,
+	BNXT_ULP_HF22_BITMASK_OO_VLAN_CFI_PRI    = 0x0800000000000000,
+	BNXT_ULP_HF22_BITMASK_OO_VLAN_VID        = 0x0400000000000000,
+	BNXT_ULP_HF22_BITMASK_OO_VLAN_TYPE       = 0x0200000000000000,
+	BNXT_ULP_HF22_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
+	BNXT_ULP_HF22_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
+	BNXT_ULP_HF22_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf_bitmask23 {
+	BNXT_ULP_HF23_BITMASK_SVIF_INDEX         = 0x8000000000000000,
+	BNXT_ULP_HF23_BITMASK_O_ETH_DMAC         = 0x4000000000000000,
+	BNXT_ULP_HF23_BITMASK_O_ETH_SMAC         = 0x2000000000000000,
+	BNXT_ULP_HF23_BITMASK_O_ETH_TYPE         = 0x1000000000000000,
+	BNXT_ULP_HF23_BITMASK_OO_VLAN_CFI_PRI    = 0x0800000000000000,
+	BNXT_ULP_HF23_BITMASK_OO_VLAN_VID        = 0x0400000000000000,
+	BNXT_ULP_HF23_BITMASK_OO_VLAN_TYPE       = 0x0200000000000000,
+	BNXT_ULP_HF23_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
+	BNXT_ULP_HF23_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
+	BNXT_ULP_HF23_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000
+};
 #endif
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 06/25] net/bnxt: free the em index on failure
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (4 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 05/25] net/bnxt: fix to break the ipv4 and ipv6 ingress rule Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 07/25] net/bnxt: add a null ptr check for the resource manager Ajit Khaparde
                   ` (19 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Mike Baucom

From: Mike Baucom <michael.baucom@broadcom.com>

When a Internal EM entry fails insertion, the allocated index needs to
be pushed back to the allocation stack.

Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_em_internal.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 462d0fa76..c95515b1b 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -175,8 +175,11 @@ tf_em_insert_int_entry(struct tf *tfp,
 					     &rptr_index,
 					     &rptr_entry,
 					     &num_of_entries);
-	if (rc)
+	if (rc) {
+		/* Free the allocated index before returning */
+		stack_push(pool, index);
 		return -1;
+	}
 
 	PMD_DRV_LOG
 		  (DEBUG,
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 07/25] net/bnxt: add a null ptr check for the resource manager
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (5 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 06/25] net/bnxt: free the em index on failure Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 08/25] net/bnxt: change default flow rule to use 8B encap Ajit Khaparde
                   ` (18 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Shahaji Bhosle, Mike Baucom

From: Shahaji Bhosle <sbhosle@broadcom.com>

Verify the resource manager exists prior to using

Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_rm.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 9aec954db..66a33583b 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -706,6 +706,8 @@ tf_rm_allocate(struct tf_rm_allocate_parms *parms)
 	TF_CHECK_PARMS2(parms, parms->rm_db);
 
 	rm_db = (struct tf_rm_new_db *)parms->rm_db;
+	if (!rm_db->db)
+		return -EINVAL;
 	cfg_type = rm_db->db[parms->db_index].cfg_type;
 
 	/* Bail out if not controlled by RM */
@@ -772,6 +774,8 @@ tf_rm_free(struct tf_rm_free_parms *parms)
 	TF_CHECK_PARMS2(parms, parms->rm_db);
 
 	rm_db = (struct tf_rm_new_db *)parms->rm_db;
+	if (!rm_db->db)
+		return -EINVAL;
 	cfg_type = rm_db->db[parms->db_index].cfg_type;
 
 	/* Bail out if not controlled by RM */
@@ -817,6 +821,8 @@ tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms)
 	TF_CHECK_PARMS2(parms, parms->rm_db);
 
 	rm_db = (struct tf_rm_new_db *)parms->rm_db;
+	if (!rm_db->db)
+		return -EINVAL;
 	cfg_type = rm_db->db[parms->db_index].cfg_type;
 
 	/* Bail out if not controlled by RM */
@@ -860,6 +866,8 @@ tf_rm_get_info(struct tf_rm_get_alloc_info_parms *parms)
 	TF_CHECK_PARMS2(parms, parms->rm_db);
 
 	rm_db = (struct tf_rm_new_db *)parms->rm_db;
+	if (!rm_db->db)
+		return -EINVAL;
 	cfg_type = rm_db->db[parms->db_index].cfg_type;
 
 	/* Bail out if not controlled by HCAPI */
@@ -883,6 +891,8 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms)
 	TF_CHECK_PARMS2(parms, parms->rm_db);
 
 	rm_db = (struct tf_rm_new_db *)parms->rm_db;
+	if (!rm_db->db)
+		return -EINVAL;
 	cfg_type = rm_db->db[parms->db_index].cfg_type;
 
 	/* Bail out if not controlled by HCAPI */
@@ -905,6 +915,8 @@ tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms)
 	TF_CHECK_PARMS2(parms, parms->rm_db);
 
 	rm_db = (struct tf_rm_new_db *)parms->rm_db;
+	if (!rm_db->db)
+		return -EINVAL;
 	cfg_type = rm_db->db[parms->db_index].cfg_type;
 
 	/* Bail out if not controlled by RM */
@@ -937,6 +949,8 @@ tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms)
 	TF_CHECK_PARMS2(parms, parms->rm_db);
 
 	rm_db = (struct tf_rm_new_db *)parms->rm_db;
+	if (!rm_db->db)
+		return -EINVAL;
 	cfg_type = rm_db->db[parms->db_index].cfg_type;
 
 	/* Bail out if not controlled by RM */
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 08/25] net/bnxt: change default flow rule to use 8B encap
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (6 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 07/25] net/bnxt: add a null ptr check for the resource manager Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 09/25] net/bnxt: fix the function id used in the flow flush Ajit Khaparde
                   ` (17 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Shahaji Bhosle

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The VFR conduit uses vlan encap to send packets, the encap record
is changed from 16B to 8B so the free 8B encap records could be used.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c            |  3 +-
 .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 59 ++++++++++---------
 2 files changed, 32 insertions(+), 30 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 21baed048..bd6039d2a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -97,7 +97,7 @@ ulp_ctx_session_open(struct bnxt *bp,
 	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023;
 
 	/* ENCAP */
-	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 16;
+	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255;
 	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 63;
 
 	/* TCAMs */
@@ -130,6 +130,7 @@ ulp_ctx_session_open(struct bnxt *bp,
 	/* ENCAP */
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 511;
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 200;
+	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255;
 
 	/* TCAMs */
 	resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] =
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index 3d133d2ff..a6dd3219c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -4528,8 +4528,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 722,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
 	.result_start_idx = 558,
 	.result_bit_size = 64,
@@ -4600,8 +4600,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 791,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
 	.result_start_idx = 589,
 	.result_bit_size = 64,
@@ -5100,8 +5100,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
 	.key_start_idx = 1209,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
 	.result_start_idx = 779,
 	.result_bit_size = 64,
@@ -10173,7 +10173,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -10183,7 +10183,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -10664,7 +10664,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -10674,7 +10674,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -11279,6 +11279,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
 		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
@@ -11293,11 +11298,6 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
@@ -13056,11 +13056,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		(BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 128,
@@ -13531,7 +13532,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -13541,7 +13542,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -17380,7 +17381,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17431,8 +17432,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17558,7 +17559,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17609,8 +17610,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -18722,7 +18723,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -18773,8 +18774,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 09/25] net/bnxt: fix the function id used in the flow flush
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (7 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 08/25] net/bnxt: change default flow rule to use 8B encap Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 10/25] net/bnxt: vfr port clean up during port stop Ajit Khaparde
                   ` (16 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Shahaji Bhosle

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The function id being used in the flush is incorrect, fixed the
flush of the flows.

Fixes: 74bcfc062489 ("net/bnxt: add session and function flow flush")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
---
 drivers/net/bnxt/bnxt_ethdev.c          |  1 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c      | 19 +++++++-----
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h      |  5 +--
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 39 ++++++++++++++++-------
 drivers/net/bnxt/tf_ulp/ulp_port_db.c   | 41 +++++++++++++++++++++++++
 drivers/net/bnxt/tf_ulp/ulp_port_db.h   | 13 ++++++++
 6 files changed, 95 insertions(+), 23 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index fdbd6ce58..bc9aeba08 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -3708,6 +3708,7 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
 		struct bnxt_vf_representor *vfr = dev->data->dev_private;
 		bp = vfr->parent_dev->data->dev_private;
+		/* parent is deleted while children are still valid */
 		if (!bp)
 			return -EIO;
 	}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index bd6039d2a..63d453ffb 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -35,14 +35,12 @@ static pthread_mutex_t bnxt_ulp_global_mutex = PTHREAD_MUTEX_INITIALIZER;
  * created the session.
  */
 bool
-ulp_ctx_deinit_allowed(void *ptr)
+ulp_ctx_deinit_allowed(struct bnxt_ulp_context *ulp_ctx)
 {
-	struct bnxt *bp = (struct bnxt *)ptr;
-
-	if (!bp || !bp->ulp_ctx || !bp->ulp_ctx->cfg_data)
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
 		return false;
 
-	if (!bp->ulp_ctx->cfg_data->ref_cnt) {
+	if (!ulp_ctx->cfg_data->ref_cnt) {
 		BNXT_TF_DBG(DEBUG, "ulp ctx shall initiate deinit\n");
 		return true;
 	}
@@ -629,9 +627,14 @@ bnxt_ulp_flush_port_flows(struct bnxt *bp)
 {
 	uint16_t func_id;
 
-	func_id = bnxt_get_fw_func_id(bp->eth_dev->data->port_id,
-				      BNXT_ULP_INTF_TYPE_INVALID);
-	ulp_flow_db_function_flow_flush(bp->ulp_ctx, func_id);
+	/* it is assumed that port is either TVF or PF */
+	if (ulp_port_db_port_func_id_get(bp->ulp_ctx,
+					 bp->eth_dev->data->port_id,
+					 &func_id)) {
+		BNXT_TF_DBG(ERR, "Invalid argument\n");
+		return;
+	}
+	(void)ulp_flow_db_function_flow_flush(bp->ulp_ctx, func_id);
 }
 
 /* Internal function to delete the VFR default flows */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 8a2825ae5..5882c545c 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -83,12 +83,9 @@ struct ulp_tlv_param {
 /*
  * Allow the deletion of context only for the bnxt device that
  * created the session
- * TBD - The implementation of the function should change to
- * using the reference count once tf_session_attach functionality
- * is fixed.
  */
 bool
-ulp_ctx_deinit_allowed(void *bp);
+ulp_ctx_deinit_allowed(struct bnxt_ulp_context *ulp_ctx);
 
 /* Function to set the device id of the hardware. */
 int32_t
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 2ab00453a..566e1254a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -10,6 +10,7 @@
 #include "ulp_flow_db.h"
 #include "ulp_mapper.h"
 #include "ulp_fc_mgr.h"
+#include "ulp_port_db.h"
 #include <rte_malloc.h>
 
 static int32_t
@@ -146,8 +147,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	mapper_cparms.act_prop = &params.act_prop;
 	mapper_cparms.class_tid = class_id;
 	mapper_cparms.act_tid = act_tmpl;
-	mapper_cparms.func_id = bnxt_get_fw_func_id(dev->data->port_id,
-						    BNXT_ULP_INTF_TYPE_INVALID);
+
+	/* Get the function id */
+	if (ulp_port_db_port_func_id_get(ulp_ctx,
+					 dev->data->port_id,
+					 &mapper_cparms.func_id)) {
+		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+		goto parse_error;
+	}
 	mapper_cparms.dir_attr = params.dir_attr;
 
 	/* Call the ulp mapper to create the flow in the hardware. */
@@ -251,8 +258,17 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev,
 	}
 
 	flow_id = (uint32_t)(uintptr_t)flow;
-	func_id = bnxt_get_fw_func_id(dev->data->port_id,
-				      BNXT_ULP_INTF_TYPE_INVALID);
+
+	if (ulp_port_db_port_func_id_get(ulp_ctx,
+					 dev->data->port_id,
+					 &func_id)) {
+		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+		if (error)
+			rte_flow_error_set(error, EINVAL,
+					   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+					   "Failed to destroy flow.");
+		return -EINVAL;
+	}
 
 	if (ulp_flow_db_validate_flow_func(ulp_ctx, flow_id, func_id) ==
 	    false) {
@@ -284,23 +300,24 @@ bnxt_ulp_flow_flush(struct rte_eth_dev *eth_dev,
 {
 	struct bnxt_ulp_context *ulp_ctx;
 	int32_t ret = 0;
-	struct bnxt *bp;
 	uint16_t func_id;
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
 	if (!ulp_ctx) {
-		BNXT_TF_DBG(DEBUG, "ULP context is not initialized\n");
 		return ret;
 	}
-	bp = eth_dev->data->dev_private;
 
 	/* Free the resources for the last device */
-	if (ulp_ctx_deinit_allowed(bp)) {
+	if (ulp_ctx_deinit_allowed(ulp_ctx)) {
 		ret = ulp_flow_db_session_flow_flush(ulp_ctx);
 	} else if (bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctx)) {
-		func_id = bnxt_get_fw_func_id(eth_dev->data->port_id,
-					      BNXT_ULP_INTF_TYPE_INVALID);
-		ret = ulp_flow_db_function_flow_flush(ulp_ctx, func_id);
+		ret = ulp_port_db_port_func_id_get(ulp_ctx,
+						   eth_dev->data->port_id,
+						   &func_id);
+		if (!ret)
+			ret = ulp_flow_db_function_flow_flush(ulp_ctx, func_id);
+		else
+			BNXT_TF_DBG(ERR, "convert port to func id failed\n");
 	}
 	if (ret)
 		rte_flow_error_set(error, ret,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index 30876478d..4b4eaeb12 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -540,3 +540,44 @@ ulp_port_db_dev_func_id_to_ulp_index(struct bnxt_ulp_context *ulp_ctxt,
 	*ifindex = port_db->ulp_func_id_tbl[func_id].ifindex;
 	return 0;
 }
+
+/*
+ * Api to get the function id for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] dpdk port id
+ * func_id [out] the function id of the given ifindex.
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt,
+			     uint16_t port_id, uint16_t *func_id)
+{
+	struct bnxt_ulp_port_db *port_db;
+	uint32_t ifindex;
+
+	port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt);
+	if (!port_db || port_id >= RTE_MAX_ETHPORTS) {
+		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+		return -EINVAL;
+	}
+	ifindex = port_db->dev_port_list[port_id];
+	if (!ifindex)
+		return -ENOENT;
+
+	switch (port_db->ulp_intf_list[ifindex].type) {
+	case BNXT_ULP_INTF_TYPE_TRUSTED_VF:
+	case BNXT_ULP_INTF_TYPE_PF:
+		*func_id =  port_db->ulp_intf_list[ifindex].drv_func_id;
+		break;
+	case BNXT_ULP_INTF_TYPE_VF:
+	case BNXT_ULP_INTF_TYPE_VF_REP:
+		*func_id =  port_db->ulp_intf_list[ifindex].vf_func_id;
+		break;
+	default:
+		*func_id = 0;
+		break;
+	}
+	return 0;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
index 2b323d168..7b85987a0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
@@ -259,4 +259,17 @@ int32_t
 ulp_port_db_dev_func_id_to_ulp_index(struct bnxt_ulp_context *ulp_ctxt,
 				     uint32_t func_id, uint32_t *ifindex);
 
+/*
+ * Api to get the function id for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] dpdk port id
+ * func_id [out] the function id of the given ifindex.
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt,
+			     uint16_t port_id, uint16_t *func_id);
+
 #endif /* _ULP_PORT_DB_H_ */
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 10/25] net/bnxt: vfr port clean up during port stop
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (8 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 09/25] net/bnxt: fix the function id used in the flow flush Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 11/25] net/bnxt: fix crash in VF rep queue selection Ajit Khaparde
                   ` (15 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Shahaji Bhosle

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

When parent VF or PF ports are cleaned up, the child VF representor
ports also need to be cleaned up. If not cleaned up, then deleting
the parent VF shall result in not cleaning up the hardware rules and
updating the firmware of vfr removal. The issue can occur even when
OVS is exited without deleting vfr ports.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
---
 drivers/net/bnxt/bnxt_ethdev.c     | 20 ++++++++++++++--
 drivers/net/bnxt/bnxt_reps.c       | 38 ++++++++++++++++++++++++++----
 drivers/net/bnxt/bnxt_reps.h       |  1 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c |  4 ++--
 4 files changed, 55 insertions(+), 8 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index bc9aeba08..ea81ff149 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1307,6 +1307,9 @@ static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 	/* disable uio/vfio intr/eventfd mapping */
 	rte_intr_disable(intr_handle);
 
+	/* Stop the child representors for this device */
+	bnxt_vf_rep_stop_all(bp);
+
 	/* delete the bnxt ULP port details */
 	bnxt_ulp_port_deinit(bp);
 
@@ -3709,8 +3712,13 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
 		struct bnxt_vf_representor *vfr = dev->data->dev_private;
 		bp = vfr->parent_dev->data->dev_private;
 		/* parent is deleted while children are still valid */
-		if (!bp)
+		if (!bp) {
+			PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
+				    dev->data->port_id,
+				    filter_type,
+				    filter_op);
 			return -EIO;
+		}
 	}
 
 	ret = is_bnxt_in_error(bp);
@@ -5912,8 +5920,12 @@ static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
 		vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
 		if (!vf_rep_eth_dev)
 			continue;
+		PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
+			    vf_rep_eth_dev->data->port_id);
 		rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
 	}
+	PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
+		    eth_dev->data->port_id);
 	ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
 
 	return ret;
@@ -6040,6 +6052,8 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 				ret = -ENODEV;
 				return ret;
 			}
+			PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
+				    backing_eth_dev->data->port_id);
 			backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
 				vf_rep_eth_dev;
 			backing_bp->num_reps++;
@@ -6088,7 +6102,8 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 
 		backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
 	}
-
+	PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
+		    backing_eth_dev->data->port_id);
 	/* probe representor ports now */
 	ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
 
@@ -6107,6 +6122,7 @@ static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
 			   * +ve value will at least help in proper cleanup
 			   */
 
+	PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 			return rte_eth_dev_destroy(eth_dev,
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 3101512c3..9f535c0ce 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -167,6 +167,7 @@ int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
 	struct rte_eth_link *link;
 	struct bnxt *parent_bp;
 
+	PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR init\n", eth_dev->data->port_id);
 	vf_rep_bp->vf_id = rep_params->vf_id;
 	vf_rep_bp->switch_domain_id = rep_params->switch_domain_id;
 	vf_rep_bp->parent_dev = rep_params->parent_dev;
@@ -217,15 +218,18 @@ int bnxt_vf_representor_uninit(struct rte_eth_dev *eth_dev)
 	struct bnxt *parent_bp;
 	struct bnxt_vf_representor *rep =
 		(struct bnxt_vf_representor *)eth_dev->data->dev_private;
-
 	uint16_t vf_id;
 
+	PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR uninit\n", eth_dev->data->port_id);
 	eth_dev->data->mac_addrs = NULL;
 	eth_dev->dev_ops = NULL;
 
 	parent_bp = rep->parent_dev->data->dev_private;
-	if (!parent_bp)
+	if (!parent_bp) {
+		PMD_DRV_LOG(DEBUG, "BNXT Port:%d already freed\n",
+			    eth_dev->data->port_id);
 		return 0;
+	}
 
 	parent_bp->num_reps--;
 	vf_id = rep->vf_id;
@@ -297,7 +301,8 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 			    vfr->vf_id, rc);
 		(void)bnxt_ulp_delete_vfr_default_rules(vfr);
 	}
-
+	BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR created and initialized\n",
+		    vfr->dpdk_port_id);
 	return rc;
 }
 
@@ -362,6 +367,7 @@ int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 	parent_bp = rep_bp->parent_dev->data->dev_private;
 	rep_info = &parent_bp->rep_info[rep_bp->vf_id];
 
+	BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR start\n", eth_dev->data->port_id);
 	pthread_mutex_lock(&rep_info->vfr_start_lock);
 	if (!rep_info->conduit_valid) {
 		rc = bnxt_get_dflt_vnic_svif(parent_bp, rep_bp);
@@ -387,6 +393,7 @@ int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 
 static int bnxt_tf_vfr_free(struct bnxt_vf_representor *vfr)
 {
+	BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR ulp free\n", vfr->dpdk_port_id);
 	return bnxt_ulp_delete_vfr_default_rules(vfr);
 }
 
@@ -402,8 +409,11 @@ static int bnxt_vfr_free(struct bnxt_vf_representor *vfr)
 	}
 
 	parent_bp = vfr->parent_dev->data->dev_private;
-	if (!parent_bp)
+	if (!parent_bp) {
+		PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR already freed\n",
+			    vfr->dpdk_port_id);
 		return 0;
+	}
 
 	/* Check if representor has been already freed in FW */
 	if (!vfr->vfr_tx_cfa_action)
@@ -433,6 +443,8 @@ void bnxt_vf_rep_dev_stop_op(struct rte_eth_dev *eth_dev)
 	eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 	eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 
+	BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR stop\n", eth_dev->data->port_id);
+
 	bnxt_vfr_free(vfr_bp);
 
 	if (eth_dev->data->dev_started)
@@ -443,6 +455,7 @@ void bnxt_vf_rep_dev_stop_op(struct rte_eth_dev *eth_dev)
 
 void bnxt_vf_rep_dev_close_op(struct rte_eth_dev *eth_dev)
 {
+	BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR close\n", eth_dev->data->port_id);
 	bnxt_vf_representor_uninit(eth_dev);
 }
 
@@ -722,3 +735,20 @@ int bnxt_vf_rep_stats_reset_op(struct rte_eth_dev *eth_dev)
 	}
 	return 0;
 }
+
+void bnxt_vf_rep_stop_all(struct bnxt *bp)
+{
+	uint16_t vf_id;
+	struct rte_eth_dev *rep_eth_dev;
+
+	/* No vfrep ports just exit */
+	if (!bp->rep_info)
+		return;
+
+	for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) {
+		rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev;
+		if (!rep_eth_dev)
+			continue;
+		bnxt_vf_rep_dev_stop_op(rep_eth_dev);
+	}
+}
diff --git a/drivers/net/bnxt/bnxt_reps.h b/drivers/net/bnxt/bnxt_reps.h
index 418b95afc..d877b0823 100644
--- a/drivers/net/bnxt/bnxt_reps.h
+++ b/drivers/net/bnxt/bnxt_reps.h
@@ -42,4 +42,5 @@ void bnxt_vf_rep_dev_close_op(struct rte_eth_dev *eth_dev);
 int bnxt_vf_rep_stats_get_op(struct rte_eth_dev *eth_dev,
 			     struct rte_eth_stats *stats);
 int bnxt_vf_rep_stats_reset_op(struct rte_eth_dev *eth_dev);
+void bnxt_vf_rep_stop_all(struct bnxt *bp);
 #endif /* _BNXT_REPS_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 63d453ffb..272536473 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -905,7 +905,7 @@ bnxt_ulp_port_init(struct bnxt *bp)
 	}
 	/* create the default rules */
 	bnxt_ulp_create_df_rules(bp);
-	BNXT_TF_DBG(DEBUG, "ULP Port:%d created and initialized\n",
+	BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init\n",
 		    bp->eth_dev->data->port_id);
 	return rc;
 
@@ -940,7 +940,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
 		return;
 	}
 
-	BNXT_TF_DBG(DEBUG, "ULP Port:%d destroyed\n",
+	BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port deinit\n",
 		    bp->eth_dev->data->port_id);
 
 	/* Get the session details  */
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 11/25] net/bnxt: fix crash in VF rep queue selection
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (9 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 10/25] net/bnxt: vfr port clean up during port stop Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 12/25] net/bnxt: fix to conditionally rollback added VF-rep ports Ajit Khaparde
                   ` (14 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, Venkat Duvvuru

From: Somnath Kotur <somnath.kotur@broadcom.com>

Instead of bounds checking against max possible rings while selecting
queue index for the VF rep, do it against the configured number of rings.

Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
 drivers/net/bnxt/bnxt_reps.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 9f535c0ce..6fa867a8a 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -45,9 +45,12 @@ bnxt_vfr_recv(uint16_t port_id, uint16_t queue_id, struct rte_mbuf *mbuf)
 
 	vfr_eth_dev = &rte_eth_devices[port_id];
 	vfr_bp = vfr_eth_dev->data->dev_private;
-	/* If rxq_id happens to be > max rep_queue, use rxq0 */
-	que = queue_id < BNXT_MAX_VF_REP_RINGS ? queue_id : 0;
+	/* If rxq_id happens to be > nr_rings, use ring 0 */
+	que = queue_id < vfr_bp->rx_nr_rings ? queue_id : 0;
 	rep_rxq = vfr_bp->rx_queues[que];
+	/* Ideally should not happen now, paranoid check */
+	if (!rep_rxq)
+		return 1;
 	rep_rxr = rep_rxq->rx_ring;
 	mask = rep_rxr->rx_ring_struct->ring_mask;
 
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 12/25] net/bnxt: fix to conditionally rollback added VF-rep ports
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (10 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 11/25] net/bnxt: fix crash in VF rep queue selection Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 13/25] net/bnxt: update resource allocation settings Ajit Khaparde
                   ` (13 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, Venkat Duvvuru

From: Somnath Kotur <somnath.kotur@broadcom.com>

If VF-rep port add fails for some reason, code was rolling back
all ports added so far. With OVS-DPDK particularly, there is no need
to do that, just log failure message for the VF rep port add and continue.
Also include RTE_MAX_ETH_PORTS value in the bounds check as one port
will be taken by the uplink port anyway

Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
 drivers/net/bnxt/bnxt_ethdev.c | 44 ++++++++++++++++++++--------------
 1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index ea81ff149..043637db6 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -5999,7 +5999,7 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 		return -EINVAL;
 	}
 
-	if (num_rep > RTE_MAX_ETHPORTS) {
+	if (num_rep >= RTE_MAX_ETHPORTS) {
 		PMD_DRV_LOG(ERR,
 			    "nb_representor_ports = %d > %d MAX ETHPORTS\n",
 			    num_rep, RTE_MAX_ETHPORTS);
@@ -6042,28 +6042,36 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 					 NULL, NULL,
 					 bnxt_vf_representor_init,
 					 &representor);
-
-		if (!ret) {
-			vf_rep_eth_dev = rte_eth_dev_allocated(name);
-			if (!vf_rep_eth_dev) {
-				PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
-					    " for VF-Rep: %s.", name);
-				bnxt_pci_remove_dev_with_reps(backing_eth_dev);
-				ret = -ENODEV;
-				return ret;
-			}
-			PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
-				    backing_eth_dev->data->port_id);
-			backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
-				vf_rep_eth_dev;
-			backing_bp->num_reps++;
-		} else {
+		if (ret) {
 			PMD_DRV_LOG(ERR, "failed to create bnxt vf "
 				    "representor %s.", name);
-			bnxt_pci_remove_dev_with_reps(backing_eth_dev);
+			goto err;
 		}
+
+		vf_rep_eth_dev = rte_eth_dev_allocated(name);
+		if (!vf_rep_eth_dev) {
+			PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
+				    " for VF-Rep: %s.", name);
+			ret = -ENODEV;
+			goto err;
+		}
+
+		PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
+				backing_eth_dev->data->port_id);
+		backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
+							 vf_rep_eth_dev;
+		backing_bp->num_reps++;
 	}
 
+	return 0;
+
+err:
+	/* If num_rep > 1, then rollback already created
+	 * ports, since we'll be failing the probe anyway
+	 */
+	if (num_rep > 1)
+		bnxt_pci_remove_dev_with_reps(backing_eth_dev);
+
 	return ret;
 }
 
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 13/25] net/bnxt: update resource allocation settings
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (11 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 12/25] net/bnxt: fix to conditionally rollback added VF-rep ports Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 14/25] net/bnxt: move IF tbl from tunneled to direct HWRM msg Ajit Khaparde
                   ` (12 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Shahaji Bhosle, Kishore Padmanabha

From: Shahaji Bhosle <sbhosle@broadcom.com>

Update resource as default configuration

Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 272536473..7650c7167 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -85,9 +85,9 @@ ulp_ctx_session_open(struct bnxt *bp,
 	/* Identifiers */
 	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 422;
 	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6;
-	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 8;
-	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 8;
-	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 8;
+	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 192;
+	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64;
+	resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 192;
 
 	/* Table Types */
 	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
@@ -95,7 +95,7 @@ ulp_ctx_session_open(struct bnxt *bp,
 	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023;
 
 	/* ENCAP */
-	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255;
+	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 511;
 	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 63;
 
 	/* TCAMs */
@@ -103,22 +103,25 @@ ulp_ctx_session_open(struct bnxt *bp,
 		422;
 	resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
 		6;
-	resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 8;
+	resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960;
 	resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 88;
 
 	/* EM */
-	resources->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13176;
+	resources->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13168;
 
 	/* EEM */
 	resources->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_TBL_SCOPE] = 1;
 
+	/* SP */
+	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 255;
+
 	/** TX **/
 	/* Identifiers */
 	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 292;
-	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 144;
-	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 8;
-	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 8;
-	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 8;
+	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 148;
+	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 192;
+	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64;
+	resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 192;
 
 	/* Table Types */
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
@@ -127,7 +130,7 @@ ulp_ctx_session_open(struct bnxt *bp,
 
 	/* ENCAP */
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 511;
-	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 200;
+	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 223;
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255;
 
 	/* TCAMs */
@@ -135,8 +138,8 @@ ulp_ctx_session_open(struct bnxt *bp,
 		292;
 	resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
 		144;
-	resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 8;
-	resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 8;
+	resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960;
+	resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 928;
 
 	/* EM */
 	resources->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232;
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 14/25] net/bnxt: move IF tbl from tunneled to direct HWRM msg
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (12 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 13/25] net/bnxt: update resource allocation settings Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 15/25] net/bnxt: remove VLAN pop action for egress flows Ajit Khaparde
                   ` (11 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Randy Schacher, Shahaji Bhosle

From: Randy Schacher <stuart.schacher@broadcom.com>

Change IF tbl from tunneled to non-tunneled HWRM msg.

Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
---
 drivers/net/bnxt/hsi_struct_def_dpdk.h | 935 ++++++++++++++++++-------
 drivers/net/bnxt/tf_core/tf_msg.c      |  58 +-
 2 files changed, 706 insertions(+), 287 deletions(-)

diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index fb4f712ce..915b4274e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -341,9 +341,9 @@ struct cmd_nums {
 	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        UINT32_C(0x52)
 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     UINT32_C(0x53)
 	#define HWRM_RING_AGGINT_QCAPS                    UINT32_C(0x54)
-	#define HWRM_RING_SQ_ALLOC                        UINT32_C(0x55)
-	#define HWRM_RING_SQ_CFG                          UINT32_C(0x56)
-	#define HWRM_RING_SQ_FREE                         UINT32_C(0x57)
+	#define HWRM_RING_SCHQ_ALLOC                      UINT32_C(0x55)
+	#define HWRM_RING_SCHQ_CFG                        UINT32_C(0x56)
+	#define HWRM_RING_SCHQ_FREE                       UINT32_C(0x57)
 	#define HWRM_RING_RESET                           UINT32_C(0x5e)
 	#define HWRM_RING_GRP_ALLOC                       UINT32_C(0x60)
 	#define HWRM_RING_GRP_FREE                        UINT32_C(0x61)
@@ -413,6 +413,7 @@ struct cmd_nums {
 	#define HWRM_FW_IPC_MAILBOX                       UINT32_C(0xcc)
 	#define HWRM_FW_ECN_CFG                           UINT32_C(0xcd)
 	#define HWRM_FW_ECN_QCFG                          UINT32_C(0xce)
+	#define HWRM_FW_SECURE_CFG                        UINT32_C(0xcf)
 	#define HWRM_EXEC_FWD_RESP                        UINT32_C(0xd0)
 	#define HWRM_REJECT_FWD_RESP                      UINT32_C(0xd1)
 	#define HWRM_FWD_RESP                             UINT32_C(0xd2)
@@ -704,6 +705,10 @@ struct cmd_nums {
 	/* Experimental */
 	#define HWRM_TF_GLOBAL_CFG_GET                    UINT32_C(0x2fd)
 	/* Experimental */
+	#define HWRM_TF_IF_TBL_SET                        UINT32_C(0x2fe)
+	/* Experimental */
+	#define HWRM_TF_IF_TBL_GET                        UINT32_C(0x2ff)
+	/* Experimental */
 	#define HWRM_SV                                   UINT32_C(0x400)
 	/* Experimental */
 	#define HWRM_DBG_READ_DIRECT                      UINT32_C(0xff10)
@@ -942,8 +947,8 @@ struct hwrm_err_output {
 #define HWRM_VERSION_MINOR 10
 #define HWRM_VERSION_UPDATE 1
 /* non-zero means beta version */
-#define HWRM_VERSION_RSVD 48
-#define HWRM_VERSION_STR "1.10.1.48"
+#define HWRM_VERSION_RSVD 56
+#define HWRM_VERSION_STR "1.10.1.56"
 
 /****************
  * hwrm_ver_get *
@@ -2204,16 +2209,18 @@ struct rx_prod_pkt_bd {
 	 */
 	#define RX_PROD_PKT_BD_FLAGS_EOP_PAD      UINT32_C(0x80)
 	/*
+	 * This field has been deprecated. There can be no additional
+	 * BDs for this packet from this ring.
+	 *
+	 * Old definition:
 	 * This value is the number of additional buffers in the ring that
 	 * describe the buffer space to be consumed for this packet.
 	 * If the value is zero, then the packet must fit within the
 	 * space described by this BD. If this value is 1 or more, it
 	 * indicates how many additional "buffer" BDs are in the ring
 	 * immediately following this BD to be used for the same
-	 * network packet.
-	 *
-	 * Even if the packet to be placed does not need all the
-	 * additional buffers, they will be consumed anyway.
+	 * network packet. Even if the packet to be placed does not need
+	 * all the additional buffers, they will be consumed anyway.
 	 */
 	#define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
 	#define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT  8
@@ -3585,16 +3592,36 @@ struct rx_pkt_v2_cmpl {
 	 * truncation placement is used, this value represents the placed
 	 * (truncated) length of the packet.
 	 */
-	#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK    UINT32_C(0x1ff)
-	#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT     0
+	#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK        UINT32_C(0x1ff)
+	#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT         0
 	/* This is data from the CFA as indicated by the meta_format field. */
-	#define RX_PKT_V2_CMPL_METADATA1_MASK         UINT32_C(0xf000)
-	#define RX_PKT_V2_CMPL_METADATA1_SFT          12
-	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
-	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
-	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT  12
+	#define RX_PKT_V2_CMPL_METADATA1_MASK             UINT32_C(0xf000)
+	#define RX_PKT_V2_CMPL_METADATA1_SFT              12
 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
-	#define RX_PKT_V2_CMPL_METADATA1_VALID         UINT32_C(0x8000)
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK     UINT32_C(0x7000)
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT      12
+	/* 0x88a8 */
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
+		(UINT32_C(0x0) << 12)
+	/* 0x8100 */
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
+		(UINT32_C(0x1) << 12)
+	/* 0x9100 */
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
+		(UINT32_C(0x2) << 12)
+	/* 0x9200 */
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
+		(UINT32_C(0x3) << 12)
+	/* 0x9300 */
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
+		(UINT32_C(0x4) << 12)
+	/* Value programmed in CFA VLANTPID register. */
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
+		(UINT32_C(0x5) << 12)
+	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
+		RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
+	/* When meta_format != 0, this value is the VLAN valid. */
+	#define RX_PKT_V2_CMPL_METADATA1_VALID             UINT32_C(0x8000)
 	/*
 	 * This value is the RSS hash value calculated for the packet
 	 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
@@ -4484,15 +4511,38 @@ struct rx_tpa_start_v2_cmpl {
 	 * with. Use this number to correlate the TPA start completion
 	 * with the TPA end completion.
 	 */
-	#define RX_TPA_START_V2_CMPL_AGG_ID_MASK            UINT32_C(0xfff)
-	#define RX_TPA_START_V2_CMPL_AGG_ID_SFT             0
-	#define RX_TPA_START_V2_CMPL_METADATA1_MASK         UINT32_C(0xf000)
-	#define RX_TPA_START_V2_CMPL_METADATA1_SFT          12
+	#define RX_TPA_START_V2_CMPL_AGG_ID_MASK                UINT32_C(0xfff)
+	#define RX_TPA_START_V2_CMPL_AGG_ID_SFT                 0
+	#define RX_TPA_START_V2_CMPL_METADATA1_MASK \
+		UINT32_C(0xf000)
+	#define RX_TPA_START_V2_CMPL_METADATA1_SFT              12
 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
-	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
-	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT  12
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
+		UINT32_C(0x7000)
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT      12
+	/* 0x88a8 */
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
+		(UINT32_C(0x0) << 12)
+	/* 0x8100 */
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
+		(UINT32_C(0x1) << 12)
+	/* 0x9100 */
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
+		(UINT32_C(0x2) << 12)
+	/* 0x9200 */
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
+		(UINT32_C(0x3) << 12)
+	/* 0x9300 */
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
+		(UINT32_C(0x4) << 12)
+	/* Value programmed in CFA VLANTPID register. */
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
+		(UINT32_C(0x5) << 12)
+	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
+		RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
 	/* When meta_format != 0, this value is the VLAN valid. */
-	#define RX_TPA_START_V2_CMPL_METADATA1_VALID         UINT32_C(0x8000)
+	#define RX_TPA_START_V2_CMPL_METADATA1_VALID \
+		UINT32_C(0x8000)
 	/*
 	 * This value is the RSS hash value calculated for the packet
 	 * based on the mode bits and key value in the VNIC.
@@ -8908,6 +8958,13 @@ struct hwrm_func_vf_cfg_input {
 	 */
 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
 		UINT32_C(0x100)
+	/*
+	 * If this bit is set to 1, the VF driver is requesting FW to disable
+	 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
+	 * ignored if the VF doesn't support PPP tx push feature.
+	 */
+	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
+		UINT32_C(0x200)
 	/* The number of RSS/COS contexts requested for the VF. */
 	uint16_t	num_rsscos_ctxs;
 	/* The number of completion rings requested for the VF. */
@@ -9396,10 +9453,10 @@ struct hwrm_func_qcaps_output {
 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
 		UINT32_C(0x20)
 	/*
-	 * If 1, the device supports scheduler queues. SQs can be managed
-	 * using RING_SQ_ALLOC/CFG/FREE commands.
+	 * If 1, the device supports scheduler queues. SCHQs can be managed
+	 * using RING_SCHQ_ALLOC/CFG/FREE commands.
 	 */
-	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SQ_SUPPORTED \
+	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
 		UINT32_C(0x40)
 	/*
 	 * If set to 1, then this function supports the TX push mode that
@@ -9407,8 +9464,8 @@ struct hwrm_func_qcaps_output {
 	 */
 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
 		UINT32_C(0x80)
-	/* The maximum number of SQs supported by this device. */
-	uint8_t	max_sqs;
+	/* The maximum number of SCHQs supported by this device. */
+	uint8_t	max_schqs;
 	uint8_t	unused_1[2];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -10159,6 +10216,15 @@ struct hwrm_func_cfg_input {
 	 */
 	#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
 		UINT32_C(0x8000000)
+	/*
+	 * If this bit is set to 1, the PF driver is requesting FW
+	 * to disable PPP TX PUSH feature on all the TX rings specified in
+	 * the num_tx_rings field. This flag is ignored if num_tx_rings
+	 * field is not specified or the function doesn't support PPP tx
+	 * push feature.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
+		UINT32_C(0x10000000)
 	uint32_t	enables;
 	/*
 	 * This bit must be '1' for the mtu field to be
@@ -10305,10 +10371,10 @@ struct hwrm_func_cfg_input {
 	#define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
 		UINT32_C(0x800000)
 	/*
-	 * This bit must be '1' for the sq_id field to be
+	 * This bit must be '1' for the schq_id field to be
 	 * configured.
 	 */
-	#define HWRM_FUNC_CFG_INPUT_ENABLES_SQ_ID \
+	#define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
 		UINT32_C(0x1000000)
 	/*
 	 * The maximum transmission unit of the function.
@@ -10574,8 +10640,8 @@ struct hwrm_func_cfg_input {
 	 * be reserved for this function on the RX side.
 	 */
 	uint16_t	num_mcast_filters;
-	/* Used by a PF driver to associate a SQ with a VF. */
-	uint16_t	sq_id;
+	/* Used by a PF driver to associate a SCHQ with a VF. */
+	uint16_t	schq_id;
 	uint8_t	unused_0[6];
 } __rte_packed;
 
@@ -10808,12 +10874,12 @@ struct hwrm_func_qstats_ext_input {
 	uint8_t	unused_0[1];
 	uint32_t	enables;
 	/*
-	 * This bit must be '1' for the sq_id and traffic_class fields to be
-	 * configured.
+	 * This bit must be '1' for the schq_id and traffic_class fields to
+	 * be configured.
 	 */
-	#define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SQ_ID     UINT32_C(0x1)
-	/* Specifies the SQ for which to gather statistics */
-	uint16_t	sq_id;
+	#define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID     UINT32_C(0x1)
+	/* Specifies the SCHQ for which to gather statistics */
+	uint16_t	schq_id;
 	/*
 	 * Specifies the traffic class for which to gather statistics. Valid
 	 * values are 0 through (max_configurable_queues - 1), where
@@ -15275,7 +15341,14 @@ struct hwrm_port_phy_cfg_input {
 		UINT32_C(0x80)
 	/*
 	 * When set to 1, then the HWRM shall enable FEC autonegotitation
-	 * on this port if supported.
+	 * on this port if supported.  When enabled, at least one of the
+	 * FEC modes must be advertised by enabling the fec_clause_74_enable,
+	 * fec_clause_91_enable, fec_rs544_1xn_enable, or fec_rs544_2xn_enable
+	 * flag.  If none of the FEC mode is currently enabled, the HWRM
+	 * shall choose a default advertisement setting.
+	 * The default advertisment setting can be queried by calling
+	 * hwrm_port_phy_qcfg.  Note that the link speed must be
+	 * in autonegotiation mode for FEC autonegotiation to take effect.
 	 * When set to 0, then this flag shall be ignored.
 	 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
 	 * flag.
@@ -15293,7 +15366,8 @@ struct hwrm_port_phy_cfg_input {
 		UINT32_C(0x200)
 	/*
 	 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
-	 * on this port if supported.
+	 * on this port if supported, by advertising FEC CLAUSE 74 if
+	 * FEC autonegotiation is enabled or force enabled otherwise.
 	 * When set to 0, then this flag shall be ignored.
 	 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
 	 * flag.
@@ -15302,7 +15376,8 @@ struct hwrm_port_phy_cfg_input {
 		UINT32_C(0x400)
 	/*
 	 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
-	 * on this port if supported.
+	 * on this port if supported, by not advertising FEC CLAUSE 74 if
+	 * FEC autonegotiation is enabled or force disabled otherwise.
 	 * When set to 0, then this flag shall be ignored.
 	 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
 	 * flag.
@@ -15311,7 +15386,8 @@ struct hwrm_port_phy_cfg_input {
 		UINT32_C(0x800)
 	/*
 	 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
-	 * on this port if supported.
+	 * on this port if supported, by advertising FEC CLAUSE 91 if
+	 * FEC autonegotiation is enabled or force enabled otherwise.
 	 * When set to 0, then this flag shall be ignored.
 	 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
 	 * flag.
@@ -15320,7 +15396,8 @@ struct hwrm_port_phy_cfg_input {
 		UINT32_C(0x1000)
 	/*
 	 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
-	 * on this port if supported.
+	 * on this port if supported, by not advertising FEC CLAUSE 91 if
+	 * FEC autonegotiation is enabled or force disabled otherwise.
 	 * When set to 0, then this flag shall be ignored.
 	 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
 	 * flag.
@@ -15347,6 +15424,46 @@ struct hwrm_port_phy_cfg_input {
 	 */
 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
 		UINT32_C(0x4000)
+	/*
+	 * When set to 1, then the HWRM shall enable FEC RS544_1XN
+	 * on this port if supported, by advertising FEC RS544_1XN if
+	 * FEC autonegotiation is enabled or force enabled otherwise.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
+	 * flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
+		UINT32_C(0x8000)
+	/*
+	 * When set to 1, then the HWRM shall disable FEC RS544_1XN
+	 * on this port if supported, by not advertising FEC RS544_1XN if
+	 * FEC autonegotiation is enabled or force disabled otherwise.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS544_1XN  is not supported, then the HWRM shall ignore this
+	 * flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
+		UINT32_C(0x10000)
+	/*
+	 * When set to 1, then the HWRM shall enable FEC RS544_2XN
+	 * on this port if supported, by advertising FEC RS544_2XN if
+	 * FEC autonegotiation is enabled or force enabled otherwise.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS544_2XN is not supported, then the HWRM shall ignore this
+	 * flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_ENABLE \
+		UINT32_C(0x20000)
+	/*
+	 * When set to 1, then the HWRM shall disable FEC RS544_2XN
+	 * on this port if supported, by not advertising FEC RS544_2XN if
+	 * FEC autonegotiation is enabled or force disabled otherwise.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS544_2XN  is not supported, then the HWRM shall ignore this
+	 * flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_DISABLE \
+		UINT32_C(0x40000)
 	uint32_t	enables;
 	/*
 	 * This bit must be '1' for the auto_mode field to be
@@ -16573,9 +16690,6 @@ struct hwrm_port_phy_qcfg_output {
 	 * is set to 1, then all other FEC configuration flags shall be ignored.
 	 * When set to 0, then FEC is supported as indicated by other
 	 * configuration flags.
-	 * If no cable is attached and the HWRM does not yet know the FEC
-	 * capability, then the HWRM shall set this flag to 1 when reporting
-	 * FEC capability.
 	 */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
 		UINT32_C(0x1)
@@ -16599,7 +16713,9 @@ struct hwrm_port_phy_qcfg_output {
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
 		UINT32_C(0x8)
 	/*
-	 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
+	 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
+	 * port. This means that FEC CLAUSE 74 is either advertised if
+	 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
 	 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
 	 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
 	 */
@@ -16612,12 +16728,84 @@ struct hwrm_port_phy_qcfg_output {
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
 		UINT32_C(0x20)
 	/*
-	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
+	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this
+	 * port. This means that FEC CLAUSE 91 is either advertised if
+	 * FEC autonegotiation is enabled or FEC CLAUSE 91 is force enabled.
 	 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
 	 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
 	 */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
 		UINT32_C(0x40)
+	/*
+	 * When set to 1, then FEC RS544_1XN is supported on this port.
+	 * When set to 0, then FEC RS544_1XN is not supported on this port.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
+		UINT32_C(0x80)
+	/*
+	 * When set to 1, then RS544_1XN is enabled on this
+	 * port. This means that FEC RS544_1XN is either advertised if
+	 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
+	 * When set to 0, then FEC RS544_1XN is disabled if supported.
+	 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
+		UINT32_C(0x100)
+	/*
+	 * When set to 1, then FEC RS544_2XN is supported on this port.
+	 * When set to 0, then FEC RS544_2XN is not supported on this port.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_SUPPORTED \
+		UINT32_C(0x200)
+	/*
+	 * When set to 1, then RS544_2XN is enabled on this
+	 * port. This means that FEC RS544_2XN is either advertised if
+	 * FEC autonegotiation is enabled or FEC RS544_2XN is force enabled.
+	 * When set to 0, then FEC RS544_2XN is disabled if supported.
+	 * This flag should be ignored if FEC RS544_2XN is not supported on this port.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ENABLED \
+		UINT32_C(0x400)
+	/*
+	 * When set to 1, then FEC CLAUSE 74 (Fire Code) is active on this
+	 * port, either successfully autonegoatiated or forced.
+	 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not active.
+	 * This flag is only valid when link is up on this port.
+	 * At most only one active FEC flags (fec_clause74_active,
+	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ACTIVE \
+		UINT32_C(0x800)
+	/*
+	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is active on this
+	 * port, either successfully autonegoatiated or forced.
+	 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not active.
+	 * This flag is only valid when link is up on this port.
+	 * At most only one active FEC flags (fec_clause74_active,
+	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ACTIVE \
+		UINT32_C(0x1000)
+	/*
+	 * When set to 1, then FEC RS544_1XN is active on this
+	 * port, either successfully autonegoatiated or forced.
+	 * When set to 0, then FEC RS544_1XN is not active.
+	 * This flag is only valid when link is up on this port.
+	 * At most only one active FEC flags (fec_clause74_active,
+	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ACTIVE \
+		UINT32_C(0x2000)
+	/*
+	 * When set to 1, then FEC RS544_2XN is active on this
+	 * port, either successfully autonegoatiated or forced.
+	 * When set to 0, then FEC RS544_2XN is not active.
+	 * This flag is only valid when link is up on this port.
+	 * At most only one active FEC flags (fec_clause74_active,
+	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ACTIVE \
+		UINT32_C(0x4000)
 	/*
 	 * This value is indicates the duplex of the current
 	 * connection state.
@@ -19079,13 +19267,24 @@ struct hwrm_port_phy_qcaps_output {
 	 */
 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
 		UINT32_C(0x8)
+	/*
+	 * If set to 1, it indicates that the port counters and extended
+	 * port counters will not reset when the firmware shuts down or
+	 * resets the PHY.  These counters will only be reset during power
+	 * cycle or by calling HWRM_PORT_CLR_STATS.
+	 * If set to 0, the state of the counters is unspecified when
+	 * firmware shuts down or resets the PHY.
+	 */
+	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
+		UINT32_C(0x10)
 	/*
 	 * Reserved field. The HWRM shall set this field to 0.
 	 * An HWRM client shall ignore this field.
 	 */
 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
-		UINT32_C(0xf0)
-	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT                    4
+		UINT32_C(0xe0)
+	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \
+		5
 	/* Number of front panel ports for this device. */
 	uint8_t	port_cnt;
 	/* Not supported or unknown */
@@ -21251,7 +21450,7 @@ struct hwrm_queue_qportcfg_input {
 	uint8_t	unused_0;
 } __rte_packed;
 
-/* hwrm_queue_qportcfg_output (size:256b/32B) */
+/* hwrm_queue_qportcfg_output (size:1344b/168B) */
 struct hwrm_queue_qportcfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
@@ -21627,6 +21826,28 @@ struct hwrm_queue_qportcfg_output {
 		UINT32_C(0xff)
 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
 		HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
+	uint8_t	unused_0;
+	/*
+	 * Up to 16 bytes of null padded ASCII string describing this queue.
+	 * The queue name includes a CoS queue index and, in some cases, text
+	 * that distinguishes the queue from other queues in the group.
+	 */
+	char	qid0_name[16];
+	/* Up to 16 bytes of null padded ASCII string describing this queue. */
+	char	qid1_name[16];
+	/* Up to 16 bytes of null padded ASCII string describing this queue. */
+	char	qid2_name[16];
+	/* Up to 16 bytes of null padded ASCII string describing this queue. */
+	char	qid3_name[16];
+	/* Up to 16 bytes of null padded ASCII string describing this queue. */
+	char	qid4_name[16];
+	/* Up to 16 bytes of null padded ASCII string describing this queue. */
+	char	qid5_name[16];
+	/* Up to 16 bytes of null padded ASCII string describing this queue. */
+	char	qid6_name[16];
+	/* Up to 16 bytes of null padded ASCII string describing this queue. */
+	char	qid7_name[16];
+	uint8_t	unused_1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -26929,10 +27150,10 @@ struct hwrm_ring_alloc_input {
 	#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
 		UINT32_C(0x100)
 	/*
-	 * This bit must be '1' for the sq_id field to be
+	 * This bit must be '1' for the schq_id field to be
 	 * configured.
 	 */
-	#define HWRM_RING_ALLOC_INPUT_ENABLES_SQ_ID \
+	#define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
 		UINT32_C(0x200)
 	/* Ring Type. */
 	uint8_t	ring_type;
@@ -26999,8 +27220,8 @@ struct hwrm_ring_alloc_input {
 	 *    element of the ring.
 	 */
 	uint8_t	page_tbl_depth;
-	/* Used by a PF driver to associate a SQ with one of its TX rings. */
-	uint16_t	sq_id;
+	/* Used by a PF driver to associate a SCHQ with one of its TX rings. */
+	uint16_t	schq_id;
 	/*
 	 * Number of 16B units in the ring.  Minimum size for
 	 * a ring is 16 16B entries.
@@ -27453,8 +27674,8 @@ struct hwrm_ring_cfg_input {
 	 */
 	#define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
 		UINT32_C(0x4)
-	/* The sq_id field is valid */
-	#define HWRM_RING_CFG_INPUT_ENABLES_SQ_ID \
+	/* The schq_id field is valid */
+	#define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
 		UINT32_C(0x8)
 	/* Update completion ring ID associated with Tx or Rx ring. */
 	#define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
@@ -27471,12 +27692,12 @@ struct hwrm_ring_cfg_input {
 	 */
 	uint16_t	proxy_fid;
 	/*
-	 * Identifies the new scheduler queue (SQ) to associate with the ring.
-	 * Only valid for Tx rings.
+	 * Identifies the new scheduler queue (SCHQ) to associate with the
+	 * ring. Only valid for Tx rings.
 	 * A value of zero indicates that the Tx ring should be associated
-	 * with the default scheduler queue (SQ).
+	 * with the default scheduler queue (SCHQ).
 	 */
-	uint16_t	sq_id;
+	uint16_t	schq_id;
 	/*
 	 * This field is valid for TX or Rx rings. This value identifies the
 	 * new completion ring ID to associate with the TX or Rx ring.
@@ -27622,12 +27843,12 @@ struct hwrm_ring_qcfg_output {
 	 */
 	uint16_t	proxy_fid;
 	/*
-	 * Identifies the new scheduler queue (SQ) to associate with the ring.
-	 * Only valid for Tx rings.
+	 * Identifies the new scheduler queue (SCHQ) to associate with the
+	 * ring. Only valid for Tx rings.
 	 * A value of zero indicates that the Tx ring should be associated with
-	 * the default scheduler queue (SQ).
+	 * the default scheduler queue (SCHQ).
 	 */
-	uint16_t	sq_id;
+	uint16_t	schq_id;
 	/*
 	 * This field is used when ring_type is a TX or Rx ring.
 	 * This value indicates what completion ring the TX or Rx ring
@@ -28222,13 +28443,13 @@ struct hwrm_ring_grp_free_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_ring_sq_alloc *
- **********************/
+/************************
+ * hwrm_ring_schq_alloc *
+ ************************/
 
 
-/* hwrm_ring_sq_alloc_input (size:1088b/136B) */
-struct hwrm_ring_sq_alloc_input {
+/* hwrm_ring_schq_alloc_input (size:1088b/136B) */
+struct hwrm_ring_schq_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -28262,380 +28483,396 @@ struct hwrm_ring_sq_alloc_input {
 	 * This bit must be '1' for the tqm_ring0 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING0     UINT32_C(0x1)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0     UINT32_C(0x1)
 	/*
 	 * This bit must be '1' for the tqm_ring1 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING1     UINT32_C(0x2)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1     UINT32_C(0x2)
 	/*
 	 * This bit must be '1' for the tqm_ring2 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING2     UINT32_C(0x4)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2     UINT32_C(0x4)
 	/*
 	 * This bit must be '1' for the tqm_ring3 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING3     UINT32_C(0x8)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3     UINT32_C(0x8)
 	/*
 	 * This bit must be '1' for the tqm_ring4 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING4     UINT32_C(0x10)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4     UINT32_C(0x10)
 	/*
 	 * This bit must be '1' for the tqm_ring5 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING5     UINT32_C(0x20)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5     UINT32_C(0x20)
 	/*
 	 * This bit must be '1' for the tqm_ring6 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING6     UINT32_C(0x40)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6     UINT32_C(0x40)
 	/*
 	 * This bit must be '1' for the tqm_ring7 fields to be
 	 * configured.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING7     UINT32_C(0x80)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7     UINT32_C(0x80)
 	/* Reserved for future use. */
 	uint32_t	reserved;
 	/* TQM ring 0 page size and level. */
 	uint8_t	tqm_ring0_pg_size_tqm_ring0_lvl;
 	/* TQM ring 0 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
 	/* TQM ring 0 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
 	/* TQM ring 1 page size and level. */
 	uint8_t	tqm_ring1_pg_size_tqm_ring1_lvl;
 	/* TQM ring 1 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
 	/* TQM ring 1 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
 	/* TQM ring 2 page size and level. */
 	uint8_t	tqm_ring2_pg_size_tqm_ring2_lvl;
 	/* TQM ring 2 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
 	/* TQM ring 2 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
 	/* TQM ring 3 page size and level. */
 	uint8_t	tqm_ring3_pg_size_tqm_ring3_lvl;
 	/* TQM ring 3 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
 	/* TQM ring 3 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
 	/* TQM ring 4 page size and level. */
 	uint8_t	tqm_ring4_pg_size_tqm_ring4_lvl;
 	/* TQM ring 4 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
 	/* TQM ring 4 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
 	/* TQM ring 5 page size and level. */
 	uint8_t	tqm_ring5_pg_size_tqm_ring5_lvl;
 	/* TQM ring 5 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
 	/* TQM ring 5 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
 	/* TQM ring 6 page size and level. */
 	uint8_t	tqm_ring6_pg_size_tqm_ring6_lvl;
 	/* TQM ring 6 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
 	/* TQM ring 6 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
 	/* TQM ring 7 page size and level. */
 	uint8_t	tqm_ring7_pg_size_tqm_ring7_lvl;
 	/* TQM ring 7 PBL indirect levels. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_MASK      UINT32_C(0xf)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_SFT       0
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
+		UINT32_C(0xf)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT       0
 	/* PBL pointer is physical start address. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
 		UINT32_C(0x0)
 	/* PBL pointer points to PTE table. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
 		UINT32_C(0x1)
 	/*
 	 * PBL pointer points to PDE table with each entry pointing to PTE
 	 * tables.
 	 */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
 		UINT32_C(0x2)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
 	/* TQM ring 7 page size. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK  UINT32_C(0xf0)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT   4
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT   4
 	/* 4KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
 		(UINT32_C(0x0) << 4)
 	/* 8KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
 		(UINT32_C(0x1) << 4)
 	/* 64KB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
 		(UINT32_C(0x2) << 4)
 	/* 2MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
 		(UINT32_C(0x3) << 4)
 	/* 8MB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
 		(UINT32_C(0x4) << 4)
 	/* 1GB. */
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
 		(UINT32_C(0x5) << 4)
-	#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
-		HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
+	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
+		HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
 	/* TQM ring 0 page directory. */
 	uint64_t	tqm_ring0_page_dir;
 	/* TQM ring 1 page directory. */
@@ -28661,7 +28898,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring0_num_entries;
 	/*
@@ -28673,7 +28910,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring1_num_entries;
 	/*
@@ -28685,7 +28922,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring2_num_entries;
 	/*
@@ -28697,7 +28934,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring3_num_entries;
 	/*
@@ -28709,7 +28946,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring4_num_entries;
 	/*
@@ -28721,7 +28958,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring5_num_entries;
 	/*
@@ -28733,7 +28970,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring6_num_entries;
 	/*
@@ -28745,7 +28982,7 @@ struct hwrm_ring_sq_alloc_input {
 	 *
 	 * Note that TQM ring sizes cannot be extended while the system is
 	 * operational. If a PF driver needs to extend a TQM ring, it needs
-	 * to delete the SQ and then reallocate it.
+	 * to delete the SCHQ and then reallocate it.
 	 */
 	uint32_t	tqm_ring7_num_entries;
 	/* Number of bytes that have been allocated for each context entry. */
@@ -28753,8 +28990,8 @@ struct hwrm_ring_sq_alloc_input {
 	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_ring_sq_alloc_output (size:128b/16B) */
-struct hwrm_ring_sq_alloc_output {
+/* hwrm_ring_schq_alloc_output (size:128b/16B) */
+struct hwrm_ring_schq_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -28764,11 +29001,11 @@ struct hwrm_ring_sq_alloc_output {
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
 	/*
-	 * This is an identifier for the SQ to be used in other HWRM commands
-	 * that need to reference this SQ. This value is greater than zero
-	 * (i.e. a sq_id of zero references the default SQ).
+	 * This is an identifier for the SCHQ to be used in other HWRM commands
+	 * that need to reference this SCHQ. This value is greater than zero
+	 * (i.e. a schq_id of zero references the default SCHQ).
 	 */
-	uint16_t	sq_id;
+	uint16_t	schq_id;
 	uint8_t	unused_0[5];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -28780,13 +29017,13 @@ struct hwrm_ring_sq_alloc_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/********************
- * hwrm_ring_sq_cfg *
- ********************/
+/**********************
+ * hwrm_ring_schq_cfg *
+ **********************/
 
 
-/* hwrm_ring_sq_cfg_input (size:768b/96B) */
-struct hwrm_ring_sq_cfg_input {
+/* hwrm_ring_schq_cfg_input (size:768b/96B) */
+struct hwrm_ring_schq_cfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -28816,23 +29053,23 @@ struct hwrm_ring_sq_cfg_input {
 	 */
 	uint64_t	resp_addr;
 	/*
-	 * Identifies the SQ being configured. A sq_id of zero refers to the
-	 * default SQ.
+	 * Identifies the SCHQ being configured. A schq_id of zero refers to
+	 * the default SCHQ.
 	 */
-	uint16_t	sq_id;
+	uint16_t	schq_id;
 	/*
 	 * This field is an 8 bit bitmap that indicates which TCs are enabled
-	 * in this SQ. Bit 0 represents traffic class 0 and bit 7 represents
+	 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
 	 * traffic class 7.
 	 */
 	uint8_t	tc_enabled;
 	uint8_t	unused_0;
 	uint32_t	flags;
 	/* The tc_max_bw array and the max_bw parameters are valid */
-	#define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
+	#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
 		UINT32_C(0x1)
 	/* The tc_min_bw array is valid */
-	#define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
+	#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
 		UINT32_C(0x2)
 	/* Maximum bandwidth of the traffic class, specified in Mbps. */
 	uint32_t	max_bw_tc0;
@@ -28854,68 +29091,68 @@ struct hwrm_ring_sq_cfg_input {
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc0;
 	/*
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc1;
 	/*
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc2;
 	/*
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc3;
 	/*
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc4;
 	/*
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc5;
 	/*
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc6;
 	/*
 	 * Bandwidth reservation for the traffic class, specified in Mbps.
 	 * A value of zero signifies that traffic belonging to this class
 	 * shares the bandwidth reservation for the same traffic class of
-	 * the default SQ.
+	 * the default SCHQ.
 	 */
 	uint32_t	min_bw_tc7;
 	/*
 	 * Indicates the max bandwidth for all enabled traffic classes in
-	 * this SQ, specified in Mbps.
+	 * this SCHQ, specified in Mbps.
 	 */
 	uint32_t	max_bw;
 	uint8_t	unused_1[4];
 } __rte_packed;
 
-/* hwrm_ring_sq_cfg_output (size:128b/16B) */
-struct hwrm_ring_sq_cfg_output {
+/* hwrm_ring_schq_cfg_output (size:128b/16B) */
+struct hwrm_ring_schq_cfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -28935,13 +29172,13 @@ struct hwrm_ring_sq_cfg_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*********************
- * hwrm_ring_sq_free *
- *********************/
+/***********************
+ * hwrm_ring_schq_free *
+ ***********************/
 
 
-/* hwrm_ring_sq_free_input (size:192b/24B) */
-struct hwrm_ring_sq_free_input {
+/* hwrm_ring_schq_free_input (size:192b/24B) */
+struct hwrm_ring_schq_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -28970,13 +29207,13 @@ struct hwrm_ring_sq_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Identifies the SQ being freed. */
-	uint16_t	sq_id;
+	/* Identifies the SCHQ being freed. */
+	uint16_t	schq_id;
 	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_ring_sq_free_output (size:128b/16B) */
-struct hwrm_ring_sq_free_output {
+/* hwrm_ring_schq_free_output (size:128b/16B) */
+struct hwrm_ring_schq_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38802,7 +39039,9 @@ struct hwrm_tf_global_cfg_set_input {
 	/* unused. */
 	uint8_t	unused0[6];
 	/* Data to set */
-	uint8_t	data[16];
+	uint8_t	data[8];
+	/* Mask of data to set, 0 indicates no mask */
+	uint8_t	mask[8];
 } __rte_packed;
 
 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
@@ -38903,6 +39142,182 @@ struct hwrm_tf_global_cfg_get_output {
 	uint8_t	data[16];
 } __rte_packed;
 
+/**********************
+ * hwrm_tf_if_tbl_get *
+ **********************/
+
+
+/* hwrm_tf_if_tbl_get_input (size:256b/32B) */
+struct hwrm_tf_if_tbl_get_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint16_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
+	/* Size of the data to set. */
+	uint16_t	size;
+	/*
+	 * Type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
+	 */
+	uint32_t	type;
+	/* Index of the type to retrieve. */
+	uint32_t	index;
+} __rte_packed;
+
+/* hwrm_tf_if_tbl_get_output (size:256b/32B) */
+struct hwrm_tf_if_tbl_get_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* Response code. */
+	uint32_t	resp_code;
+	/* Response size. */
+	uint16_t	size;
+	/* unused */
+	uint16_t	unused0;
+	/* Response data. */
+	uint8_t	data[8];
+	/* unused */
+	uint8_t	unused1[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/***************************
+ * hwrm_tf_if_tbl_type_set *
+ ***************************/
+
+
+/* hwrm_tf_if_tbl_set_input (size:384b/48B) */
+struct hwrm_tf_if_tbl_set_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint16_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
+	/* unused. */
+	uint8_t	unused0[2];
+	/*
+	 * Type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
+	 */
+	uint32_t	type;
+	/* Index of the type to set. */
+	uint32_t	index;
+	/* Size of the data to set. */
+	uint16_t	size;
+	/* unused */
+	uint8_t	unused1[6];
+	/* Data to be set. */
+	uint8_t	data[8];
+} __rte_packed;
+
+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
+struct hwrm_tf_if_tbl_set_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* unused. */
+	uint8_t	unused0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
 /******************************
  * hwrm_tunnel_dst_port_query *
  ******************************/
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index db471f625..7c2ad172f 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -1250,8 +1250,8 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,
 {
 	int rc = 0;
 	struct tfp_send_msg_parms parms = { 0 };
-	tf_if_tbl_get_input_t req = { 0 };
-	tf_if_tbl_get_output_t resp;
+	struct hwrm_tf_if_tbl_get_input req = { 0 };
+	struct hwrm_tf_if_tbl_get_output resp = { 0 };
 	uint32_t flags = 0;
 	struct tf_session *tfs;
 
@@ -1265,25 +1265,26 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,
 		return rc;
 	}
 
-	flags = (params->dir == TF_DIR_TX ? TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX :
-		 TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX);
+	flags = (params->dir == TF_DIR_TX ?
+		HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX :
+		HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX);
 
 	/* Populate the request */
 	req.fw_session_id =
 		tfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);
 	req.flags = flags;
-	req.tf_if_tbl_type = params->hcapi_type;
-	req.idx = tfp_cpu_to_le_16(params->idx);
-	req.data_sz_in_bytes = tfp_cpu_to_le_16(params->data_sz_in_bytes);
+	req.type = params->hcapi_type;
+	req.index = tfp_cpu_to_le_16(params->idx);
+	req.size = tfp_cpu_to_le_16(params->data_sz_in_bytes);
 
-	MSG_PREP(parms,
-		 TF_KONG_MB,
-		 HWRM_TF,
-		 HWRM_TFT_IF_TBL_GET,
-		 req,
-		 resp);
+	parms.tf_type = HWRM_TF_IF_TBL_GET;
+	parms.req_data = (uint32_t *)&req;
+	parms.req_size = sizeof(req);
+	parms.resp_data = (uint32_t *)&resp;
+	parms.resp_size = sizeof(resp);
+	parms.mailbox = TF_KONG_MB;
 
-	rc = tfp_send_msg_tunneled(tfp, &parms);
+	rc = tfp_send_msg_direct(tfp, &parms);
 
 	if (rc != 0)
 		return rc;
@@ -1291,7 +1292,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,
 	if (parms.tf_resp_code != 0)
 		return tfp_le_to_cpu_32(parms.tf_resp_code);
 
-	tfp_memcpy(&params->data[0], resp.data, req.data_sz_in_bytes);
+	tfp_memcpy(&params->data[0], resp.data, req.size);
 
 	return tfp_le_to_cpu_32(parms.tf_resp_code);
 }
@@ -1302,7 +1303,8 @@ tf_msg_set_if_tbl_entry(struct tf *tfp,
 {
 	int rc = 0;
 	struct tfp_send_msg_parms parms = { 0 };
-	tf_if_tbl_set_input_t req = { 0 };
+	struct hwrm_tf_if_tbl_set_input req = { 0 };
+	struct hwrm_tf_if_tbl_get_output resp = { 0 };
 	uint32_t flags = 0;
 	struct tf_session *tfs;
 
@@ -1317,25 +1319,27 @@ tf_msg_set_if_tbl_entry(struct tf *tfp,
 	}
 
 
-	flags = (params->dir == TF_DIR_TX ? TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX :
-		 TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX);
+	flags = (params->dir == TF_DIR_TX ?
+		HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX :
+		HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX);
 
 	/* Populate the request */
 	req.fw_session_id =
 		tfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);
 	req.flags = flags;
-	req.tf_if_tbl_type = params->hcapi_type;
-	req.idx = tfp_cpu_to_le_32(params->idx);
-	req.data_sz_in_bytes = tfp_cpu_to_le_32(params->data_sz_in_bytes);
+	req.type = params->hcapi_type;
+	req.index = tfp_cpu_to_le_32(params->idx);
+	req.size = tfp_cpu_to_le_32(params->data_sz_in_bytes);
 	tfp_memcpy(&req.data[0], params->data, params->data_sz_in_bytes);
 
-	MSG_PREP_NO_RESP(parms,
-			 TF_KONG_MB,
-			 HWRM_TF,
-			 HWRM_TFT_IF_TBL_SET,
-			 req);
+	parms.tf_type = HWRM_TF_IF_TBL_SET;
+	parms.req_data = (uint32_t *)&req;
+	parms.req_size = sizeof(req);
+	parms.resp_data = (uint32_t *)&resp;
+	parms.resp_size = sizeof(resp);
+	parms.mailbox = TF_KONG_MB;
 
-	rc = tfp_send_msg_tunneled(tfp, &parms);
+	rc = tfp_send_msg_direct(tfp, &parms);
 
 	if (rc != 0)
 		return rc;
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 15/25] net/bnxt: remove VLAN pop action for egress flows
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (13 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 14/25] net/bnxt: move IF tbl from tunneled to direct HWRM msg Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 16/25] net/bnxt: increase counter support from 8K to 16K Ajit Khaparde
                   ` (10 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Whitney platform does not support vlan pop action in the egress
direction, hence the vlan pop action is removed from the egress
action templates.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 42 +++++--------------
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |  3 +-
 2 files changed, 12 insertions(+), 33 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index 22142c137..de96afe8c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -1036,7 +1036,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET,
@@ -1434,21 +1434,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
-	.result_operand = {
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -2346,21 +2336,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
-	.result_operand = {
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 51758868a..4c1161acd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -218,8 +218,7 @@ enum bnxt_ulp_mapper_opc {
 	BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9,
 	BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10,
 	BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11,
-	BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12,
-	BNXT_ULP_MAPPER_OPC_LAST = 13
+	BNXT_ULP_MAPPER_OPC_LAST = 12
 };
 
 enum bnxt_ulp_mark_db_opcode {
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 16/25] net/bnxt: increase counter support from 8K to 16K
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (14 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 15/25] net/bnxt: remove VLAN pop action for egress flows Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 17/25] net/bnxt: fix to explicitly check and set for start cntr ID Ajit Khaparde
                   ` (9 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The number of internal stats counter is increased to 16k
in both egress and ingress direction.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 7650c7167..1e4aa8da4 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -91,7 +91,7 @@ ulp_ctx_session_open(struct bnxt *bp,
 
 	/* Table Types */
 	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
-	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 8192;
+	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 16384;
 	resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023;
 
 	/* ENCAP */
@@ -125,7 +125,7 @@ ulp_ctx_session_open(struct bnxt *bp,
 
 	/* Table Types */
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
-	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 8192;
+	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 16384;
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023;
 
 	/* ENCAP */
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 17/25] net/bnxt: fix to explicitly check and set for start cntr ID
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (15 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 16/25] net/bnxt: increase counter support from 8K to 16K Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 18/25] net/bnxt: enable support for VXLAN ipv6 encapsulation Ajit Khaparde
                   ` (8 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, Venkat Duvvuru

From: Somnath Kotur <somnath.kotur@broadcom.com>

Instead of relying on value of Flow counter ID to determine validity
have an explicit boolean flag for the same to check and set.

Fixes: 306c2d28e247 ("net/bnxt: support count action in flow query")
Fixes: 9cf9c8385df7 ("net/bnxt: add ULP flow counter manager")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 8 ++++----
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 1 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index df1921d54..5a0bf602a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -431,8 +431,7 @@ bool ulp_fc_mgr_start_idx_isset(struct bnxt_ulp_context *ctxt, enum tf_dir dir)
 
 	ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
 
-	/* Assuming start_idx of 0 is invalid */
-	return (ulp_fc_info->shadow_hw_tbl[dir].start_idx != 0);
+	return ulp_fc_info->shadow_hw_tbl[dir].start_idx_is_set;
 }
 
 /*
@@ -456,9 +455,10 @@ int32_t ulp_fc_mgr_start_idx_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
 	if (!ulp_fc_info)
 		return -EIO;
 
-	/* Assuming that 0 is an invalid counter ID ? */
-	if (ulp_fc_info->shadow_hw_tbl[dir].start_idx == 0)
+	if (!ulp_fc_info->shadow_hw_tbl[dir].start_idx_is_set) {
 		ulp_fc_info->shadow_hw_tbl[dir].start_idx = start_idx;
+		ulp_fc_info->shadow_hw_tbl[dir].start_idx_is_set = true;
+	}
 
 	return 0;
 }
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 9c317b023..0cb880d4b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -38,6 +38,7 @@ struct hw_fc_mem_info {
 	 */
 	void *mem_pa;
 	uint32_t start_idx;
+	bool start_idx_is_set;
 };
 
 struct bnxt_ulp_fc_info {
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 18/25] net/bnxt: enable support for VXLAN ipv6 encapsulation
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (16 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 17/25] net/bnxt: fix to explicitly check and set for start cntr ID Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 19/25] net/bnxt: enable support for nat action with tagged traffic Ajit Khaparde
                   ` (7 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Add code to support vxlan ipv6 tunnel encapsulation. The
ipv6 flow traffic class and flow label wild card match
are ignore to support ovs offload.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c            |   1 +
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      | 132 ++++++++++++++----
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h      |   5 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c |   2 +-
 drivers/net/bnxt/tf_ulp/ulp_utils.c           |  43 ++++--
 drivers/net/bnxt/tf_ulp/ulp_utils.h           |   7 +-
 6 files changed, 147 insertions(+), 43 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 1e4aa8da4..eae8884bd 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -149,6 +149,7 @@ ulp_ctx_session_open(struct bnxt *bp,
 
 	/* SP */
 	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488;
+	resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 511;
 
 	rc = tf_open_session(&bp->tfp, &params);
 	if (rc) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index ed95cf60f..03d759851 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -78,6 +78,16 @@ ulp_rte_prsr_mask_copy(struct ulp_rte_parser_params *params,
 	*idx = *idx + 1;
 }
 
+/* Utility function to ignore field masks items */
+static void
+ulp_rte_prsr_mask_ignore(struct ulp_rte_parser_params *params __rte_unused,
+			 uint32_t *idx,
+			 const void *buffer __rte_unused,
+			 uint32_t size __rte_unused)
+{
+	*idx = *idx + 1;
+}
+
 /*
  * Function to handle the parsing of RTE Flows and placing
  * the RTE flow items into the ulp structures.
@@ -741,7 +751,8 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
 		 * wild card match and it is not supported. This is a work
 		 * around and shall be addressed in the future.
 		 */
-		idx += 1;
+		ulp_rte_prsr_mask_ignore(params, &idx, &priority,
+					 sizeof(priority));
 
 		ulp_rte_prsr_mask_copy(params, &idx, &vlan_tag,
 				       sizeof(vlan_tag));
@@ -920,7 +931,10 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
 		 * match and it is not supported. This is a work around and
 		 * shall be addressed in the future.
 		 */
-		idx += 1;
+		ulp_rte_prsr_mask_ignore(params, &idx,
+					 &ipv4_mask->hdr.type_of_service,
+					 sizeof(ipv4_mask->hdr.type_of_service)
+					 );
 
 		ulp_rte_prsr_mask_copy(params, &idx,
 				       &ipv4_mask->hdr.total_length,
@@ -1041,17 +1055,17 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
 		ulp_rte_prsr_mask_copy(params, &idx,
 				       &vtcf_mask,
 				       size);
-
+		/*
+		 * The TC and flow lable field are ignored since OVS is seting
+		 * it for match and it is not supported.
+		 * This is a work around and
+		 * shall be addressed in the future.
+		 */
 		vtcf_mask = BNXT_ULP_GET_IPV6_TC(ipv6_mask->hdr.vtc_flow);
-		ulp_rte_prsr_mask_copy(params, &idx,
-				       &vtcf_mask,
-				       size);
-
+		ulp_rte_prsr_mask_ignore(params, &idx, &vtcf_mask, size);
 		vtcf_mask =
 			BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_mask->hdr.vtc_flow);
-		ulp_rte_prsr_mask_copy(params, &idx,
-				       &vtcf_mask,
-				       size);
+		ulp_rte_prsr_mask_ignore(params, &idx, &vtcf_mask, size);
 
 		ulp_rte_prsr_mask_copy(params, &idx,
 				       &ipv6_mask->hdr.payload_len,
@@ -1414,8 +1428,12 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
 	/* IP header per byte - ver/hlen, TOS, ID, ID, FRAG, FRAG, TTL, PROTO */
 	const uint8_t def_ipv4_hdr[] = {0x45, 0x00, 0x00, 0x01, 0x00,
 				    0x00, 0x40, 0x11};
+	/* IPv6 header per byte - vtc-flow,flow,zero,nexthdr-ttl */
+	const uint8_t def_ipv6_hdr[] = {0x60, 0x00, 0x00, 0x01, 0x00,
+				0x00, 0x11, 0xf6};
 	struct ulp_rte_act_bitmap *act = &params->act_bitmap;
 	struct ulp_rte_act_prop *ap = &params->act_prop;
+	const uint8_t *tmp_buff;
 
 	vxlan_encap = action_item->conf;
 	if (!vxlan_encap) {
@@ -1441,12 +1459,14 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
 	buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC];
 	ulp_encap_buffer_copy(buff,
 			      eth_spec->dst.addr_bytes,
-			      BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC);
+			      BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
+			      ULP_BUFFER_ALIGN_8_BYTE);
 
 	buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC];
 	ulp_encap_buffer_copy(buff,
 			      eth_spec->src.addr_bytes,
-			      BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC);
+			      BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
+			      ULP_BUFFER_ALIGN_8_BYTE);
 
 	/* Goto the next item */
 	if (!ulp_rte_item_skip_void(&item, 1))
@@ -1458,7 +1478,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
 		buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG];
 		ulp_encap_buffer_copy(buff,
 				      item->spec,
-				      sizeof(struct rte_flow_item_vlan));
+				      sizeof(struct rte_flow_item_vlan),
+				      ULP_BUFFER_ALIGN_8_BYTE);
 
 		if (!ulp_rte_item_skip_void(&item, 1))
 			return BNXT_TF_RC_ERROR;
@@ -1499,32 +1520,41 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
 			ulp_encap_buffer_copy(buff,
 					      def_ipv4_hdr,
 					      BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
-					      BNXT_ULP_ENCAP_IPV4_ID_PROTO);
+					      BNXT_ULP_ENCAP_IPV4_ID_PROTO,
+					      ULP_BUFFER_ALIGN_8_BYTE);
 		} else {
-			const uint8_t *tmp_buff;
-
+			/* Total length being ignored in the ip hdr. */
 			buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
 			tmp_buff = (const uint8_t *)&ipv4_spec->hdr.packet_id;
 			ulp_encap_buffer_copy(buff,
 					      tmp_buff,
-					      BNXT_ULP_ENCAP_IPV4_ID_PROTO);
+					      BNXT_ULP_ENCAP_IPV4_ID_PROTO,
+					      ULP_BUFFER_ALIGN_8_BYTE);
 			buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
 			     BNXT_ULP_ENCAP_IPV4_ID_PROTO];
 			ulp_encap_buffer_copy(buff,
 					      &ipv4_spec->hdr.version_ihl,
-					      BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS);
+					      BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS,
+					      ULP_BUFFER_ALIGN_8_BYTE);
 		}
+
+		/* Update the dst ip address in ip encap buffer */
 		buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
 		    BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
 		    BNXT_ULP_ENCAP_IPV4_ID_PROTO];
 		ulp_encap_buffer_copy(buff,
 				      (const uint8_t *)&ipv4_spec->hdr.dst_addr,
-				      BNXT_ULP_ENCAP_IPV4_DEST_IP);
+				      sizeof(ipv4_spec->hdr.dst_addr),
+				      ULP_BUFFER_ALIGN_8_BYTE);
 
-		buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC];
+		/* Update the src ip address */
+		buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC +
+			BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC -
+			sizeof(ipv4_spec->hdr.src_addr)];
 		ulp_encap_buffer_copy(buff,
 				      (const uint8_t *)&ipv4_spec->hdr.src_addr,
-				      BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC);
+				      sizeof(ipv4_spec->hdr.src_addr),
+				      ULP_BUFFER_ALIGN_8_BYTE);
 
 		/* Update the ip size details */
 		ip_size = tfp_cpu_to_be_32(ip_size);
@@ -1546,9 +1576,46 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
 		ipv6_spec = item->spec;
 		ip_size = BNXT_ULP_ENCAP_IPV6_SIZE;
 
-		/* copy the ipv4 details */
-		memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP],
-		       ipv6_spec, BNXT_ULP_ENCAP_IPV6_SIZE);
+		/* copy the ipv6 details */
+		tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
+		if (ulp_buffer_is_empty(tmp_buff,
+					BNXT_ULP_ENCAP_IPV6_VTC_FLOW)) {
+			buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
+			ulp_encap_buffer_copy(buff,
+					      def_ipv6_hdr,
+					      sizeof(def_ipv6_hdr),
+					      ULP_BUFFER_ALIGN_8_BYTE);
+		} else {
+			/* The payload length being ignored in the ip hdr. */
+			buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
+			tmp_buff = (const uint8_t *)&ipv6_spec->hdr.proto;
+			ulp_encap_buffer_copy(buff,
+					      tmp_buff,
+					      BNXT_ULP_ENCAP_IPV6_PROTO_TTL,
+					      ULP_BUFFER_ALIGN_8_BYTE);
+			buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
+				BNXT_ULP_ENCAP_IPV6_PROTO_TTL +
+				BNXT_ULP_ENCAP_IPV6_DO];
+			tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
+			ulp_encap_buffer_copy(buff,
+					      tmp_buff,
+					      BNXT_ULP_ENCAP_IPV6_VTC_FLOW,
+					      ULP_BUFFER_ALIGN_8_BYTE);
+		}
+		/* Update the dst ip address in ip encap buffer */
+		buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
+			sizeof(def_ipv6_hdr)];
+		ulp_encap_buffer_copy(buff,
+				      (const uint8_t *)ipv6_spec->hdr.dst_addr,
+				      sizeof(ipv6_spec->hdr.dst_addr),
+				      ULP_BUFFER_ALIGN_8_BYTE);
+
+		/* Update the src ip address */
+		buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC];
+		ulp_encap_buffer_copy(buff,
+				      (const uint8_t *)ipv6_spec->hdr.src_addr,
+				      sizeof(ipv6_spec->hdr.src_addr),
+				      ULP_BUFFER_ALIGN_16_BYTE);
 
 		/* Update the ip size details */
 		ip_size = tfp_cpu_to_be_32(ip_size);
@@ -1578,7 +1645,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
 	}
 	/* copy the udp details */
 	ulp_encap_buffer_copy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP],
-			      item->spec, BNXT_ULP_ENCAP_UDP_SIZE);
+			      item->spec, BNXT_ULP_ENCAP_UDP_SIZE,
+			      ULP_BUFFER_ALIGN_8_BYTE);
 
 	if (!ulp_rte_item_skip_void(&item, 1))
 		return BNXT_TF_RC_ERROR;
@@ -1592,9 +1660,17 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
 	/* copy the vxlan details */
 	memcpy(&vxlan_spec, item->spec, vxlan_size);
 	vxlan_spec.flags = 0x08;
-	ulp_encap_buffer_copy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN],
-			      (const uint8_t *)&vxlan_spec,
-			      vxlan_size);
+	buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN];
+	if (ip_type == rte_cpu_to_be_32(BNXT_ULP_ETH_IPV4)) {
+		ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
+				      vxlan_size, ULP_BUFFER_ALIGN_8_BYTE);
+	} else {
+		ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
+				      vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
+		ulp_encap_buffer_copy(buff + (vxlan_size / 2),
+				      (const uint8_t *)&vxlan_spec.vni,
+				      vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
+	}
 	vxlan_size = tfp_cpu_to_be_32(vxlan_size);
 	memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ],
 	       &vxlan_size, sizeof(uint32_t));
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 7b6b57e0e..41f3df998 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -17,7 +17,10 @@
 #define BNXT_ULP_ENCAP_IPV4_ID_PROTO		6
 #define BNXT_ULP_ENCAP_IPV4_DEST_IP		4
 #define BNXT_ULP_ENCAP_IPV4_SIZE		12
-#define BNXT_ULP_ENCAP_IPV6_SIZE		8
+#define BNXT_ULP_ENCAP_IPV6_VTC_FLOW		4
+#define BNXT_ULP_ENCAP_IPV6_PROTO_TTL		2
+#define BNXT_ULP_ENCAP_IPV6_DO			2
+#define BNXT_ULP_ENCAP_IPV6_SIZE		24
 #define BNXT_ULP_ENCAP_UDP_SIZE			4
 #define BNXT_ULP_INVALID_SVIF_VAL		-1U
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index de96afe8c..cab3445a2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -1036,7 +1036,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index a923da86e..24474e2e2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -546,8 +546,8 @@ ulp_blob_encap_swap_idx_set(struct ulp_blob *blob)
 void
 ulp_blob_perform_encap_swap(struct ulp_blob *blob)
 {
-	uint32_t		i, idx = 0, end_idx = 0;
-	uint8_t		temp_val_1, temp_val_2;
+	uint32_t i, idx = 0, end_idx = 0, roundoff;
+	uint8_t temp_val_1, temp_val_2;
 
 	/* validate the arguments */
 	if (!blob) {
@@ -556,7 +556,11 @@ ulp_blob_perform_encap_swap(struct ulp_blob *blob)
 	}
 	idx = ULP_BITS_2_BYTE_NR(blob->encap_swap_idx);
 	end_idx = ULP_BITS_2_BYTE(blob->write_idx);
-
+	roundoff = ULP_BYTE_2_BITS(ULP_BITS_2_BYTE(end_idx));
+	if (roundoff > end_idx) {
+		blob->write_idx += ULP_BYTE_2_BITS(roundoff - end_idx);
+		end_idx = roundoff;
+	}
 	while (idx <= end_idx) {
 		for (i = 0; i < 4; i = i + 2) {
 			temp_val_1 = blob->data[idx + i];
@@ -631,20 +635,35 @@ ulp_operand_read(uint8_t *operand,
  * dst [out] The destination buffer
  * src [in] The source buffer dst
  * size[in] size of the buffer.
+ * align[in] The alignment is either 8 or 16.
  */
 void
 ulp_encap_buffer_copy(uint8_t *dst,
 		      const uint8_t *src,
-		      uint16_t size)
+		      uint16_t size,
+		      uint16_t align)
 {
-	uint16_t	idx = 0;
-
-	/* copy 2 bytes at a time. Write MSB to LSB */
-	while ((idx + sizeof(uint16_t)) <= size) {
-		memcpy(&dst[idx], &src[size - idx - sizeof(uint16_t)],
-		       sizeof(uint16_t));
-		idx += sizeof(uint16_t);
-	}
+	uint16_t	idx, tmp_size = 0;
+
+	do {
+		dst += tmp_size;
+		src += tmp_size;
+		idx = 0;
+		if (size > align) {
+			tmp_size = align;
+			size -= align;
+		} else {
+			tmp_size = size;
+			size = 0;
+		}
+		/* copy 2 bytes at a time. Write MSB to LSB */
+		while ((idx + sizeof(uint16_t)) <= tmp_size) {
+			memcpy(&dst[idx],
+			       &src[tmp_size - idx - sizeof(uint16_t)],
+			       sizeof(uint16_t));
+			idx += sizeof(uint16_t);
+		}
+	} while (size);
 }
 
 /*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 22dfb1732..c054a77a9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -9,6 +9,9 @@
 #include "bnxt.h"
 #include "ulp_template_db_enum.h"
 
+#define ULP_BUFFER_ALIGN_8_BYTE		8
+#define ULP_BUFFER_ALIGN_16_BYTE	16
+
 /*
  * Macros for bitmap sets and gets
  * These macros can be used if the val are power of 2.
@@ -315,11 +318,13 @@ ulp_operand_read(uint8_t *operand,
  * dst [out] The destination buffer
  * src [in] The source buffer dst
  * size[in] size of the buffer.
+ * align[in] The alignment is either 8 or 16.
  */
 void
 ulp_encap_buffer_copy(uint8_t *dst,
 		      const uint8_t *src,
-		      uint16_t size);
+		      uint16_t size,
+		      uint16_t align);
 
 /*
  * Check the buffer is empty
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 19/25] net/bnxt: enable support for nat action with tagged traffic
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (17 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 18/25] net/bnxt: enable support for VXLAN ipv6 encapsulation Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 20/25] net/bnxt: fix out of bound access in action bit handling Ajit Khaparde
                   ` (6 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Added support for performing l3 or l4 rewrite for vlan tagged
flows. The outer most dmac, smac and vlan are used to overwrite
when nat operations are performed.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c            | 14 ++-----
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h            |  6 +++
 drivers/net/bnxt/tf_ulp/ulp_mapper.c          | 21 ++++++++++
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 40 ++++++++++++++-----
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |  3 +-
 5 files changed, 63 insertions(+), 21 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index eae8884bd..364853a6e 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -721,15 +721,11 @@ bnxt_ulp_deinit(struct bnxt *bp,
 	/* Disable NAT feature */
 	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP,
 					 TF_TUNNEL_ENCAP_NAT,
-					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
-					 0);
+					 BNXT_ULP_NAT_OUTER_MOST_FLAGS, 0);
 
 	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP,
 					 TF_TUNNEL_ENCAP_NAT,
-					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
-					 0);
+					 BNXT_ULP_NAT_OUTER_MOST_FLAGS, 0);
 
 	/* Delete the ulp context and tf session and free the ulp context */
 	ulp_ctx_deinit(bp, session);
@@ -808,8 +804,7 @@ bnxt_ulp_init(struct bnxt *bp,
 	 */
 	rc = bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP,
 					TF_TUNNEL_ENCAP_NAT,
-					(BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					BNXT_ULP_NAT_INNER_L2_HEADER_DMAC), 1);
+					BNXT_ULP_NAT_OUTER_MOST_FLAGS, 1);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to set rx global configuration\n");
 		goto jump_to_error;
@@ -817,8 +812,7 @@ bnxt_ulp_init(struct bnxt *bp,
 
 	rc = bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP,
 					TF_TUNNEL_ENCAP_NAT,
-					(BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					BNXT_ULP_NAT_INNER_L2_HEADER_DMAC), 1);
+					BNXT_ULP_NAT_OUTER_MOST_FLAGS, 1);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed to set tx global configuration\n");
 		goto jump_to_error;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 5882c545c..ed978734a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -16,7 +16,13 @@
 
 /* NAT defines to reuse existing inner L2 SMAC and DMAC */
 #define BNXT_ULP_NAT_INNER_L2_HEADER_SMAC	0x2000
+#define BNXT_ULP_NAT_OUTER_MOST_L2_HDR_SMAC	0x6000
+#define BNXT_ULP_NAT_OUTER_MOST_L2_VLAN_TAGS	0xc00
 #define BNXT_ULP_NAT_INNER_L2_HEADER_DMAC	0x100
+#define BNXT_ULP_NAT_OUTER_MOST_L2_HDR_DMAC	0x300
+#define BNXT_ULP_NAT_OUTER_MOST_FLAGS (BNXT_ULP_NAT_OUTER_MOST_L2_HDR_SMAC |\
+					BNXT_ULP_NAT_OUTER_MOST_L2_VLAN_TAGS |\
+					BNXT_ULP_NAT_OUTER_MOST_L2_HDR_DMAC)
 
 /* defines for the ulp_flags */
 #define BNXT_ULP_VF_REP_ENABLED		0x1
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 6ac4b0f83..15682673d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -783,6 +783,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
 	uint32_t val_size = 0, field_size = 0;
 	uint64_t act_bit;
 	uint8_t act_val;
+	uint64_t hdr_bit;
 
 	switch (fld->result_opcode) {
 	case BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT:
@@ -1033,6 +1034,26 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
 			return -EINVAL;
 		}
 		break;
+	case BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST:
+		if (!ulp_operand_read(fld->result_operand,
+				      (uint8_t *)&hdr_bit, sizeof(uint64_t))) {
+			BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
+			return -EINVAL;
+		}
+		hdr_bit = tfp_be_to_cpu_64(hdr_bit);
+		if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) {
+			/* Header bit is set so consider operand_true */
+			val = fld->result_operand_true;
+		} else {
+			/* Header bit is not set, use the operand false */
+			val = fld->result_operand_false;
+		}
+		if (!ulp_blob_push(blob, val, fld->field_bit_size)) {
+			BNXT_TF_DBG(ERR, "%s failed to add field\n",
+				    name);
+			return -EINVAL;
+		}
+		break;
 	default:
 		BNXT_TF_DBG(ERR, "invalid result mapper opcode 0x%x\n",
 			    fld->result_opcode);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index cab3445a2..22142c137 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -1434,11 +1434,21 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {
-		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
+	.result_operand = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -2336,11 +2346,21 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {
-		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
+	.result_operand = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 4c1161acd..51758868a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -218,7 +218,8 @@ enum bnxt_ulp_mapper_opc {
 	BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9,
 	BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10,
 	BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11,
-	BNXT_ULP_MAPPER_OPC_LAST = 12
+	BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12,
+	BNXT_ULP_MAPPER_OPC_LAST = 13
 };
 
 enum bnxt_ulp_mark_db_opcode {
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 20/25] net/bnxt: fix out of bound access in action bit handling
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (18 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 19/25] net/bnxt: enable support for nat action with tagged traffic Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 21/25] net/bnxt: provide switch info while VF-Reps are configured Ajit Khaparde
                   ` (5 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Shahaji Bhosle, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The act_val is changed to be array to resolve out of bound access issue

Fixes: 52799debdf1c ("net/bnxt: support action bitmap opcode")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_mapper.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 15682673d..732141166 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -782,7 +782,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
 	uint64_t regval;
 	uint32_t val_size = 0, field_size = 0;
 	uint64_t act_bit;
-	uint8_t act_val;
+	uint8_t act_val[16];
 	uint64_t hdr_bit;
 
 	switch (fld->result_opcode) {
@@ -824,19 +824,18 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
 			return -EINVAL;
 		}
 		act_bit = tfp_be_to_cpu_64(act_bit);
+		memset(act_val, 0, sizeof(act_val));
 		if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit))
-			act_val = 1;
-		else
-			act_val = 0;
+			act_val[0] = 1;
 		if (fld->field_bit_size > ULP_BYTE_2_BITS(sizeof(act_val))) {
 			BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name);
 			return -EINVAL;
 		}
-		if (!ulp_blob_push(blob, &act_val, fld->field_bit_size)) {
+		if (!ulp_blob_push(blob, act_val, fld->field_bit_size)) {
 			BNXT_TF_DBG(ERR, "%s push field failed\n", name);
 			return -EINVAL;
 		}
-		val = &act_val;
+		val = act_val;
 		break;
 	case BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ:
 		if (!ulp_operand_read(fld->result_operand,
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 21/25] net/bnxt: provide switch info while VF-Reps are configured
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (19 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 20/25] net/bnxt: fix out of bound access in action bit handling Ajit Khaparde
@ 2020-09-11  1:55 ` Ajit Khaparde
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 22/25] net/bnxt: fix bugs in representor data path Ajit Khaparde
                   ` (4 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:55 UTC (permalink / raw)
  To: dev; +Cc: Sriharsha Basavapatna

From: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>

Some applications need switch_info of the device to be returned as a part
of eth_dev_info_get(). The offload logic in such applications could use
this info.

Fixes: 322bd6e70272 ("net/bnxt: add port representor infrastructure")

Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt_ethdev.c | 8 ++++++++
 drivers/net/bnxt/bnxt_reps.c   | 5 +++++
 drivers/net/bnxt/bnxt_reps.h   | 7 +++++++
 3 files changed, 20 insertions(+)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 043637db6..e77e45486 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -908,6 +908,14 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 	dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 	dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 
+	if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
+		dev_info->switch_info.name = eth_dev->device->name;
+		dev_info->switch_info.domain_id = bp->switch_domain_id;
+		dev_info->switch_info.port_id =
+				BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
+				    BNXT_SWITCH_PORT_ID_TRUSTED_VF;
+	}
+
 	/* *INDENT-ON* */
 
 	/*
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 6fa867a8a..9d5fa7394 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -501,6 +501,11 @@ int bnxt_vf_rep_dev_info_get_op(struct rte_eth_dev *eth_dev,
 	dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 	dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 
+	dev_info->switch_info.name = eth_dev->device->name;
+	dev_info->switch_info.domain_id = rep_bp->switch_domain_id;
+	dev_info->switch_info.port_id =
+			rep_bp->vf_id & BNXT_SWITCH_PORT_ID_VF_MASK;
+
 	return 0;
 }
 
diff --git a/drivers/net/bnxt/bnxt_reps.h b/drivers/net/bnxt/bnxt_reps.h
index d877b0823..3239e03fc 100644
--- a/drivers/net/bnxt/bnxt_reps.h
+++ b/drivers/net/bnxt/bnxt_reps.h
@@ -12,6 +12,13 @@
 #define BNXT_MAX_CFA_CODE               65536
 #define BNXT_VF_IDX_INVALID             0xffff
 
+/* Switchdev Port ID Mapping (Per switch domain id).
+ * Lower 15 bits map the VFs (VF_ID). Upper bit maps the PF.
+ */
+#define	BNXT_SWITCH_PORT_ID_PF		0x8000
+#define	BNXT_SWITCH_PORT_ID_TRUSTED_VF	0x0
+#define BNXT_SWITCH_PORT_ID_VF_MASK	0x7FFF
+
 uint16_t
 bnxt_vfr_recv(uint16_t port_id, uint16_t queue_id, struct rte_mbuf *mbuf);
 int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params);
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 22/25] net/bnxt: fix bugs in representor data path
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (20 preceding siblings ...)
  2020-09-11  1:55 ` [dpdk-dev] [PATCH 21/25] net/bnxt: provide switch info while VF-Reps are configured Ajit Khaparde
@ 2020-09-11  1:56 ` Ajit Khaparde
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 23/25] net/bnxt: add support for locks in flow database Ajit Khaparde
                   ` (3 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:56 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, Sriharsha Basavapatna, Venkat Duvvuru

From: Somnath Kotur <somnath.kotur@broadcom.com>

1.Representor Rx ring producer index was not getting reset in
the ring full case. Fix it by incrementing only in
success case.
2.Instead of calling the mbuf specific routine to free the mbuf when
representor ring is full rte_free was being called leading to
'invalid memory' errors being logged.
3. Do not account the pkt meant for the representor in the parent
Rx ring's array that is returned to the application.

Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
 drivers/net/bnxt/bnxt_reps.c |  7 ++++---
 drivers/net/bnxt/bnxt_rxr.c  | 27 +++++++++++++--------------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 9d5fa7394..fd111bec5 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -55,16 +55,17 @@ bnxt_vfr_recv(uint16_t port_id, uint16_t queue_id, struct rte_mbuf *mbuf)
 	mask = rep_rxr->rx_ring_struct->ring_mask;
 
 	/* Put this mbuf on the RxQ of the Representor */
-	prod_rx_buf =
-		&rep_rxr->rx_buf_ring[rep_rxr->rx_prod++ & mask];
+	prod_rx_buf = &rep_rxr->rx_buf_ring[rep_rxr->rx_prod & mask];
 	if (!prod_rx_buf->mbuf) {
 		prod_rx_buf->mbuf = mbuf;
 		vfr_bp->rx_bytes[que] += mbuf->pkt_len;
 		vfr_bp->rx_pkts[que]++;
+		rep_rxr->rx_prod++;
 	} else {
+		/* Representor Rx ring full, drop pkt */
 		vfr_bp->rx_drop_bytes[que] += mbuf->pkt_len;
 		vfr_bp->rx_drop_pkts[que]++;
-		rte_pktmbuf_free(mbuf); /* Representor Rx ring full, drop pkt */
+		rte_pktmbuf_free(mbuf);
 	}
 
 	return 0;
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index b08689814..5bfe62a2a 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -733,6 +733,19 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
 		goto rx;
 	}
 	rxr->rx_prod = prod;
+
+	if (BNXT_TRUFLOW_EN(bp) && (BNXT_VF_IS_TRUSTED(bp) || BNXT_PF(bp)) &&
+	    vfr_flag) {
+		bnxt_vfr_recv(mark_id, rxq->queue_id, mbuf);
+		/* Now return an error so that nb_rx_pkts is not
+		 * incremented.
+		 * This packet was meant to be given to the representor.
+		 * So no need to account the packet and give it to
+		 * parent Rx burst function.
+		 */
+		rc = -ENODEV;
+		goto next_rx;
+	}
 	/*
 	 * All MBUFs are allocated with the same size under DPDK,
 	 * no optimization for rx_copy_thresh
@@ -740,20 +753,6 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
 rx:
 	*rx_pkt = mbuf;
 
-	if (BNXT_TRUFLOW_EN(bp) &&
-	    (BNXT_VF_IS_TRUSTED(bp) || BNXT_PF(bp)) &&
-	    vfr_flag) {
-		if (!bnxt_vfr_recv(mark_id, rxq->queue_id, mbuf)) {
-			/* Now return an error so that nb_rx_pkts is not
-			 * incremented.
-			 * This packet was meant to be given to the representor.
-			 * So no need to account the packet and give it to
-			 * parent Rx burst function.
-			 */
-			rc = -ENODEV;
-		}
-	}
-
 next_rx:
 
 	*raw_cons = tmp_raw_cons;
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 23/25] net/bnxt: add support for locks in flow database
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (21 preceding siblings ...)
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 22/25] net/bnxt: fix bugs in representor data path Ajit Khaparde
@ 2020-09-11  1:56 ` Ajit Khaparde
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 24/25] net/bnxt: fix to check for vnic ptr in bnxt shutdown path Ajit Khaparde
                   ` (2 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:56 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Shahaji Bhosle

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Added support for mutex protection for the flow database to prevent
simultaneous access to flow database and protect flow creation and
deletion.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c    | 33 +++++++++++++++++++++++++++
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h    |  7 ++++++
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 13 ++++++++++-
 drivers/net/bnxt/tf_ulp/ulp_mapper.c  | 20 +++++++++++++++-
 4 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 364853a6e..e8927f629 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -727,6 +727,9 @@ bnxt_ulp_deinit(struct bnxt *bp,
 					 TF_TUNNEL_ENCAP_NAT,
 					 BNXT_ULP_NAT_OUTER_MOST_FLAGS, 0);
 
+	/* free the flow db lock */
+	pthread_mutex_destroy(&bp->ulp_ctx->cfg_data->flow_db_lock);
+
 	/* Delete the ulp context and tf session and free the ulp context */
 	ulp_ctx_deinit(bp, session);
 	BNXT_TF_DBG(DEBUG, "ulp ctx has been deinitialized\n");
@@ -750,6 +753,12 @@ bnxt_ulp_init(struct bnxt *bp,
 		goto jump_to_error;
 	}
 
+	rc = pthread_mutex_init(&bp->ulp_ctx->cfg_data->flow_db_lock, NULL);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Unable to initialize flow db lock\n");
+		goto jump_to_error;
+	}
+
 	/* Initialize ulp dparms with values devargs passed */
 	rc = ulp_dparms_init(bp, bp->ulp_ctx);
 	if (rc) {
@@ -1235,3 +1244,27 @@ bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(struct bnxt_ulp_context *ulp_ctx,
 
 	return &ulp_ctx->cfg_data->vfr_rule_info[port_id];
 }
+
+/* Function to acquire the flow database lock from the ulp context. */
+int32_t
+bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context	*ulp_ctx)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
+		return -1;
+
+	if (pthread_mutex_lock(&ulp_ctx->cfg_data->flow_db_lock)) {
+		BNXT_TF_DBG(ERR, "unable to acquire fdb lock\n");
+		return -1;
+	}
+	return 0;
+}
+
+/* Function to release the flow database lock from the ulp context. */
+void
+bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context	*ulp_ctx)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
+		return;
+
+	pthread_mutex_unlock(&ulp_ctx->cfg_data->flow_db_lock);
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index ed978734a..36405ae1e 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -47,6 +47,7 @@ struct bnxt_ulp_data {
 	uint32_t			dev_id; /* Hardware device id */
 	uint32_t			ref_cnt;
 	struct bnxt_ulp_flow_db		*flow_db;
+	pthread_mutex_t			flow_db_lock;
 	void				*mapper_data;
 	struct bnxt_ulp_port_db		*port_db;
 	struct bnxt_ulp_fc_info		*fc_info;
@@ -196,4 +197,10 @@ struct bnxt_ulp_vfr_rule_info*
 bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(struct bnxt_ulp_context *ulp_ctx,
 				     uint32_t port_id);
 
+int32_t
+bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context	*ulp_ctx);
+
+void
+bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context	*ulp_ctx);
+
 #endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index cbdf5df68..9a2d3758d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -793,10 +793,17 @@ int32_t	ulp_flow_db_flush_flows(struct bnxt_ulp_context *ulp_ctx,
 		BNXT_TF_DBG(ERR, "Flow database not found\n");
 		return -EINVAL;
 	}
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
+
 	flow_tbl = &flow_db->flow_tbl[idx];
 	while (!ulp_flow_db_next_entry_get(flow_tbl, &fid))
 		ulp_mapper_resources_free(ulp_ctx, fid, idx);
 
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
 	return 0;
 }
 
@@ -826,13 +833,17 @@ ulp_flow_db_function_flow_flush(struct bnxt_ulp_context *ulp_ctx,
 		BNXT_TF_DBG(ERR, "Flow database not found\n");
 		return -EINVAL;
 	}
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
 	flow_tbl = &flow_db->flow_tbl[BNXT_ULP_REGULAR_FLOW_TABLE];
 	while (!ulp_flow_db_next_entry_get(flow_tbl, &flow_id)) {
 		if (flow_db->func_id_tbl[flow_id] == func_id)
 			ulp_mapper_resources_free(ulp_ctx, flow_id,
 						  BNXT_ULP_REGULAR_FLOW_TABLE);
 	}
-
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 	return 0;
 }
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 732141166..85ae3b5c4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2668,12 +2668,21 @@ int32_t
 ulp_mapper_flow_destroy(struct bnxt_ulp_context	*ulp_ctx, uint32_t fid,
 			enum bnxt_ulp_flow_db_tables flow_tbl_type)
 {
+	int32_t rc;
+
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "Invalid parms, unable to free flow\n");
 		return -EINVAL;
 	}
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
+
+	rc = ulp_mapper_resources_free(ulp_ctx, fid, flow_tbl_type);
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+	return rc;
 
-	return ulp_mapper_resources_free(ulp_ctx, fid, flow_tbl_type);
 }
 
 /* Function to handle the default global templates that are allocated during
@@ -2838,6 +2847,12 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 		return -EINVAL;
 	}
 
+	/* Protect flow creation */
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
+
 	/* Allocate a Flow ID for attaching all resources for the flow to.
 	 * Once allocated, all errors have to walk the list of resources and
 	 * free each of them.
@@ -2848,6 +2863,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 				   &parms.fid);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
+		bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 		return rc;
 	}
 
@@ -2871,10 +2887,12 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 	}
 
 	*flowid = parms.fid;
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
 	return rc;
 
 flow_error:
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 	/* Free all resources that were allocated during flow creation */
 	trc = ulp_mapper_flow_destroy(ulp_ctx, parms.fid,
 				      BNXT_ULP_REGULAR_FLOW_TABLE);
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 24/25] net/bnxt: fix to check for vnic ptr in bnxt shutdown path
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (22 preceding siblings ...)
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 23/25] net/bnxt: add support for locks in flow database Ajit Khaparde
@ 2020-09-11  1:56 ` Ajit Khaparde
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 25/25] net/bnxt: fix to have a separate mutex for FW health check Ajit Khaparde
  2020-09-16  4:28 ` [dpdk-dev] [PATCH v2 00/25] patchset for bnxt Ajit Khaparde
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:56 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, stable

From: Somnath Kotur <somnath.kotur@broadcom.com>

Add a couple of NULL ptr checks in bnxt_free_all_filters()
and bnxt_free_vnics() respectively to guard against certain error
injection/recovery scenarios where it was found that the application
was crashing with the bp->vnic_info ptr being NULL.

Fixes: 51fafb89a9a0 ("net/bnxt: get rid of ff pools and use VNIC info array")
Cc: stable@dpdk.org

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt_filter.c | 14 +++++++++-----
 drivers/net/bnxt/bnxt_vnic.c   |  3 +++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_filter.c b/drivers/net/bnxt/bnxt_filter.c
index d822ff607..6d8598324 100644
--- a/drivers/net/bnxt/bnxt_filter.c
+++ b/drivers/net/bnxt/bnxt_filter.c
@@ -81,6 +81,15 @@ void bnxt_free_all_filters(struct bnxt *bp)
 	struct bnxt_filter_info *filter, *temp_filter;
 	unsigned int i;
 
+	for (i = 0; i < bp->pf->max_vfs; i++) {
+		STAILQ_FOREACH(filter, &bp->pf->vf_info[i].filter, next) {
+			bnxt_hwrm_clear_l2_filter(bp, filter);
+		}
+	}
+
+	if (bp->vnic_info == NULL)
+		return;
+
 	for (i = 0; i < bp->nr_vnics; i++) {
 		vnic = &bp->vnic_info[i];
 		filter = STAILQ_FIRST(&vnic->filter);
@@ -95,11 +104,6 @@ void bnxt_free_all_filters(struct bnxt *bp)
 		STAILQ_INIT(&vnic->filter);
 	}
 
-	for (i = 0; i < bp->pf->max_vfs; i++) {
-		STAILQ_FOREACH(filter, &bp->pf->vf_info[i].filter, next) {
-			bnxt_hwrm_clear_l2_filter(bp, filter);
-		}
-	}
 }
 
 void bnxt_free_filter_mem(struct bnxt *bp)
diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c
index 326c0d1b6..9a135ae88 100644
--- a/drivers/net/bnxt/bnxt_vnic.c
+++ b/drivers/net/bnxt/bnxt_vnic.c
@@ -78,6 +78,9 @@ void bnxt_free_all_vnics(struct bnxt *bp)
 	struct bnxt_vnic_info *vnic;
 	unsigned int i;
 
+	if (bp->vnic_info == NULL)
+		return;
+
 	for (i = 0; i < bp->max_vnics; i++) {
 		vnic = &bp->vnic_info[i];
 		STAILQ_INSERT_TAIL(&bp->free_vnic_list, vnic, next);
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH 25/25] net/bnxt: fix to have a separate mutex for FW health check
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (23 preceding siblings ...)
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 24/25] net/bnxt: fix to check for vnic ptr in bnxt shutdown path Ajit Khaparde
@ 2020-09-11  1:56 ` Ajit Khaparde
  2020-09-16  4:28 ` [dpdk-dev] [PATCH v2 00/25] patchset for bnxt Ajit Khaparde
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-11  1:56 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, stable, Sriharsha Basavapatna, Kalesh Anakkur Purayil

From: Somnath Kotur <somnath.kotur@broadcom.com>

def_cp_lock was added to sync race between dev_configure and
int_handler. It should not be used to synchronize scheduling of FW
health check between dev_start and async event handler as well,
use a separate mutex for the same.

Fixes: a73b8e939f10 ("net/bnxt: fix race between start and interrupt handler")
Cc: stable@dpdk.org

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
Reviewed-by: Kalesh Anakkur Purayil <kalesh-anakkur.purayil@broadcom.com>
---
 drivers/net/bnxt/bnxt.h        |  1 +
 drivers/net/bnxt/bnxt_ethdev.c | 16 ++++++++++++----
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index d2944aa74..5770f4b73 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -713,6 +713,7 @@ struct bnxt {
 	rte_iova_t			hwrm_short_cmd_req_dma_addr;
 	rte_spinlock_t			hwrm_lock;
 	pthread_mutex_t			def_cp_lock;
+	pthread_mutex_t			health_check_lock;
 	uint16_t			max_req_len;
 	uint16_t			max_resp_len;
 	uint16_t                        hwrm_max_ext_req_len;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index e77e45486..8128b246a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1252,9 +1252,7 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 	eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 	eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 
-	pthread_mutex_lock(&bp->def_cp_lock);
 	bnxt_schedule_fw_health_check(bp);
-	pthread_mutex_unlock(&bp->def_cp_lock);
 
 	return 0;
 
@@ -4663,17 +4661,22 @@ void bnxt_schedule_fw_health_check(struct bnxt *bp)
 {
 	uint32_t polling_freq;
 
+	pthread_mutex_lock(&bp->health_check_lock);
+
 	if (!bnxt_is_recovery_enabled(bp))
-		return;
+		goto done;
 
 	if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
-		return;
+		goto done;
 
 	polling_freq = bp->recovery_info->driver_polling_freq;
 
 	rte_eal_alarm_set(US_PER_MS * polling_freq,
 			  bnxt_check_fw_health, (void *)bp);
 	bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
+
+done:
+	pthread_mutex_unlock(&bp->health_check_lock);
 }
 
 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
@@ -5461,6 +5464,10 @@ bnxt_init_locks(struct bnxt *bp)
 	err = pthread_mutex_init(&bp->def_cp_lock, NULL);
 	if (err)
 		PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
+
+	err = pthread_mutex_init(&bp->health_check_lock, NULL);
+	if (err)
+		PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
 	return err;
 }
 
@@ -5869,6 +5876,7 @@ bnxt_uninit_locks(struct bnxt *bp)
 {
 	pthread_mutex_destroy(&bp->flow_lock);
 	pthread_mutex_destroy(&bp->def_cp_lock);
+	pthread_mutex_destroy(&bp->health_check_lock);
 	if (bp->rep_info) {
 		pthread_mutex_destroy(&bp->rep_info->vfr_lock);
 		pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH v2 00/25] patchset for bnxt
  2020-09-11  1:55 [dpdk-dev] [PATCH 00/25] patchset for bnxt Ajit Khaparde
                   ` (24 preceding siblings ...)
  2020-09-11  1:56 ` [dpdk-dev] [PATCH 25/25] net/bnxt: fix to have a separate mutex for FW health check Ajit Khaparde
@ 2020-09-16  4:28 ` Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 01/25] net/bnxt: fix resource cleanup in port stop Ajit Khaparde
                     ` (25 more replies)
  25 siblings, 26 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-16  4:28 UTC (permalink / raw)
  To: dev

Some fixes and enhancements in the PMD and TruFlow layers.

v1->v2:
 - rebased to latest
 - updated commit messages

Kishore Padmanabha (14):
  net/bnxt: fix port stop process and cleanup resources
  net/bnxt: fix the drop action flow to support count
  net/bnxt: reject flow offload with invalid MAC
  net/bnxt: reduce debug log messages
  net/bnxt: fix coexistence of ipv4 and ipv6 ingress rules
  net/bnxt: modify default flow rule creation
  net/bnxt: fix the function id used in flow flush
  net/bnxt: refactor VFR port clean up
  net/bnxt: remove VLAN pop action for egress flows
  net/bnxt: increase counter support from 8K to 16K
  net/bnxt: enable VXLAN ipv6 encapsulation
  net/bnxt: enable NAT action with tagged traffic
  net/bnxt: fix out of bound access in bit handling
  net/bnxt: add locks in flow database

Mike Baucom (1):
  net/bnxt: free the EM index on failure

Randy Schacher (1):
  net/bnxt: use direct HWRM message for interface table

Shahaji Bhosle (2):
  net/bnxt: add null pointer check for resource manager
  net/bnxt: update resource settings

Somnath Kotur (6):
  net/bnxt: fix crash in VFR queue select
  net/bnxt: fix VFR cleanup during init failure
  net/bnxt: check and set initial counter ID
  net/bnxt: fix bugs in representor data path
  net/bnxt: fix to check VNIC in shutdown path
  net/bnxt: add separate mutex for FW health check

Sriharsha Basavapatna (1):
  net/bnxt: provide switch info if VFR are configured

 drivers/net/bnxt/bnxt.h                       |   13 +-
 drivers/net/bnxt/bnxt_ethdev.c                |  101 +-
 drivers/net/bnxt/bnxt_filter.c                |   14 +-
 drivers/net/bnxt/bnxt_hwrm.c                  |   13 +-
 drivers/net/bnxt/bnxt_reps.c                  |  162 +-
 drivers/net/bnxt/bnxt_reps.h                  |    8 +
 drivers/net/bnxt/bnxt_rxr.c                   |   27 +-
 drivers/net/bnxt/bnxt_vnic.c                  |    3 +
 drivers/net/bnxt/hsi_struct_def_dpdk.h        |  935 ++-
 drivers/net/bnxt/tf_core/tf_em_internal.c     |    5 +-
 drivers/net/bnxt/tf_core/tf_msg.c             |   58 +-
 drivers/net/bnxt/tf_core/tf_rm.c              |   14 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c            |  569 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h            |   34 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c       |   56 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c       |  131 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c          |    8 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h          |    1 +
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c         |   17 +-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h         |    4 +-
 drivers/net/bnxt/tf_ulp/ulp_mapper.c          |   52 +-
 drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c        |    6 -
 drivers/net/bnxt/tf_ulp/ulp_port_db.c         |   41 +
 drivers/net/bnxt/tf_ulp/ulp_port_db.h         |   13 +
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |  153 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h      |    5 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c |  295 +-
 .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 5531 +++++++++++------
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |   66 +-
 .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  767 ++-
 drivers/net/bnxt/tf_ulp/ulp_utils.c           |   43 +-
 drivers/net/bnxt/tf_ulp/ulp_utils.h           |    7 +-
 32 files changed, 5836 insertions(+), 3316 deletions(-)

-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH v2 01/25] net/bnxt: fix resource cleanup in port stop
  2020-09-16  4:28 ` [dpdk-dev] [PATCH v2 00/25] patchset for bnxt Ajit Khaparde
@ 2020-09-16  4:28   ` Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 02/25] net/bnxt: fix the drop action flow to support count Ajit Khaparde
                     ` (24 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-16  4:28 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Shahaji Bhosle

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The port deinitialization now cleans up all the resources
properly. If all the ports are stopped then ULP context is
freed.
Added fix to update the correct tfp pointer in the ULP context
with the changes to support multi control channels.

Fixes: 70e64b27af5b42 ("net/bnxt: support ULP session manager cleanup")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
---
 drivers/net/bnxt/bnxt.h                 |  12 +-
 drivers/net/bnxt/bnxt_ethdev.c          |  18 +-
 drivers/net/bnxt/bnxt_reps.c            | 106 ++---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c      | 494 ++++++++++++++----------
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h      |  16 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c |  19 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 131 ++++++-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c   |   4 +-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h   |   4 +-
 9 files changed, 494 insertions(+), 310 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index ef5824cf9..f0b080015 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -822,8 +822,7 @@ struct bnxt_vf_representor {
 	uint16_t		dflt_vnic_id;
 	uint16_t		svif;
 	uint16_t		vfr_tx_cfa_action;
-	uint32_t		rep2vf_flow_id;
-	uint32_t		vf2rep_flow_id;
+	uint32_t		dpdk_port_id;
 	/* Private data store of associated PF/Trusted VF */
 	struct rte_eth_dev	*parent_dev;
 	uint8_t			mac_addr[RTE_ETHER_ADDR_LEN];
@@ -893,11 +892,14 @@ extern int bnxt_logtype_driver;
 	  PMD_DRV_LOG_RAW(level, fmt, ## args)
 
 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
-int32_t bnxt_ulp_init(struct bnxt *bp);
-void bnxt_ulp_deinit(struct bnxt *bp);
+int32_t bnxt_ulp_port_init(struct bnxt *bp);
+void bnxt_ulp_port_deinit(struct bnxt *bp);
 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
-
+int32_t
+bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
+int32_t
+bnxt_ulp_delete_vfr_default_rules(struct bnxt_vf_representor *vfr);
 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
 		       enum bnxt_ulp_intf_type type);
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 2b2b2eeb8..073412de2 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1236,6 +1236,11 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 	if (rc)
 		goto error;
 
+	/* Initialize bnxt ULP port details */
+	rc = bnxt_ulp_port_init(bp);
+	if (rc)
+		goto error;
+
 	eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 	eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 
@@ -1243,8 +1248,6 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 	bnxt_schedule_fw_health_check(bp);
 	pthread_mutex_unlock(&bp->def_cp_lock);
 
-	bnxt_ulp_init(bp);
-
 	return 0;
 
 error:
@@ -1306,8 +1309,8 @@ static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 	/* disable uio/vfio intr/eventfd mapping */
 	rte_intr_disable(intr_handle);
 
-	bnxt_ulp_destroy_df_rules(bp, false);
-	bnxt_ulp_deinit(bp);
+	/* delete the bnxt ULP port details */
+	bnxt_ulp_port_deinit(bp);
 
 	bnxt_cancel_fw_health_check(bp);
 
@@ -1601,8 +1604,6 @@ static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 	if (rc != 0)
 		vnic->flags = old_flags;
 
-	bnxt_ulp_create_df_rules(bp);
-
 	return rc;
 }
 
@@ -3716,9 +3717,14 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
 	struct bnxt *bp = dev->data->dev_private;
 	int ret = 0;
 
+	if (!bp)
+		return -EIO;
+
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
 		struct bnxt_vf_representor *vfr = dev->data->dev_private;
 		bp = vfr->parent_dev->data->dev_private;
+		if (!bp)
+			return -EIO;
 	}
 
 	ret = is_bnxt_in_error(bp);
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index b4ed5d6ef..00e44bce5 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -267,66 +267,37 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
 	struct rte_eth_dev *parent_dev = vfr->parent_dev;
 	struct bnxt *parent_bp = parent_dev->data->dev_private;
-	uint16_t vfr_port_id = vfr_ethdev->data->port_id;
-	struct ulp_tlv_param param_list[] = {
-		{
-			.type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID,
-			.length = 2,
-			.value = {(vfr_port_id >> 8) & 0xff, vfr_port_id & 0xff}
-		},
-		{
-			.type = BNXT_ULP_DF_PARAM_TYPE_LAST,
-			.length = 0,
-			.value = {0}
-		}
-	};
 
-	ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev);
+	if (!parent_bp || !parent_bp->ulp_ctx) {
+		BNXT_TF_DBG(ERR, "Invalid arguments\n");
+		return 0;
+	}
 
-	rc = ulp_default_flow_create(parent_dev, param_list,
-				     BNXT_ULP_DF_TPL_VFREP_TO_VF,
-				     &vfr->rep2vf_flow_id);
+	/* Update the ULP portdata base with the new VFR interface */
+	rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev);
 	if (rc) {
-		BNXT_TF_DBG(DEBUG,
-			    "Default flow rule creation for VFR->VF failed!\n");
-		goto err;
+		BNXT_TF_DBG(ERR, "Failed to update ulp port details vfr:%u\n",
+			    vfr->vf_id);
+		return rc;
 	}
 
-	BNXT_TF_DBG(DEBUG, "*** Default flow rule created for VFR->VF! ***\n");
-	BNXT_TF_DBG(DEBUG, "rep2vf_flow_id = %d\n", vfr->rep2vf_flow_id);
-	rc = ulp_default_flow_db_cfa_action_get(parent_bp->ulp_ctx,
-						vfr->rep2vf_flow_id,
-						&vfr->vfr_tx_cfa_action);
-	if (rc) {
-		BNXT_TF_DBG(DEBUG,
-			    "Failed to get action_ptr for VFR->VF dflt rule\n");
-		goto rep2vf_free;
-	}
-	BNXT_TF_DBG(DEBUG, "tx_cfa_action = %d\n", vfr->vfr_tx_cfa_action);
-	rc = ulp_default_flow_create(parent_dev, param_list,
-				     BNXT_ULP_DF_TPL_VF_TO_VFREP,
-				     &vfr->vf2rep_flow_id);
+	/* Create the default rules for the VFR */
+	rc = bnxt_ulp_create_vfr_default_rules(vfr_ethdev);
 	if (rc) {
-		BNXT_TF_DBG(DEBUG,
-			    "Default flow rule creation for VF->VFR failed!\n");
-		goto rep2vf_free;
+		BNXT_TF_DBG(ERR, "Failed to create VFR default rules vfr:%u\n",
+			    vfr->vf_id);
+		return rc;
 	}
-
-	BNXT_TF_DBG(DEBUG, "*** Default flow rule created for VF->VFR! ***\n");
-	BNXT_TF_DBG(DEBUG, "vfr2rep_flow_id = %d\n", vfr->vf2rep_flow_id);
-
+	/* update the port id so you can backtrack to ethdev */
+	vfr->dpdk_port_id = vfr_ethdev->data->port_id;
 	rc = bnxt_hwrm_cfa_vfr_alloc(parent_bp, vfr->vf_id);
-	if (rc)
-		goto vf2rep_free;
-
-	return 0;
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed in hwrm vfr alloc vfr:%u rc=%d\n",
+			    vfr->vf_id, rc);
+		(void)bnxt_ulp_delete_vfr_default_rules(vfr);
+	}
 
-vf2rep_free:
-	ulp_default_flow_destroy(vfr->parent_dev, vfr->vf2rep_flow_id);
-rep2vf_free:
-	ulp_default_flow_destroy(vfr->parent_dev, vfr->rep2vf_flow_id);
-err:
-	return -EIO;
+	return rc;
 }
 
 static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
@@ -337,7 +308,7 @@ static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 
 	if (!vfr || !vfr->parent_dev) {
 		PMD_DRV_LOG(ERR,
-			    "No memory allocated for representor\n");
+				"No memory allocated for representor\n");
 		return -ENOMEM;
 	}
 
@@ -391,14 +362,12 @@ int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 	rep_info = &parent_bp->rep_info[rep_bp->vf_id];
 
 	pthread_mutex_lock(&rep_info->vfr_start_lock);
-	if (rep_info->conduit_valid) {
-		pthread_mutex_unlock(&rep_info->vfr_start_lock);
-		return 0;
-	}
-	rc = bnxt_get_dflt_vnic_svif(parent_bp, rep_bp);
-	if (rc || !rep_info->conduit_valid) {
-		pthread_mutex_unlock(&rep_info->vfr_start_lock);
-		return rc;
+	if (!rep_info->conduit_valid) {
+		rc = bnxt_get_dflt_vnic_svif(parent_bp, rep_bp);
+		if (rc || !rep_info->conduit_valid) {
+			pthread_mutex_unlock(&rep_info->vfr_start_lock);
+			return rc;
+		}
 	}
 	pthread_mutex_unlock(&rep_info->vfr_start_lock);
 
@@ -417,21 +386,7 @@ int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 
 static int bnxt_tf_vfr_free(struct bnxt_vf_representor *vfr)
 {
-	int rc = 0;
-
-	rc = ulp_default_flow_destroy(vfr->parent_dev,
-				      vfr->rep2vf_flow_id);
-	if (rc)
-		PMD_DRV_LOG(ERR,
-			    "default flow destroy failed rep2vf flowid: %d\n",
-			    vfr->rep2vf_flow_id);
-	rc = ulp_default_flow_destroy(vfr->parent_dev,
-				      vfr->vf2rep_flow_id);
-	if (rc)
-		PMD_DRV_LOG(ERR,
-			    "default flow destroy failed vf2rep flowid: %d\n",
-			    vfr->vf2rep_flow_id);
-	return 0;
+	return bnxt_ulp_delete_vfr_default_rules(vfr);
 }
 
 static int bnxt_vfr_free(struct bnxt_vf_representor *vfr)
@@ -458,7 +413,6 @@ static int bnxt_vfr_free(struct bnxt_vf_representor *vfr)
 		PMD_DRV_LOG(ERR,
 			    "Failed to free representor %d in FW\n",
 			    vfr->vf_id);
-		return rc;
 	}
 
 	PMD_DRV_LOG(DEBUG, "freed representor %d in FW\n",
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 0d4a45513..21baed048 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -32,23 +32,22 @@ static pthread_mutex_t bnxt_ulp_global_mutex = PTHREAD_MUTEX_INITIALIZER;
 
 /*
  * Allow the deletion of context only for the bnxt device that
- * created the session
- * TBD - The implementation of the function should change to
- * using the reference count once tf_session_attach functionality
- * is fixed.
+ * created the session.
  */
 bool
 ulp_ctx_deinit_allowed(void *ptr)
 {
 	struct bnxt *bp = (struct bnxt *)ptr;
 
-	if (!bp)
-		return 0;
+	if (!bp || !bp->ulp_ctx || !bp->ulp_ctx->cfg_data)
+		return false;
 
-	if (&bp->tfp == bp->ulp_ctx->g_tfp)
-		return 1;
+	if (!bp->ulp_ctx->cfg_data->ref_cnt) {
+		BNXT_TF_DBG(DEBUG, "ulp ctx shall initiate deinit\n");
+		return true;
+	}
 
-	return 0;
+	return false;
 }
 
 /*
@@ -155,8 +154,10 @@ ulp_ctx_session_open(struct bnxt *bp,
 			    params.ctrl_chan_name, rc);
 		return -EINVAL;
 	}
-	session->session_opened = 1;
-	session->g_tfp = &bp->tfp;
+	if (!session->session_opened) {
+		session->session_opened = 1;
+		session->g_tfp = &bp->tfp;
+	}
 	return rc;
 }
 
@@ -173,7 +174,6 @@ ulp_ctx_session_close(struct bnxt *bp,
 		tf_close_session(&bp->tfp);
 	session->session_opened = 0;
 	session->g_tfp = NULL;
-	bp->ulp_ctx->g_tfp = NULL;
 }
 
 static void
@@ -285,10 +285,6 @@ ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
 	if (!ulp_ctx || !ulp_ctx->cfg_data)
 		return -EINVAL;
 
-	/* Free the resources for the last device */
-	if (!ulp_ctx_deinit_allowed(bp))
-		return rc;
-
 	tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx);
 	if (!tfp) {
 		BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
@@ -331,11 +327,6 @@ static int32_t
 ulp_ctx_deinit(struct bnxt *bp,
 	       struct bnxt_ulp_session_state *session)
 {
-	if (!session || !bp) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
 	/* close the tf session */
 	ulp_ctx_session_close(bp, session);
 
@@ -356,11 +347,6 @@ ulp_ctx_init(struct bnxt *bp,
 	struct bnxt_ulp_data	*ulp_data;
 	int32_t			rc = 0;
 
-	if (!session || !bp) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
 	/* Allocate memory to hold ulp context data. */
 	ulp_data = rte_zmalloc("bnxt_ulp_data",
 			       sizeof(struct bnxt_ulp_data), 0);
@@ -378,11 +364,12 @@ ulp_ctx_init(struct bnxt *bp,
 	/* Open the ulp session. */
 	rc = ulp_ctx_session_open(bp, session);
 	if (rc) {
+		session->session_opened = 1;
 		(void)ulp_ctx_deinit(bp, session);
 		return rc;
 	}
 
-	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session->g_tfp);
+	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
 	return rc;
 }
 
@@ -395,7 +382,7 @@ ulp_dparms_init(struct bnxt *bp,
 	uint32_t dev_id;
 
 	if (!bp->max_num_kflows)
-		return -EINVAL;
+		return 0;
 
 	if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) {
 		BNXT_TF_DBG(DEBUG, "Failed to get device id\n");
@@ -445,51 +432,37 @@ ulp_dparms_dev_port_intf_update(struct bnxt *bp,
 }
 
 static int32_t
-ulp_ctx_attach(struct bnxt_ulp_context *ulp_ctx,
+ulp_ctx_attach(struct bnxt *bp,
 	       struct bnxt_ulp_session_state *session)
 {
-	if (!ulp_ctx || !session) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
+	int32_t rc = 0;
 
 	/* Increment the ulp context data reference count usage. */
-	ulp_ctx->cfg_data = session->cfg_data;
-	ulp_ctx->cfg_data->ref_cnt++;
+	bp->ulp_ctx->cfg_data = session->cfg_data;
+	bp->ulp_ctx->cfg_data->ref_cnt++;
 
-	/* TBD call TF_session_attach. */
-	ulp_ctx->g_tfp = session->g_tfp;
-	return 0;
-}
-
-static int32_t
-ulp_ctx_detach(struct bnxt *bp,
-	       struct bnxt_ulp_session_state *session)
-{
-	struct bnxt_ulp_context *ulp_ctx;
+	/* update the session details in bnxt tfp */
+	bp->tfp.session = session->g_tfp->session;
 
-	if (!bp || !session) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
+	/* Create a TF Client */
+	rc = ulp_ctx_session_open(bp, session);
+	if (rc) {
+		PMD_DRV_LOG(ERR, "Failed to open ctxt session, rc:%d\n", rc);
+		bp->tfp.session = NULL;
+		return rc;
 	}
-	ulp_ctx = bp->ulp_ctx;
 
-	if (!ulp_ctx->cfg_data)
-		return 0;
-
-	/* TBD call TF_session_detach */
+	bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+	return rc;
+}
 
-	/* Increment the ulp context data reference count usage. */
-	if (ulp_ctx->cfg_data->ref_cnt >= 1) {
-		ulp_ctx->cfg_data->ref_cnt--;
-		if (ulp_ctx_deinit_allowed(bp))
-			ulp_ctx_deinit(bp, session);
-		ulp_ctx->cfg_data = NULL;
-		ulp_ctx->g_tfp = NULL;
-		return 0;
+static void
+ulp_ctx_detach(struct bnxt *bp)
+{
+	if (bp->tfp.session) {
+		tf_close_session(&bp->tfp);
+		bp->tfp.session = NULL;
 	}
-	BNXT_TF_DBG(ERR, "context deatach on invalid data\n");
-	return 0;
 }
 
 /*
@@ -542,6 +515,7 @@ ulp_session_init(struct bnxt *bp,
 	struct rte_pci_device		*pci_dev;
 	struct rte_pci_addr		*pci_addr;
 	struct bnxt_ulp_session_state	*session;
+	int rc = 0;
 
 	if (!bp)
 		return NULL;
@@ -567,7 +541,12 @@ ulp_session_init(struct bnxt *bp,
 			/* Add it to the queue */
 			session->pci_info.domain = pci_addr->domain;
 			session->pci_info.bus = pci_addr->bus;
-			pthread_mutex_init(&session->bnxt_ulp_mutex, NULL);
+			rc = pthread_mutex_init(&session->bnxt_ulp_mutex, NULL);
+			if (rc) {
+				BNXT_TF_DBG(ERR, "mutex create failed\n");
+				pthread_mutex_unlock(&bnxt_ulp_global_mutex);
+				return NULL;
+			}
 			STAILQ_INSERT_TAIL(&bnxt_ulp_session_list,
 					   session, next);
 		}
@@ -643,80 +622,122 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
 	return rc;
 }
 
+/* Internal function to delete all the flows belonging to the given port */
+static void
+bnxt_ulp_flush_port_flows(struct bnxt *bp)
+{
+	uint16_t func_id;
+
+	func_id = bnxt_get_fw_func_id(bp->eth_dev->data->port_id,
+				      BNXT_ULP_INTF_TYPE_INVALID);
+	ulp_flow_db_function_flow_flush(bp->ulp_ctx, func_id);
+}
+
+/* Internal function to delete the VFR default flows */
+static void
+bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global)
+{
+	struct bnxt_ulp_vfr_rule_info *info;
+	uint8_t port_id;
+	struct rte_eth_dev *vfr_eth_dev;
+	struct bnxt_vf_representor *vfr_bp;
+
+	if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev))
+		return;
+
+	if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data)
+		return;
+
+	/* Delete default rules for all ports */
+	for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
+		info = &bp->ulp_ctx->cfg_data->vfr_rule_info[port_id];
+		if (!info->valid)
+			continue;
+
+		if (!global && info->parent_port_id !=
+		    bp->eth_dev->data->port_id)
+			continue;
+
+		/* Destroy the flows */
+		ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
+		ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
+		/* Clean up the tx action pointer */
+		vfr_eth_dev = &rte_eth_devices[port_id];
+		if (vfr_eth_dev) {
+			vfr_bp = vfr_eth_dev->data->dev_private;
+			vfr_bp->vfr_tx_cfa_action = 0;
+		}
+		memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
+	}
+}
+
 /*
- * When a port is initialized by dpdk. This functions is called
- * and this function initializes the ULP context and rest of the
+ * When a port is deinit'ed by dpdk. This function is called
+ * and this function clears the ULP context and rest of the
  * infrastructure associated with it.
  */
-int32_t
-bnxt_ulp_init(struct bnxt *bp)
+static void
+bnxt_ulp_deinit(struct bnxt *bp,
+		struct bnxt_ulp_session_state *session)
 {
-	struct bnxt_ulp_session_state *session;
-	bool init;
-	int rc;
+	if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data)
+		return;
 
-	if (!BNXT_TRUFLOW_EN(bp))
-		return 0;
+	/* clean up default flows */
+	bnxt_ulp_destroy_df_rules(bp, true);
 
-	if (bp->ulp_ctx) {
-		BNXT_TF_DBG(DEBUG, "ulp ctx already allocated\n");
-		return -EINVAL;
-	}
+	/* clean up default VFR flows */
+	bnxt_ulp_destroy_vfr_default_rules(bp, true);
 
-	/*
-	 * Multiple uplink ports can be associated with a single vswitch.
-	 * Make sure only the port that is started first will initialize
-	 * the TF session.
-	 */
-	session = ulp_session_init(bp, &init);
-	if (!session) {
-		BNXT_TF_DBG(ERR, "Failed to initialize the tf session\n");
-		return -EINVAL;
-	}
+	/* clean up regular flows */
+	ulp_flow_db_flush_flows(bp->ulp_ctx, BNXT_ULP_REGULAR_FLOW_TABLE);
 
-	bp->ulp_ctx = rte_zmalloc("bnxt_ulp_ctx",
-				  sizeof(struct bnxt_ulp_context), 0);
-	if (!bp->ulp_ctx) {
-		BNXT_TF_DBG(ERR, "Failed to allocate ulp ctx\n");
-		ulp_session_deinit(session);
-		return -ENOMEM;
-	}
+	/* cleanup the eem table scope */
+	ulp_eem_tbl_scope_deinit(bp, bp->ulp_ctx);
 
-	/*
-	 * If ULP is already initialized for a specific domain then simply
-	 * assign the ulp context to this rte_eth_dev.
-	 */
-	if (init) {
-		rc = ulp_ctx_attach(bp->ulp_ctx, session);
-		if (rc) {
-			BNXT_TF_DBG(ERR,
-				    "Failed to attach the ulp context\n");
-			ulp_session_deinit(session);
-			rte_free(bp->ulp_ctx);
-			return rc;
-		}
+	/* cleanup the flow database */
+	ulp_flow_db_deinit(bp->ulp_ctx);
 
-		/* Update bnxt driver flags */
-		rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
-		if (rc) {
-			BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
-			ulp_ctx_detach(bp, session);
-			ulp_session_deinit(session);
-			rte_free(bp->ulp_ctx);
-			return rc;
-		}
+	/* Delete the Mark database */
+	ulp_mark_db_deinit(bp->ulp_ctx);
 
-		/* update the port database */
-		rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
-		if (rc) {
-			BNXT_TF_DBG(ERR,
-				    "Failed to update port database\n");
-			ulp_ctx_detach(bp, session);
-			ulp_session_deinit(session);
-			rte_free(bp->ulp_ctx);
-		}
-		return rc;
-	}
+	/* cleanup the ulp mapper */
+	ulp_mapper_deinit(bp->ulp_ctx);
+
+	/* Delete the Flow Counter Manager */
+	ulp_fc_mgr_deinit(bp->ulp_ctx);
+
+	/* Delete the Port database */
+	ulp_port_db_deinit(bp->ulp_ctx);
+
+	/* Disable NAT feature */
+	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP,
+					 TF_TUNNEL_ENCAP_NAT,
+					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
+					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
+					 0);
+
+	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP,
+					 TF_TUNNEL_ENCAP_NAT,
+					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
+					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
+					 0);
+
+	/* Delete the ulp context and tf session and free the ulp context */
+	ulp_ctx_deinit(bp, session);
+	BNXT_TF_DBG(DEBUG, "ulp ctx has been deinitialized\n");
+}
+
+/*
+ * When a port is initialized by dpdk. This functions is called
+ * and this function initializes the ULP context and rest of the
+ * infrastructure associated with it.
+ */
+static int32_t
+bnxt_ulp_init(struct bnxt *bp,
+	      struct bnxt_ulp_session_state *session)
+{
+	int rc;
 
 	/* Allocate and Initialize the ulp context. */
 	rc = ulp_ctx_init(bp, session);
@@ -727,25 +748,15 @@ bnxt_ulp_init(struct bnxt *bp)
 
 	/* Initialize ulp dparms with values devargs passed */
 	rc = ulp_dparms_init(bp, bp->ulp_ctx);
-
-	/* create the port database */
-	rc = ulp_port_db_init(bp->ulp_ctx, bp->port_cnt);
-	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to create the port database\n");
-		goto jump_to_error;
-	}
-
-	/* Update bnxt driver flags */
-	rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
 	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
+		BNXT_TF_DBG(ERR, "Failed to initialize the dparms\n");
 		goto jump_to_error;
 	}
 
-	/* update the port database */
-	rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
+	/* create the port database */
+	rc = ulp_port_db_init(bp->ulp_ctx, bp->port_cnt);
 	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to update port database\n");
+		BNXT_TF_DBG(ERR, "Failed to create the port database\n");
 		goto jump_to_error;
 	}
 
@@ -804,32 +815,131 @@ bnxt_ulp_init(struct bnxt *bp)
 		BNXT_TF_DBG(ERR, "Failed to set tx global configuration\n");
 		goto jump_to_error;
 	}
-
+	BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n");
 	return rc;
 
 jump_to_error:
-	bnxt_ulp_deinit(bp);
-	return -ENOMEM;
+	bnxt_ulp_deinit(bp, session);
+	return rc;
 }
 
-/* Below are the access functions to access internal data of ulp context. */
+/*
+ * When a port is initialized by dpdk. This functions sets up
+ * the port specific details.
+ */
+int32_t
+bnxt_ulp_port_init(struct bnxt *bp)
+{
+	struct bnxt_ulp_session_state *session;
+	bool initialized;
+	int32_t rc = 0;
+
+	if (!bp || !BNXT_TRUFLOW_EN(bp))
+		return rc;
+
+	if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
+		BNXT_TF_DBG(ERR,
+			    "Skip ulp init for port: %d, not a TVF or PF\n",
+			bp->eth_dev->data->port_id);
+		return rc;
+	}
+
+	if (bp->ulp_ctx) {
+		BNXT_TF_DBG(DEBUG, "ulp ctx already allocated\n");
+		return rc;
+	}
+
+	bp->ulp_ctx = rte_zmalloc("bnxt_ulp_ctx",
+				  sizeof(struct bnxt_ulp_context), 0);
+	if (!bp->ulp_ctx) {
+		BNXT_TF_DBG(ERR, "Failed to allocate ulp ctx\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * Multiple uplink ports can be associated with a single vswitch.
+	 * Make sure only the port that is started first will initialize
+	 * the TF session.
+	 */
+	session = ulp_session_init(bp, &initialized);
+	if (!session) {
+		BNXT_TF_DBG(ERR, "Failed to initialize the tf session\n");
+		rc = -EIO;
+		goto jump_to_error;
+	}
+
+	if (initialized) {
+		/*
+		 * If ULP is already initialized for a specific domain then
+		 * simply assign the ulp context to this rte_eth_dev.
+		 */
+		rc = ulp_ctx_attach(bp, session);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Failed to attach the ulp context\n");
+			goto jump_to_error;
+		}
+	} else {
+		rc = bnxt_ulp_init(bp, session);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Failed to initialize the ulp init\n");
+			goto jump_to_error;
+		}
+	}
+
+	/* Update bnxt driver flags */
+	rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
+		goto jump_to_error;
+	}
+
+	/* update the port database for the given interface */
+	rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to update port database\n");
+		goto jump_to_error;
+	}
+	/* create the default rules */
+	bnxt_ulp_create_df_rules(bp);
+	BNXT_TF_DBG(DEBUG, "ULP Port:%d created and initialized\n",
+		    bp->eth_dev->data->port_id);
+	return rc;
+
+jump_to_error:
+	bnxt_ulp_port_deinit(bp);
+	return rc;
+}
 
 /*
- * When a port is deinit'ed by dpdk. This function is called
- * and this function clears the ULP context and rest of the
- * infrastructure associated with it.
+ * When a port is de-initialized by dpdk. This functions clears up
+ * the port specific details.
  */
 void
-bnxt_ulp_deinit(struct bnxt *bp)
+bnxt_ulp_port_deinit(struct bnxt *bp)
 {
-	struct bnxt_ulp_session_state	*session;
-	struct rte_pci_device		*pci_dev;
-	struct rte_pci_addr		*pci_addr;
+	struct bnxt_ulp_session_state *session;
+	struct rte_pci_device *pci_dev;
+	struct rte_pci_addr *pci_addr;
 
 	if (!BNXT_TRUFLOW_EN(bp))
 		return;
 
-	/* Get the session first */
+	if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
+		BNXT_TF_DBG(ERR,
+			    "Skip ULP deinit port:%d, not a TVF or PF\n",
+			    bp->eth_dev->data->port_id);
+		return;
+	}
+
+	if (!bp->ulp_ctx) {
+		BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
+		return;
+	}
+
+	BNXT_TF_DBG(DEBUG, "ULP Port:%d destroyed\n",
+		    bp->eth_dev->data->port_id);
+
+	/* Get the session details  */
 	pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device);
 	pci_addr = &pci_dev->addr;
 	pthread_mutex_lock(&bnxt_ulp_global_mutex);
@@ -837,57 +947,42 @@ bnxt_ulp_deinit(struct bnxt *bp)
 	pthread_mutex_unlock(&bnxt_ulp_global_mutex);
 
 	/* session not found then just exit */
-	if (!session)
+	if (!session) {
+		/* Free the ulp context */
+		rte_free(bp->ulp_ctx);
+		bp->ulp_ctx = NULL;
 		return;
+	}
 
-	/* clean up default flows */
-	bnxt_ulp_destroy_df_rules(bp, true);
-
-	/* clean up regular flows */
-	ulp_flow_db_flush_flows(bp->ulp_ctx, BNXT_ULP_REGULAR_FLOW_TABLE);
-
-	/* cleanup the eem table scope */
-	ulp_eem_tbl_scope_deinit(bp, bp->ulp_ctx);
-
-	/* cleanup the flow database */
-	ulp_flow_db_deinit(bp->ulp_ctx);
-
-	/* Delete the Mark database */
-	ulp_mark_db_deinit(bp->ulp_ctx);
-
-	/* cleanup the ulp mapper */
-	ulp_mapper_deinit(bp->ulp_ctx);
-
-	/* Delete the Flow Counter Manager */
-	ulp_fc_mgr_deinit(bp->ulp_ctx);
-
-	/* Delete the Port database */
-	ulp_port_db_deinit(bp->ulp_ctx);
-
-	/* Disable NAT feature */
-	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP,
-					 TF_TUNNEL_ENCAP_NAT,
-					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
-					 0);
+	/* Check the reference count to deinit or deattach*/
+	if (bp->ulp_ctx->cfg_data && bp->ulp_ctx->cfg_data->ref_cnt) {
+		bp->ulp_ctx->cfg_data->ref_cnt--;
+		if (bp->ulp_ctx->cfg_data->ref_cnt) {
+			/* free the port details */
+			/* Free the default flow rule associated to this port */
+			bnxt_ulp_destroy_df_rules(bp, false);
+			bnxt_ulp_destroy_vfr_default_rules(bp, false);
 
-	(void)bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP,
-					 TF_TUNNEL_ENCAP_NAT,
-					 (BNXT_ULP_NAT_INNER_L2_HEADER_SMAC |
-					  BNXT_ULP_NAT_INNER_L2_HEADER_DMAC),
-					 0);
+			/* free flows associated with this port */
+			bnxt_ulp_flush_port_flows(bp);
 
-	/* Delete the ulp context and tf session */
-	ulp_ctx_detach(bp, session);
+			/* close the session associated with this port */
+			ulp_ctx_detach(bp);
+		} else {
+			/* Perform ulp ctx deinit */
+			bnxt_ulp_deinit(bp, session);
+		}
+	}
 
-	/* Finally delete the bnxt session*/
+	/* clean up the session */
 	ulp_session_deinit(session);
 
+	/* Free the ulp context */
 	rte_free(bp->ulp_ctx);
-
 	bp->ulp_ctx = NULL;
 }
 
+/* Below are the access functions to access internal data of ulp context. */
 /* Function to set the Mark DB into the context */
 int32_t
 bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx,
@@ -974,7 +1069,6 @@ bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
 		return -EINVAL;
 	}
 
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	ulp->g_tfp = tfp;
 	return 0;
 }
@@ -987,7 +1081,6 @@ bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp)
 		BNXT_TF_DBG(ERR, "Invalid arguments\n");
 		return NULL;
 	}
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	return ulp->g_tfp;
 }
 
@@ -1129,3 +1222,14 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx,
 	*flags =  ulp_ctx->cfg_data->ulp_flags;
 	return 0;
 }
+
+/* Function to get the ulp vfr info from the ulp context. */
+struct bnxt_ulp_vfr_rule_info*
+bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(struct bnxt_ulp_context *ulp_ctx,
+				     uint32_t port_id)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data || port_id >= RTE_MAX_ETHPORTS)
+		return NULL;
+
+	return &ulp_ctx->cfg_data->vfr_rule_info[port_id];
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index d53245215..8a2825ae5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -28,6 +28,13 @@ struct bnxt_ulp_df_rule_info {
 	uint8_t				valid;
 };
 
+struct bnxt_ulp_vfr_rule_info {
+	uint32_t			rep2vf_flow_id;
+	uint32_t			vf2rep_flow_id;
+	uint16_t			parent_port_id;
+	uint8_t				valid;
+};
+
 struct bnxt_ulp_data {
 	uint32_t			tbl_scope_id;
 	struct bnxt_ulp_mark_tbl	*mark_tbl;
@@ -38,12 +45,12 @@ struct bnxt_ulp_data {
 	struct bnxt_ulp_port_db		*port_db;
 	struct bnxt_ulp_fc_info		*fc_info;
 	uint32_t			ulp_flags;
-	struct bnxt_ulp_df_rule_info   df_rule_info[RTE_MAX_ETHPORTS];
+	struct bnxt_ulp_df_rule_info	df_rule_info[RTE_MAX_ETHPORTS];
+	struct bnxt_ulp_vfr_rule_info	vfr_rule_info[RTE_MAX_ETHPORTS];
 };
 
 struct bnxt_ulp_context {
 	struct bnxt_ulp_data	*cfg_data;
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	struct tf		*g_tfp;
 };
 
@@ -58,7 +65,6 @@ struct bnxt_ulp_session_state {
 	pthread_mutex_t				bnxt_ulp_mutex;
 	struct bnxt_ulp_pci_info		pci_info;
 	struct bnxt_ulp_data			*cfg_data;
-	/* TBD The tfp should be removed once tf_attach is implemented. */
 	struct tf				*g_tfp;
 	uint32_t				session_opened;
 };
@@ -183,4 +189,8 @@ int32_t
 bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx,
 			  struct bnxt_ulp_df_rule_info *info);
 
+struct bnxt_ulp_vfr_rule_info*
+bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(struct bnxt_ulp_context *ulp_ctx,
+				     uint32_t port_id);
+
 #endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 89fffcf01..2ab00453a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -87,19 +87,19 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	uint32_t class_id, act_tmpl;
 	struct rte_flow *flow_id;
 	uint32_t fid;
-	int ret;
+	int ret = BNXT_TF_RC_ERROR;
 
 	if (bnxt_ulp_flow_validate_args(attr,
 					pattern, actions,
 					error) == BNXT_TF_RC_ERROR) {
 		BNXT_TF_DBG(ERR, "Invalid arguments being passed\n");
-		return NULL;
+		goto parse_error;
 	}
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		return NULL;
+		goto parse_error;
 	}
 
 	/* Initialize the parser params */
@@ -173,20 +173,20 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
 {
 	struct ulp_rte_parser_params		params;
 	uint32_t class_id, act_tmpl;
-	int ret;
+	int ret = BNXT_TF_RC_ERROR;
 	struct bnxt_ulp_context *ulp_ctx;
 
 	if (bnxt_ulp_flow_validate_args(attr,
 					pattern, actions,
 					error) == BNXT_TF_RC_ERROR) {
 		BNXT_TF_DBG(ERR, "Invalid arguments being passed\n");
-		return -EINVAL;
+		goto parse_error;
 	}
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		return -EINVAL;
+		goto parse_error;
 	}
 
 	/* Initialize the parser params */
@@ -289,11 +289,8 @@ bnxt_ulp_flow_flush(struct rte_eth_dev *eth_dev,
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
 	if (!ulp_ctx) {
-		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		rte_flow_error_set(error, EINVAL,
-				   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
-				   "Failed to flush flow.");
-		return -EINVAL;
+		BNXT_TF_DBG(DEBUG, "ULP context is not initialized\n");
+		return ret;
 	}
 	bp = eth_dev->data->dev_private;
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index 46acc1d65..2d0c3bccc 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -377,7 +377,7 @@ int32_t
 ulp_default_flow_destroy(struct rte_eth_dev *eth_dev, uint32_t flow_id)
 {
 	struct bnxt_ulp_context *ulp_ctx;
-	int rc;
+	int rc = 0;
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
 	if (!ulp_ctx) {
@@ -385,6 +385,11 @@ ulp_default_flow_destroy(struct rte_eth_dev *eth_dev, uint32_t flow_id)
 		return -EINVAL;
 	}
 
+	if (!flow_id) {
+		BNXT_TF_DBG(DEBUG, "invalid flow id zero\n");
+		return rc;
+	}
+
 	rc = ulp_mapper_flow_destroy(ulp_ctx, flow_id,
 				     BNXT_ULP_DEFAULT_FLOW_TABLE);
 	if (rc)
@@ -417,7 +422,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
 					 info->port_to_app_flow_id);
 		ulp_default_flow_destroy(bp->eth_dev,
 					 info->app_to_port_flow_id);
-		info->valid = false;
+		memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info));
 		return;
 	}
 
@@ -431,7 +436,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
 					 info->port_to_app_flow_id);
 		ulp_default_flow_destroy(bp->eth_dev,
 					 info->app_to_port_flow_id);
-		info->valid = false;
+		memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info));
 	}
 }
 
@@ -470,22 +475,19 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
 
 	port_id = bp->eth_dev->data->port_id;
 	info = &bp->ulp_ctx->cfg_data->df_rule_info[port_id];
-	BNXT_TF_DBG(INFO, "*** creating port to app default rule ***\n");
 	rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS,
 					  &info->port_to_app_flow_id);
 	if (rc) {
-		PMD_DRV_LOG(ERR,
+		BNXT_TF_DBG(ERR,
 			    "Failed to create port to app default rule\n");
 		return rc;
 	}
-	BNXT_TF_DBG(INFO, "*** created port to app default rule ***\n");
 
 	bp->tx_cfa_action = 0;
-	BNXT_TF_DBG(INFO, "*** creating app to port default rule ***\n");
 	rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT,
 					  &info->app_to_port_flow_id);
 	if (rc) {
-		PMD_DRV_LOG(ERR,
+		BNXT_TF_DBG(ERR,
 			    "Failed to create app to port default rule\n");
 		goto port_to_app_free;
 	}
@@ -497,7 +499,6 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
 		goto app_to_port_free;
 
 	info->valid = true;
-	BNXT_TF_DBG(INFO, "*** created app to port default rule ***\n");
 	return 0;
 
 app_to_port_free:
@@ -508,3 +509,115 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
 
 	return rc;
 }
+
+static int32_t
+bnxt_create_port_vfr_default_rule(struct bnxt *bp,
+				  uint8_t flow_type,
+				  uint16_t vfr_port_id,
+				  uint32_t *flow_id)
+{
+	struct ulp_tlv_param param_list[] = {
+		{
+			.type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID,
+			.length = 2,
+			.value = {(vfr_port_id >> 8) & 0xff, vfr_port_id & 0xff}
+		},
+		{
+			.type = BNXT_ULP_DF_PARAM_TYPE_LAST,
+			.length = 0,
+			.value = {0}
+		}
+	};
+	return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
+				       flow_id);
+}
+
+int32_t
+bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
+{
+	struct bnxt_ulp_vfr_rule_info *info;
+	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
+	struct rte_eth_dev *parent_dev = vfr->parent_dev;
+	struct bnxt *bp = parent_dev->data->dev_private;
+	uint16_t vfr_port_id = vfr_ethdev->data->port_id;
+	uint8_t port_id;
+	int rc;
+
+	if (!bp || !BNXT_TRUFLOW_EN(bp))
+		return 0;
+
+	port_id = vfr_ethdev->data->port_id;
+	info = bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(bp->ulp_ctx, port_id);
+
+	if (!info) {
+		BNXT_TF_DBG(ERR, "Failed to get vfr ulp context\n");
+		return -EINVAL;
+	}
+
+	if (info->valid) {
+		BNXT_TF_DBG(ERR, "VFR already allocated\n");
+		return -EINVAL;
+	}
+
+	memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
+	rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VFREP_TO_VF,
+					       vfr_port_id,
+					       &info->rep2vf_flow_id);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to create VFREP to VF default rule\n");
+		goto error;
+	}
+	rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VF_TO_VFREP,
+					       vfr_port_id,
+					       &info->vf2rep_flow_id);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to create VF to VFREP default rule\n");
+		goto error;
+	}
+	rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
+						info->rep2vf_flow_id,
+						&vfr->vfr_tx_cfa_action);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to get the tx cfa action\n");
+		goto error;
+	}
+
+	/* Update the other details */
+	info->valid = true;
+	info->parent_port_id =  bp->eth_dev->data->port_id;
+	return 0;
+
+error:
+	if (info->rep2vf_flow_id)
+		ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
+	if (info->vf2rep_flow_id)
+		ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
+	return rc;
+}
+
+int32_t
+bnxt_ulp_delete_vfr_default_rules(struct bnxt_vf_representor *vfr)
+{
+	struct bnxt_ulp_vfr_rule_info *info;
+	struct rte_eth_dev *parent_dev = vfr->parent_dev;
+	struct bnxt *bp = parent_dev->data->dev_private;
+
+	if (!bp || !BNXT_TRUFLOW_EN(bp))
+		return 0;
+	info = bnxt_ulp_cntxt_ptr2_ulp_vfr_info_get(bp->ulp_ctx,
+						    vfr->dpdk_port_id);
+	if (!info) {
+		BNXT_TF_DBG(ERR, "Failed to get vfr ulp context\n");
+		return -EINVAL;
+	}
+
+	if (!info->valid) {
+		BNXT_TF_DBG(ERR, "VFR already freed\n");
+		return -EINVAL;
+	}
+	ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
+	ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
+	vfr->vfr_tx_cfa_action = 0;
+	memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
+	return 0;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 714451740..cbdf5df68 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -351,10 +351,8 @@ int32_t	ulp_flow_db_deinit(struct bnxt_ulp_context *ulp_ctxt)
 	struct bnxt_ulp_flow_db			*flow_db;
 
 	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
-	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+	if (!flow_db)
 		return -EINVAL;
-	}
 
 	/* Detach the flow database from the ulp context. */
 	bnxt_ulp_cntxt_ptr2_flow_db_set(ulp_ctxt, NULL);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 117e250d6..8c83664d0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -9,8 +9,8 @@
 #include "bnxt_ulp.h"
 #include "ulp_template_db_enum.h"
 
-#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS		128
-#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES	5
+#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS		512
+#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES	8
 
 /*
  * Structure for the flow database resource information
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH v2 02/25] net/bnxt: fix the drop action flow to support count
  2020-09-16  4:28 ` [dpdk-dev] [PATCH v2 00/25] patchset for bnxt Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 01/25] net/bnxt: fix resource cleanup in port stop Ajit Khaparde
@ 2020-09-16  4:28   ` Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 03/25] net/bnxt: reject flow offload with invalid MAC Ajit Khaparde
                     ` (23 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-16  4:28 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Changed the action template to support count action in addition
to a flow that does drop action.

Fixes: fe82f3e02701 ("net/bnxt: support exact match templates")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c  | 5 +++--
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index 14ce16ebd..b669a1408 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -36,7 +36,7 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_0020] = 25,
 	[BNXT_ULP_ACT_HID_0901] = 26,
 	[BNXT_ULP_ACT_HID_0121] = 27,
-	[BNXT_ULP_ACT_HID_0004] = 28,
+	[BNXT_ULP_ACT_HID_0006] = 28,
 	[BNXT_ULP_ACT_HID_0804] = 29,
 	[BNXT_ULP_ACT_HID_0105] = 30,
 	[BNXT_ULP_ACT_HID_0024] = 31,
@@ -332,9 +332,10 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 2
 	},
 	[28] = {
-	.act_hid = BNXT_ULP_ACT_HID_0004,
+	.act_hid = BNXT_ULP_ACT_HID_0006,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
+		BNXT_ULP_ACTION_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 4c6c3599d..f5c43a9f8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -838,7 +838,7 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_0020 = 0x0020,
 	BNXT_ULP_ACT_HID_0901 = 0x0901,
 	BNXT_ULP_ACT_HID_0121 = 0x0121,
-	BNXT_ULP_ACT_HID_0004 = 0x0004,
+	BNXT_ULP_ACT_HID_0006 = 0x0006,
 	BNXT_ULP_ACT_HID_0804 = 0x0804,
 	BNXT_ULP_ACT_HID_0105 = 0x0105,
 	BNXT_ULP_ACT_HID_0024 = 0x0024,
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH v2 03/25] net/bnxt: reject flow offload with invalid MAC
  2020-09-16  4:28 ` [dpdk-dev] [PATCH v2 00/25] patchset for bnxt Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 01/25] net/bnxt: fix resource cleanup in port stop Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 02/25] net/bnxt: fix the drop action flow to support count Ajit Khaparde
@ 2020-09-16  4:28   ` Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 04/25] net/bnxt: reduce debug log messages Ajit Khaparde
                     ` (22 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-16  4:28 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Reject offload flows that have broadcast or multicast
ethernet addresses.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index fcb7c4430..c0339e6ab 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -603,6 +603,19 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
 	}
 }
 
+/* Internal Function to identify broadcast or multicast packets */
+static int32_t
+ulp_rte_parser_is_bcmc_addr(const struct rte_ether_addr *eth_addr)
+{
+	if (rte_is_multicast_ether_addr(eth_addr) ||
+	    rte_is_broadcast_ether_addr(eth_addr)) {
+		BNXT_TF_DBG(DEBUG,
+			    "No support for bcast or mcast addr offload\n");
+		return 1;
+	}
+	return 0;
+}
+
 /* Function to handle the parsing of RTE Flow item Ethernet Header. */
 int32_t
 ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
@@ -625,10 +638,18 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
 		field = ulp_rte_parser_fld_copy(&params->hdr_field[idx],
 						eth_spec->dst.addr_bytes,
 						size);
+		/* Todo: work around to avoid multicast and broadcast addr */
+		if (ulp_rte_parser_is_bcmc_addr(&eth_spec->dst))
+			return BNXT_TF_RC_PARSE_ERR;
+
 		size = sizeof(eth_spec->src.addr_bytes);
 		field = ulp_rte_parser_fld_copy(field,
 						eth_spec->src.addr_bytes,
 						size);
+		/* Todo: work around to avoid multicast and broadcast addr */
+		if (ulp_rte_parser_is_bcmc_addr(&eth_spec->src))
+			return BNXT_TF_RC_PARSE_ERR;
+
 		field = ulp_rte_parser_fld_copy(field,
 						&eth_spec->type,
 						sizeof(eth_spec->type));
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH v2 04/25] net/bnxt: reduce debug log messages
  2020-09-16  4:28 ` [dpdk-dev] [PATCH v2 00/25] patchset for bnxt Ajit Khaparde
                     ` (2 preceding siblings ...)
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 03/25] net/bnxt: reject flow offload with invalid MAC Ajit Khaparde
@ 2020-09-16  4:28   ` Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 05/25] net/bnxt: fix coexistence of ipv4 and ipv6 ingress rules Ajit Khaparde
                     ` (21 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-16  4:28 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Removed the mark id log message since it is in the data path.
Also optimized the link status debug message.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt_hwrm.c           | 13 ++++---------
 drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c |  6 ------
 2 files changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index b26952646..57d1026f9 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1343,15 +1343,10 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 
 	HWRM_UNLOCK();
 
-	PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
-	PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
-	PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
-	PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
-	PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
-		    link_info->auto_link_speed_mask);
-	PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
-		    link_info->force_link_speed);
-
+	PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
+		    link_info->link_speed, link_info->auto_mode,
+		    link_info->auto_link_speed, link_info->auto_link_speed_mask,
+		    link_info->support_speeds, link_info->force_link_speed);
 	return rc;
 }
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 4df850f22..8b8dccf9f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -194,9 +194,6 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
 		    ULP_MARK_DB_ENTRY_IS_INVALID(&mtbl->gfid_tbl[idx]))
 			return -EINVAL;
 
-		BNXT_TF_DBG(DEBUG, "Get GFID[0x%0x] = 0x%0x\n",
-			    idx, mtbl->gfid_tbl[idx].mark_id);
-
 		*vfr_flag = ULP_MARK_DB_ENTRY_IS_VFR_ID(&mtbl->gfid_tbl[idx]);
 		*mark = mtbl->gfid_tbl[idx].mark_id;
 	} else {
@@ -204,9 +201,6 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
 		    ULP_MARK_DB_ENTRY_IS_INVALID(&mtbl->lfid_tbl[idx]))
 			return -EINVAL;
 
-		BNXT_TF_DBG(DEBUG, "Get LFID[0x%0x] = 0x%0x\n",
-			    idx, mtbl->lfid_tbl[idx].mark_id);
-
 		*vfr_flag = ULP_MARK_DB_ENTRY_IS_VFR_ID(&mtbl->lfid_tbl[idx]);
 		*mark = mtbl->lfid_tbl[idx].mark_id;
 	}
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [dpdk-dev] [PATCH v2 05/25] net/bnxt: fix coexistence of ipv4 and ipv6 ingress rules
  2020-09-16  4:28 ` [dpdk-dev] [PATCH v2 00/25] patchset for bnxt Ajit Khaparde
                     ` (3 preceding siblings ...)
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 04/25] net/bnxt: reduce debug log messages Ajit Khaparde
@ 2020-09-16  4:28   ` Ajit Khaparde
  2020-09-16  4:28   ` [dpdk-dev] [PATCH v2 06/25] net/bnxt: free the EM index on failure Ajit Khaparde
                     ` (20 subsequent siblings)
  25 siblings, 0 replies; 56+ messages in thread
From: Ajit Khaparde @ 2020-09-16  4:28 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The ingress rule to match on ipv4 and ipv6 is now two rules to
make sure both rules can coexist at the same time. Added count
action only for ingress flows.

Fixes: fe82f3e02701 ("net/bnxt: support exact match templates")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c |  298 +-
 .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 5522 +++++++++++------
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |   66 +-
 .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  767 ++-
 4 files changed, 4088 insertions(+), 2565 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index b669a1408..22142c137 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -36,64 +36,61 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_0020] = 25,
 	[BNXT_ULP_ACT_HID_0901] = 26,
 	[BNXT_ULP_ACT_HID_0121] = 27,
-	[BNXT_ULP_ACT_HID_0006] = 28,
-	[BNXT_ULP_ACT_HID_0804] = 29,
-	[BNXT_ULP_ACT_HID_0105] = 30,
-	[BNXT_ULP_ACT_HID_0024] = 31,
-	[BNXT_ULP_ACT_HID_0905] = 32,
-	[BNXT_ULP_ACT_HID_0125] = 33,
-	[BNXT_ULP_ACT_HID_0001] = 34,
-	[BNXT_ULP_ACT_HID_0005] = 35,
-	[BNXT_ULP_ACT_HID_0009] = 36,
-	[BNXT_ULP_ACT_HID_000d] = 37,
-	[BNXT_ULP_ACT_HID_0021] = 38,
-	[BNXT_ULP_ACT_HID_0029] = 39,
-	[BNXT_ULP_ACT_HID_0025] = 40,
-	[BNXT_ULP_ACT_HID_002d] = 41,
-	[BNXT_ULP_ACT_HID_0801] = 42,
-	[BNXT_ULP_ACT_HID_0809] = 43,
-	[BNXT_ULP_ACT_HID_0805] = 44,
-	[BNXT_ULP_ACT_HID_080d] = 45,
-	[BNXT_ULP_ACT_HID_0c15] = 46,
-	[BNXT_ULP_ACT_HID_0c19] = 47,
-	[BNXT_ULP_ACT_HID_02f6] = 48,
-	[BNXT_ULP_ACT_HID_04f8] = 49,
-	[BNXT_ULP_ACT_HID_01df] = 50,
-	[BNXT_ULP_ACT_HID_07e5] = 51,
-	[BNXT_ULP_ACT_HID_06ce] = 52,
-	[BNXT_ULP_ACT_HID_02fa] = 53,
-	[BNXT_ULP_ACT_HID_04fc] = 54,
-	[BNXT_ULP_ACT_HID_01e3] = 55,
-	[BNXT_ULP_ACT_HID_07e9] = 56,
-	[BNXT_ULP_ACT_HID_06d2] = 57,
-	[BNXT_ULP_ACT_HID_03f7] = 58,
-	[BNXT_ULP_ACT_HID_05f9] = 59,
-	[BNXT_ULP_ACT_HID_02e0] = 60,
-	[BNXT_ULP_ACT_HID_08e6] = 61,
-	[BNXT_ULP_ACT_HID_07cf] = 62,
-	[BNXT_ULP_ACT_HID_03fb] = 63,
-	[BNXT_ULP_ACT_HID_05fd] = 64,
-	[BNXT_ULP_ACT_HID_02e4] = 65,
-	[BNXT_ULP_ACT_HID_08ea] = 66,
-	[BNXT_ULP_ACT_HID_07d3] = 67,
-	[BNXT_ULP_ACT_HID_040d] = 68,
-	[BNXT_ULP_ACT_HID_040f] = 69,
-	[BNXT_ULP_ACT_HID_0413] = 70,
-	[BNXT_ULP_ACT_HID_0c0d] = 71,
+	[BNXT_ULP_ACT_HID_0004] = 28,
+	[BNXT_ULP_ACT_HID_0006] = 29,
+	[BNXT_ULP_ACT_HID_0804] = 30,
+	[BNXT_ULP_ACT_HID_0105] = 31,
+	[BNXT_ULP_ACT_HID_0024] = 32,
+	[BNXT_ULP_ACT_HID_0905] = 33,
+	[BNXT_ULP_ACT_HID_0125] = 34,
+	[BNXT_ULP_ACT_HID_0001] = 35,
+	[BNXT_ULP_ACT_HID_0005] = 36,
+	[BNXT_ULP_ACT_HID_0009] = 37,
+	[BNXT_ULP_ACT_HID_000d] = 38,
+	[BNXT_ULP_ACT_HID_0021] = 39,
+	[BNXT_ULP_ACT_HID_0029] = 40,
+	[BNXT_ULP_ACT_HID_0025] = 41,
+	[BNXT_ULP_ACT_HID_002d] = 42,
+	[BNXT_ULP_ACT_HID_0801] = 43,
+	[BNXT_ULP_ACT_HID_0809] = 44,
+	[BNXT_ULP_ACT_HID_0805] = 45,
+	[BNXT_ULP_ACT_HID_080d] = 46,
+	[BNXT_ULP_ACT_HID_0c15] = 47,
+	[BNXT_ULP_ACT_HID_0c19] = 48,
+	[BNXT_ULP_ACT_HID_02f6] = 49,
+	[BNXT_ULP_ACT_HID_04f8] = 50,
+	[BNXT_ULP_ACT_HID_01df] = 51,
+	[BNXT_ULP_ACT_HID_07e5] = 52,
+	[BNXT_ULP_ACT_HID_06ce] = 53,
+	[BNXT_ULP_ACT_HID_02fa] = 54,
+	[BNXT_ULP_ACT_HID_04fc] = 55,
+	[BNXT_ULP_ACT_HID_01e3] = 56,
+	[BNXT_ULP_ACT_HID_07e9] = 57,
+	[BNXT_ULP_ACT_HID_06d2] = 58,
+	[BNXT_ULP_ACT_HID_03f7] = 59,
+	[BNXT_ULP_ACT_HID_05f9] = 60,
+	[BNXT_ULP_ACT_HID_02e0] = 61,
+	[BNXT_ULP_ACT_HID_08e6] = 62,
+	[BNXT_ULP_ACT_HID_07cf] = 63,
+	[BNXT_ULP_ACT_HID_03fb] = 64,
+	[BNXT_ULP_ACT_HID_05fd] = 65,
+	[BNXT_ULP_ACT_HID_02e4] = 66,
+	[BNXT_ULP_ACT_HID_08ea] = 67,
+	[BNXT_ULP_ACT_HID_07d3] = 68,
+	[BNXT_ULP_ACT_HID_040d] = 69,
+	[BNXT_ULP_ACT_HID_040f] = 70,
+	[BNXT_ULP_ACT_HID_0413] = 71,
 	[BNXT_ULP_ACT_HID_0567] = 72,
 	[BNXT_ULP_ACT_HID_0a49] = 73,
 	[BNXT_ULP_ACT_HID_050e] = 74,
-	[BNXT_ULP_ACT_HID_0d0e] = 75,
-	[BNXT_ULP_ACT_HID_0668] = 76,
-	[BNXT_ULP_ACT_HID_0b4a] = 77,
-	[BNXT_ULP_ACT_HID_0411] = 78,
-	[BNXT_ULP_ACT_HID_056b] = 79,
-	[BNXT_ULP_ACT_HID_0a4d] = 80,
-	[BNXT_ULP_ACT_HID_0c11] = 81,
-	[BNXT_ULP_ACT_HID_0512] = 82,
-	[BNXT_ULP_ACT_HID_0d12] = 83,
-	[BNXT_ULP_ACT_HID_066c] = 84,
-	[BNXT_ULP_ACT_HID_0b4e] = 85
+	[BNXT_ULP_ACT_HID_0668] = 75,
+	[BNXT_ULP_ACT_HID_0b4a] = 76,
+	[BNXT_ULP_ACT_HID_0411] = 77,
+	[BNXT_ULP_ACT_HID_056b] = 78,
+	[BNXT_ULP_ACT_HID_0a4d] = 79,
+	[BNXT_ULP_ACT_HID_0512] = 80,
+	[BNXT_ULP_ACT_HID_066c] = 81,
+	[BNXT_ULP_ACT_HID_0b4e] = 82
 };
 
 struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
@@ -332,6 +329,13 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 2
 	},
 	[28] = {
+	.act_hid = BNXT_ULP_ACT_HID_0004,
+	.act_sig = { .bits =
+		BNXT_ULP_ACTION_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 2
+	},
+	[29] = {
 	.act_hid = BNXT_ULP_ACT_HID_0006,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -339,7 +343,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[29] = {
+	[30] = {
 	.act_hid = BNXT_ULP_ACT_HID_0804,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -347,7 +351,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[30] = {
+	[31] = {
 	.act_hid = BNXT_ULP_ACT_HID_0105,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -355,7 +359,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[31] = {
+	[32] = {
 	.act_hid = BNXT_ULP_ACT_HID_0024,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -363,7 +367,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[32] = {
+	[33] = {
 	.act_hid = BNXT_ULP_ACT_HID_0905,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -372,7 +376,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[33] = {
+	[34] = {
 	.act_hid = BNXT_ULP_ACT_HID_0125,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -381,14 +385,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
 	},
-	[34] = {
+	[35] = {
 	.act_hid = BNXT_ULP_ACT_HID_0001,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[35] = {
+	[36] = {
 	.act_hid = BNXT_ULP_ACT_HID_0005,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -396,7 +400,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[36] = {
+	[37] = {
 	.act_hid = BNXT_ULP_ACT_HID_0009,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -404,7 +408,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[37] = {
+	[38] = {
 	.act_hid = BNXT_ULP_ACT_HID_000d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -413,7 +417,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[38] = {
+	[39] = {
 	.act_hid = BNXT_ULP_ACT_HID_0021,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -421,7 +425,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[39] = {
+	[40] = {
 	.act_hid = BNXT_ULP_ACT_HID_0029,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -430,7 +434,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[40] = {
+	[41] = {
 	.act_hid = BNXT_ULP_ACT_HID_0025,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -439,7 +443,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[41] = {
+	[42] = {
 	.act_hid = BNXT_ULP_ACT_HID_002d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -449,7 +453,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[42] = {
+	[43] = {
 	.act_hid = BNXT_ULP_ACT_HID_0801,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -457,7 +461,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[43] = {
+	[44] = {
 	.act_hid = BNXT_ULP_ACT_HID_0809,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -466,7 +470,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[44] = {
+	[45] = {
 	.act_hid = BNXT_ULP_ACT_HID_0805,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -475,7 +479,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[45] = {
+	[46] = {
 	.act_hid = BNXT_ULP_ACT_HID_080d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_MARK |
@@ -485,14 +489,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[46] = {
+	[47] = {
 	.act_hid = BNXT_ULP_ACT_HID_0c15,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[47] = {
+	[48] = {
 	.act_hid = BNXT_ULP_ACT_HID_0c19,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
@@ -500,14 +504,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[48] = {
+	[49] = {
 	.act_hid = BNXT_ULP_ACT_HID_02f6,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[49] = {
+	[50] = {
 	.act_hid = BNXT_ULP_ACT_HID_04f8,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
@@ -515,14 +519,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[50] = {
+	[51] = {
 	.act_hid = BNXT_ULP_ACT_HID_01df,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[51] = {
+	[52] = {
 	.act_hid = BNXT_ULP_ACT_HID_07e5,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
@@ -531,7 +535,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[52] = {
+	[53] = {
 	.act_hid = BNXT_ULP_ACT_HID_06ce,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
@@ -541,7 +545,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[53] = {
+	[54] = {
 	.act_hid = BNXT_ULP_ACT_HID_02fa,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -549,7 +553,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[54] = {
+	[55] = {
 	.act_hid = BNXT_ULP_ACT_HID_04fc,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -558,7 +562,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[55] = {
+	[56] = {
 	.act_hid = BNXT_ULP_ACT_HID_01e3,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -566,7 +570,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[56] = {
+	[57] = {
 	.act_hid = BNXT_ULP_ACT_HID_07e9,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -576,7 +580,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[57] = {
+	[58] = {
 	.act_hid = BNXT_ULP_ACT_HID_06d2,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -587,7 +591,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[58] = {
+	[59] = {
 	.act_hid = BNXT_ULP_ACT_HID_03f7,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -595,7 +599,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[59] = {
+	[60] = {
 	.act_hid = BNXT_ULP_ACT_HID_05f9,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -604,7 +608,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[60] = {
+	[61] = {
 	.act_hid = BNXT_ULP_ACT_HID_02e0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -612,7 +616,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[61] = {
+	[62] = {
 	.act_hid = BNXT_ULP_ACT_HID_08e6,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -622,7 +626,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[62] = {
+	[63] = {
 	.act_hid = BNXT_ULP_ACT_HID_07cf,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -633,7 +637,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[63] = {
+	[64] = {
 	.act_hid = BNXT_ULP_ACT_HID_03fb,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -642,7 +646,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[64] = {
+	[65] = {
 	.act_hid = BNXT_ULP_ACT_HID_05fd,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -652,7 +656,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[65] = {
+	[66] = {
 	.act_hid = BNXT_ULP_ACT_HID_02e4,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -661,7 +665,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[66] = {
+	[67] = {
 	.act_hid = BNXT_ULP_ACT_HID_08ea,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -672,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[67] = {
+	[68] = {
 	.act_hid = BNXT_ULP_ACT_HID_07d3,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -684,20 +688,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[68] = {
+	[69] = {
 	.act_hid = BNXT_ULP_ACT_HID_040d,
 	.act_sig = { .bits =
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[69] = {
+	[70] = {
 	.act_hid = BNXT_ULP_ACT_HID_040f,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DROP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[70] = {
+	[71] = {
 	.act_hid = BNXT_ULP_ACT_HID_0413,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DROP |
@@ -705,13 +709,6 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[71] = {
-	.act_hid = BNXT_ULP_ACT_HID_0c0d,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
 	[72] = {
 	.act_hid = BNXT_ULP_ACT_HID_0567,
 	.act_sig = { .bits =
@@ -737,14 +734,6 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 6
 	},
 	[75] = {
-	.act_hid = BNXT_ULP_ACT_HID_0d0e,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_DEC_TTL |
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
-	[76] = {
 	.act_hid = BNXT_ULP_ACT_HID_0668,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -754,7 +743,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[77] = {
+	[76] = {
 	.act_hid = BNXT_ULP_ACT_HID_0b4a,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_DEC_TTL |
@@ -763,14 +752,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[78] = {
+	[77] = {
 	.act_hid = BNXT_ULP_ACT_HID_0411,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[79] = {
+	[78] = {
 	.act_hid = BNXT_ULP_ACT_HID_056b,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -780,7 +769,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[80] = {
+	[79] = {
 	.act_hid = BNXT_ULP_ACT_HID_0a4d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -789,15 +778,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[81] = {
-	.act_hid = BNXT_ULP_ACT_HID_0c11,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_COUNT |
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
-	[82] = {
+	[80] = {
 	.act_hid = BNXT_ULP_ACT_HID_0512,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -805,16 +786,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[83] = {
-	.act_hid = BNXT_ULP_ACT_HID_0d12,
-	.act_sig = { .bits =
-		BNXT_ULP_ACTION_BIT_COUNT |
-		BNXT_ULP_ACTION_BIT_DEC_TTL |
-		BNXT_ULP_ACTION_BIT_POP_VLAN |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
-	.act_tid = 6
-	},
-	[84] = {
+	[81] = {
 	.act_hid = BNXT_ULP_ACT_HID_066c,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -825,7 +797,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[85] = {
+	[82] = {
 	.act_hid = BNXT_ULP_ACT_HID_0b4e,
 	.act_sig = { .bits =
 		BNXT_ULP_ACTION_BIT_COUNT |
@@ -1064,7 +1036,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET,
@@ -1462,11 +1434,21 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {
-		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
+	.result_operand = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -2364,11 +2346,21 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {
-		BNXT_ULP_SYM_DECAP_FUNC_THRU_L2,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST,
+	.result_operand = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -2593,17 +2585,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT,
-	.result_operand = {
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index 1f650e0d7..3d133d2ff 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -11,36 +11,36 @@
 uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_CLASS_HID_0138] = 1,
 	[BNXT_ULP_CLASS_HID_03f0] = 2,
-	[BNXT_ULP_CLASS_HID_0134] = 3,
-	[BNXT_ULP_CLASS_HID_03fc] = 4,
-	[BNXT_ULP_CLASS_HID_0139] = 5,
-	[BNXT_ULP_CLASS_HID_03f1] = 6,
-	[BNXT_ULP_CLASS_HID_068b] = 7,
-	[BNXT_ULP_CLASS_HID_0143] = 8,
-	[BNXT_ULP_CLASS_HID_0135] = 9,
-	[BNXT_ULP_CLASS_HID_03fd] = 10,
-	[BNXT_ULP_CLASS_HID_0687] = 11,
-	[BNXT_ULP_CLASS_HID_014f] = 12,
-	[BNXT_ULP_CLASS_HID_0118] = 13,
-	[BNXT_ULP_CLASS_HID_03d0] = 14,
-	[BNXT_ULP_CLASS_HID_0114] = 15,
-	[BNXT_ULP_CLASS_HID_03dc] = 16,
-	[BNXT_ULP_CLASS_HID_0119] = 17,
-	[BNXT_ULP_CLASS_HID_03d1] = 18,
-	[BNXT_ULP_CLASS_HID_06ab] = 19,
-	[BNXT_ULP_CLASS_HID_0163] = 20,
-	[BNXT_ULP_CLASS_HID_0115] = 21,
-	[BNXT_ULP_CLASS_HID_03dd] = 22,
-	[BNXT_ULP_CLASS_HID_06a7] = 23,
-	[BNXT_ULP_CLASS_HID_016f] = 24,
-	[BNXT_ULP_CLASS_HID_0128] = 25,
-	[BNXT_ULP_CLASS_HID_03e0] = 26,
-	[BNXT_ULP_CLASS_HID_0124] = 27,
-	[BNXT_ULP_CLASS_HID_03ec] = 28,
-	[BNXT_ULP_CLASS_HID_0129] = 29,
-	[BNXT_ULP_CLASS_HID_03e1] = 30,
-	[BNXT_ULP_CLASS_HID_069b] = 31,
-	[BNXT_ULP_CLASS_HID_0153] = 32,
+	[BNXT_ULP_CLASS_HID_0139] = 3,
+	[BNXT_ULP_CLASS_HID_03f1] = 4,
+	[BNXT_ULP_CLASS_HID_068b] = 5,
+	[BNXT_ULP_CLASS_HID_0143] = 6,
+	[BNXT_ULP_CLASS_HID_0118] = 7,
+	[BNXT_ULP_CLASS_HID_03d0] = 8,
+	[BNXT_ULP_CLASS_HID_0119] = 9,
+	[BNXT_ULP_CLASS_HID_03d1] = 10,
+	[BNXT_ULP_CLASS_HID_06ab] = 11,
+	[BNXT_ULP_CLASS_HID_0163] = 12,
+	[BNXT_ULP_CLASS_HID_0128] = 13,
+	[BNXT_ULP_CLASS_HID_03e0] = 14,
+	[BNXT_ULP_CLASS_HID_0129] = 15,
+	[BNXT_ULP_CLASS_HID_03e1] = 16,
+	[BNXT_ULP_CLASS_HID_069b] = 17,
+	[BNXT_ULP_CLASS_HID_0153] = 18,
+	[BNXT_ULP_CLASS_HID_0134] = 19,
+	[BNXT_ULP_CLASS_HID_03fc] = 20,
+	[BNXT_ULP_CLASS_HID_0135] = 21,
+	[BNXT_ULP_CLASS_HID_03fd] = 22,
+	[BNXT_ULP_CLASS_HID_0687] = 23,
+	[BNXT_ULP_CLASS_HID_014f] = 24,
+	[BNXT_ULP_CLASS_HID_0114] = 25,
+	[BNXT_ULP_CLASS_HID_03dc] = 26,
+	[BNXT_ULP_CLASS_HID_0115] = 27,
+	[BNXT_ULP_CLASS_HID_03dd] = 28,
+	[BNXT_ULP_CLASS_HID_06a7] = 29,
+	[BNXT_ULP_CLASS_HID_016f] = 30,
+	[BNXT_ULP_CLASS_HID_0124] = 31,
+	[BNXT_ULP_CLASS_HID_03ec] = 32,
 	[BNXT_ULP_CLASS_HID_0125] = 33,
 	[BNXT_ULP_CLASS_HID_03ed] = 34,
 	[BNXT_ULP_CLASS_HID_0697] = 35,
@@ -153,36 +153,36 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_CLASS_HID_077f] = 142,
 	[BNXT_ULP_CLASS_HID_01e1] = 143,
 	[BNXT_ULP_CLASS_HID_0329] = 144,
-	[BNXT_ULP_CLASS_HID_01dd] = 145,
-	[BNXT_ULP_CLASS_HID_0315] = 146,
-	[BNXT_ULP_CLASS_HID_01c1] = 147,
-	[BNXT_ULP_CLASS_HID_0309] = 148,
-	[BNXT_ULP_CLASS_HID_003d] = 149,
-	[BNXT_ULP_CLASS_HID_02f5] = 150,
-	[BNXT_ULP_CLASS_HID_01d1] = 151,
-	[BNXT_ULP_CLASS_HID_0319] = 152,
-	[BNXT_ULP_CLASS_HID_01cd] = 153,
-	[BNXT_ULP_CLASS_HID_0305] = 154,
-	[BNXT_ULP_CLASS_HID_01e2] = 155,
-	[BNXT_ULP_CLASS_HID_032a] = 156,
-	[BNXT_ULP_CLASS_HID_0650] = 157,
-	[BNXT_ULP_CLASS_HID_0198] = 158,
-	[BNXT_ULP_CLASS_HID_01de] = 159,
-	[BNXT_ULP_CLASS_HID_0316] = 160,
-	[BNXT_ULP_CLASS_HID_066c] = 161,
-	[BNXT_ULP_CLASS_HID_01a4] = 162,
-	[BNXT_ULP_CLASS_HID_01c2] = 163,
-	[BNXT_ULP_CLASS_HID_030a] = 164,
-	[BNXT_ULP_CLASS_HID_0670] = 165,
-	[BNXT_ULP_CLASS_HID_01b8] = 166,
-	[BNXT_ULP_CLASS_HID_003e] = 167,
-	[BNXT_ULP_CLASS_HID_02f6] = 168,
-	[BNXT_ULP_CLASS_HID_078c] = 169,
-	[BNXT_ULP_CLASS_HID_0044] = 170,
-	[BNXT_ULP_CLASS_HID_01d2] = 171,
-	[BNXT_ULP_CLASS_HID_031a] = 172,
-	[BNXT_ULP_CLASS_HID_0660] = 173,
-	[BNXT_ULP_CLASS_HID_01a8] = 174,
+	[BNXT_ULP_CLASS_HID_01c1] = 145,
+	[BNXT_ULP_CLASS_HID_0309] = 146,
+	[BNXT_ULP_CLASS_HID_01d1] = 147,
+	[BNXT_ULP_CLASS_HID_0319] = 148,
+	[BNXT_ULP_CLASS_HID_01e2] = 149,
+	[BNXT_ULP_CLASS_HID_032a] = 150,
+	[BNXT_ULP_CLASS_HID_0650] = 151,
+	[BNXT_ULP_CLASS_HID_0198] = 152,
+	[BNXT_ULP_CLASS_HID_01c2] = 153,
+	[BNXT_ULP_CLASS_HID_030a] = 154,
+	[BNXT_ULP_CLASS_HID_0670] = 155,
+	[BNXT_ULP_CLASS_HID_01b8] = 156,
+	[BNXT_ULP_CLASS_HID_01d2] = 157,
+	[BNXT_ULP_CLASS_HID_031a] = 158,
+	[BNXT_ULP_CLASS_HID_0660] = 159,
+	[BNXT_ULP_CLASS_HID_01a8] = 160,
+	[BNXT_ULP_CLASS_HID_01dd] = 161,
+	[BNXT_ULP_CLASS_HID_0315] = 162,
+	[BNXT_ULP_CLASS_HID_003d] = 163,
+	[BNXT_ULP_CLASS_HID_02f5] = 164,
+	[BNXT_ULP_CLASS_HID_01cd] = 165,
+	[BNXT_ULP_CLASS_HID_0305] = 166,
+	[BNXT_ULP_CLASS_HID_01de] = 167,
+	[BNXT_ULP_CLASS_HID_0316] = 168,
+	[BNXT_ULP_CLASS_HID_066c] = 169,
+	[BNXT_ULP_CLASS_HID_01a4] = 170,
+	[BNXT_ULP_CLASS_HID_003e] = 171,
+	[BNXT_ULP_CLASS_HID_02f6] = 172,
+	[BNXT_ULP_CLASS_HID_078c] = 173,
+	[BNXT_ULP_CLASS_HID_0044] = 174,
 	[BNXT_ULP_CLASS_HID_01ce] = 175,
 	[BNXT_ULP_CLASS_HID_0306] = 176,
 	[BNXT_ULP_CLASS_HID_067c] = 177,
@@ -218,10 +218,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 1
 	},
 	[3] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0134,
+	.class_hid = BNXT_ULP_CLASS_HID_0139,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -232,10 +233,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 2
 	},
 	[4] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03fc,
+	.class_hid = BNXT_ULP_CLASS_HID_03f1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -245,7 +247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 3
 	},
 	[5] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0139,
+	.class_hid = BNXT_ULP_CLASS_HID_068b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
@@ -255,12 +257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 4
 	},
 	[6] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03f1,
+	.class_hid = BNXT_ULP_CLASS_HID_0143,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
@@ -269,47 +272,47 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 5
 	},
 	[7] = {
-	.class_hid = BNXT_ULP_CLASS_HID_068b,
+	.class_hid = BNXT_ULP_CLASS_HID_0118,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 6
 	},
 	[8] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0143,
+	.class_hid = BNXT_ULP_CLASS_HID_03d0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 7
 	},
 	[9] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0135,
+	.class_hid = BNXT_ULP_CLASS_HID_0119,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -320,11 +323,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 8
 	},
 	[10] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03fd,
+	.class_hid = BNXT_ULP_CLASS_HID_03d1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -334,11 +338,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 9
 	},
 	[11] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0687,
+	.class_hid = BNXT_ULP_CLASS_HID_06ab,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -350,11 +355,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 10
 	},
 	[12] = {
-	.class_hid = BNXT_ULP_CLASS_HID_014f,
+	.class_hid = BNXT_ULP_CLASS_HID_0163,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -365,11 +371,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 11
 	},
 	[13] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0118,
+	.class_hid = BNXT_ULP_CLASS_HID_0128,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -380,11 +386,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 12
 	},
 	[14] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03d0,
+	.class_hid = BNXT_ULP_CLASS_HID_03e0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -394,11 +400,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 13
 	},
 	[15] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0114,
+	.class_hid = BNXT_ULP_CLASS_HID_0129,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -409,11 +416,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 14
 	},
 	[16] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03dc,
+	.class_hid = BNXT_ULP_CLASS_HID_03e1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
@@ -423,254 +431,246 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 15
 	},
 	[17] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0119,
+	.class_hid = BNXT_ULP_CLASS_HID_069b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 16
 	},
 	[18] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03d1,
+	.class_hid = BNXT_ULP_CLASS_HID_0153,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 6,
 	.wc_pri = 17
 	},
 	[19] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06ab,
+	.class_hid = BNXT_ULP_CLASS_HID_0134,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 18
+	.class_tid = 7,
+	.wc_pri = 0
 	},
 	[20] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0163,
+	.class_hid = BNXT_ULP_CLASS_HID_03fc,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 19
+	.class_tid = 7,
+	.wc_pri = 1
 	},
 	[21] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0115,
+	.class_hid = BNXT_ULP_CLASS_HID_0135,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 20
+	.class_tid = 7,
+	.wc_pri = 2
 	},
 	[22] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03dd,
+	.class_hid = BNXT_ULP_CLASS_HID_03fd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 21
+	.class_tid = 7,
+	.wc_pri = 3
 	},
 	[23] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06a7,
+	.class_hid = BNXT_ULP_CLASS_HID_0687,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 22
+	.class_tid = 7,
+	.wc_pri = 4
 	},
 	[24] = {
-	.class_hid = BNXT_ULP_CLASS_HID_016f,
+	.class_hid = BNXT_ULP_CLASS_HID_014f,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 23
+	.class_tid = 7,
+	.wc_pri = 5
 	},
 	[25] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0128,
+	.class_hid = BNXT_ULP_CLASS_HID_0114,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 24
+	.class_tid = 7,
+	.wc_pri = 6
 	},
 	[26] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03e0,
+	.class_hid = BNXT_ULP_CLASS_HID_03dc,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 25
+	.class_tid = 7,
+	.wc_pri = 7
 	},
 	[27] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0124,
+	.class_hid = BNXT_ULP_CLASS_HID_0115,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 26
+	.class_tid = 7,
+	.wc_pri = 8
 	},
 	[28] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03ec,
+	.class_hid = BNXT_ULP_CLASS_HID_03dd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 27
+	.class_tid = 7,
+	.wc_pri = 9
 	},
 	[29] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0129,
+	.class_hid = BNXT_ULP_CLASS_HID_06a7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 28
+	.class_tid = 7,
+	.wc_pri = 10
 	},
 	[30] = {
-	.class_hid = BNXT_ULP_CLASS_HID_03e1,
+	.class_hid = BNXT_ULP_CLASS_HID_016f,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 29
+	.class_tid = 7,
+	.wc_pri = 11
 	},
 	[31] = {
-	.class_hid = BNXT_ULP_CLASS_HID_069b,
+	.class_hid = BNXT_ULP_CLASS_HID_0124,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 30
+	.class_tid = 7,
+	.wc_pri = 12
 	},
 	[32] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0153,
+	.class_hid = BNXT_ULP_CLASS_HID_03ec,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 31
+	.class_tid = 7,
+	.wc_pri = 13
 	},
 	[33] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0125,
@@ -681,12 +681,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 32
+	.class_tid = 7,
+	.wc_pri = 14
 	},
 	[34] = {
 	.class_hid = BNXT_ULP_CLASS_HID_03ed,
@@ -697,11 +697,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 33
+	.class_tid = 7,
+	.wc_pri = 15
 	},
 	[35] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0697,
@@ -712,13 +712,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 34
+	.class_tid = 7,
+	.wc_pri = 16
 	},
 	[36] = {
 	.class_hid = BNXT_ULP_CLASS_HID_015f,
@@ -729,12 +729,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF6_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF7_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 6,
-	.wc_pri = 35
+	.class_tid = 7,
+	.wc_pri = 17
 	},
 	[37] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0452,
@@ -744,14 +744,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 0
 	},
 	[38] = {
@@ -762,13 +762,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 1
 	},
 	[39] = {
@@ -779,13 +779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 2
 	},
 	[40] = {
@@ -796,12 +796,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 7,
+	.class_tid = 8,
 	.wc_pri = 3
 	},
 	[41] = {
@@ -812,14 +812,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 0
 	},
 	[42] = {
@@ -830,13 +830,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 1
 	},
 	[43] = {
@@ -847,13 +847,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 2
 	},
 	[44] = {
@@ -864,12 +864,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 8,
+	.class_tid = 9,
 	.wc_pri = 3
 	},
 	[45] = {
@@ -880,14 +880,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 0
 	},
 	[46] = {
@@ -898,13 +898,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 1
 	},
 	[47] = {
@@ -915,13 +915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 2
 	},
 	[48] = {
@@ -932,12 +932,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 9,
+	.class_tid = 10,
 	.wc_pri = 3
 	},
 	[49] = {
@@ -948,14 +948,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 0
 	},
 	[50] = {
@@ -966,13 +966,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 1
 	},
 	[51] = {
@@ -983,13 +983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 2
 	},
 	[52] = {
@@ -1000,12 +1000,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 10,
+	.class_tid = 11,
 	.wc_pri = 3
 	},
 	[53] = {
@@ -1016,15 +1016,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 0
 	},
 	[54] = {
@@ -1035,14 +1035,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 1
 	},
 	[55] = {
@@ -1053,14 +1053,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 2
 	},
 	[56] = {
@@ -1071,13 +1071,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 3
 	},
 	[57] = {
@@ -1089,16 +1089,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 4
 	},
 	[58] = {
@@ -1110,15 +1110,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 5
 	},
 	[59] = {
@@ -1130,15 +1130,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 6
 	},
 	[60] = {
@@ -1150,14 +1150,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 7
 	},
 	[61] = {
@@ -1169,15 +1169,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 8
 	},
 	[62] = {
@@ -1189,14 +1189,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 9
 	},
 	[63] = {
@@ -1208,14 +1208,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 10
 	},
 	[64] = {
@@ -1227,13 +1227,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF11_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 11,
+	.class_tid = 12,
 	.wc_pri = 11
 	},
 	[65] = {
@@ -1244,15 +1244,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 0
 	},
 	[66] = {
@@ -1263,14 +1263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 1
 	},
 	[67] = {
@@ -1281,14 +1281,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 2
 	},
 	[68] = {
@@ -1299,13 +1299,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 3
 	},
 	[69] = {
@@ -1317,16 +1317,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 4
 	},
 	[70] = {
@@ -1338,15 +1338,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 5
 	},
 	[71] = {
@@ -1358,15 +1358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 6
 	},
 	[72] = {
@@ -1378,14 +1378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 7
 	},
 	[73] = {
@@ -1397,15 +1397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 8
 	},
 	[74] = {
@@ -1417,14 +1417,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 9
 	},
 	[75] = {
@@ -1436,14 +1436,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 10
 	},
 	[76] = {
@@ -1455,13 +1455,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF12_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 12,
+	.class_tid = 13,
 	.wc_pri = 11
 	},
 	[77] = {
@@ -1472,15 +1472,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 0
 	},
 	[78] = {
@@ -1491,14 +1491,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 1
 	},
 	[79] = {
@@ -1509,14 +1509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 2
 	},
 	[80] = {
@@ -1527,13 +1527,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 3
 	},
 	[81] = {
@@ -1545,16 +1545,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 4
 	},
 	[82] = {
@@ -1566,15 +1566,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 5
 	},
 	[83] = {
@@ -1586,15 +1586,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 6
 	},
 	[84] = {
@@ -1606,14 +1606,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 7
 	},
 	[85] = {
@@ -1625,15 +1625,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 8
 	},
 	[86] = {
@@ -1645,14 +1645,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 9
 	},
 	[87] = {
@@ -1664,14 +1664,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 10
 	},
 	[88] = {
@@ -1683,13 +1683,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF13_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 13,
+	.class_tid = 14,
 	.wc_pri = 11
 	},
 	[89] = {
@@ -1700,15 +1700,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 0
 	},
 	[90] = {
@@ -1719,14 +1719,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 1
 	},
 	[91] = {
@@ -1737,14 +1737,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 2
 	},
 	[92] = {
@@ -1755,13 +1755,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 3
 	},
 	[93] = {
@@ -1773,16 +1773,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 4
 	},
 	[94] = {
@@ -1794,15 +1794,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 5
 	},
 	[95] = {
@@ -1814,15 +1814,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 6
 	},
 	[96] = {
@@ -1834,14 +1834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 7
 	},
 	[97] = {
@@ -1853,15 +1853,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 8
 	},
 	[98] = {
@@ -1873,14 +1873,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 9
 	},
 	[99] = {
@@ -1892,14 +1892,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 10
 	},
 	[100] = {
@@ -1911,13 +1911,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF14_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 14,
+	.class_tid = 15,
 	.wc_pri = 11
 	},
 	[101] = {
@@ -1932,19 +1932,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_I_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF15_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF15_BITMASK_I_ETH_TYPE |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT |
-		BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF16_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
+		BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 15,
+	.class_tid = 16,
 	.wc_pri = 0
 	},
 	[102] = {
@@ -1959,17 +1959,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_I_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF15_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR |
-		BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID |
-		BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT |
-		BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
+		BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 15,
+	.class_tid = 16,
 	.wc_pri = 1
 	},
 	[103] = {
@@ -1981,14 +1981,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 0
 	},
 	[104] = {
@@ -2000,13 +2000,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 1
 	},
 	[105] = {
@@ -2018,13 +2018,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 2
 	},
 	[106] = {
@@ -2036,12 +2036,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 3
 	},
 	[107] = {
@@ -2053,13 +2053,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 4
 	},
 	[108] = {
@@ -2071,12 +2071,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 5
 	},
 	[109] = {
@@ -2088,12 +2088,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 6
 	},
 	[110] = {
@@ -2105,11 +2105,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 7
 	},
 	[111] = {
@@ -2122,15 +2122,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 8
 	},
 	[112] = {
@@ -2143,14 +2143,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 9
 	},
 	[113] = {
@@ -2163,14 +2163,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 10
 	},
 	[114] = {
@@ -2183,13 +2183,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 11
 	},
 	[115] = {
@@ -2202,14 +2202,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 12
 	},
 	[116] = {
@@ -2222,13 +2222,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 13
 	},
 	[117] = {
@@ -2241,13 +2241,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 14
 	},
 	[118] = {
@@ -2260,12 +2260,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 15
 	},
 	[119] = {
@@ -2278,14 +2278,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 16
 	},
 	[120] = {
@@ -2298,13 +2298,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 17
 	},
 	[121] = {
@@ -2317,13 +2317,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 18
 	},
 	[122] = {
@@ -2336,12 +2336,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 19
 	},
 	[123] = {
@@ -2354,13 +2354,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 20
 	},
 	[124] = {
@@ -2373,12 +2373,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 21
 	},
 	[125] = {
@@ -2391,12 +2391,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 22
 	},
 	[126] = {
@@ -2409,11 +2409,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 16,
+	.class_tid = 17,
 	.wc_pri = 23
 	},
 	[127] = {
@@ -2424,14 +2424,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 0
 	},
 	[128] = {
@@ -2442,13 +2442,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 1
 	},
 	[129] = {
@@ -2459,13 +2459,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 2
 	},
 	[130] = {
@@ -2476,12 +2476,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 17,
+	.class_tid = 18,
 	.wc_pri = 3
 	},
 	[131] = {
@@ -2492,14 +2492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 0
 	},
 	[132] = {
@@ -2510,13 +2510,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 1
 	},
 	[133] = {
@@ -2527,13 +2527,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 2
 	},
 	[134] = {
@@ -2544,12 +2544,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 18,
+	.class_tid = 19,
 	.wc_pri = 3
 	},
 	[135] = {
@@ -2560,14 +2560,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 0
 	},
 	[136] = {
@@ -2578,13 +2578,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 1
 	},
 	[137] = {
@@ -2595,13 +2595,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 2
 	},
 	[138] = {
@@ -2612,12 +2612,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 19,
+	.class_tid = 20,
 	.wc_pri = 3
 	},
 	[139] = {
@@ -2628,14 +2628,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 0
 	},
 	[140] = {
@@ -2646,13 +2646,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 1
 	},
 	[141] = {
@@ -2663,13 +2663,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 2
 	},
 	[142] = {
@@ -2680,12 +2680,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 20,
+	.class_tid = 21,
 	.wc_pri = 3
 	},
 	[143] = {
@@ -2695,11 +2695,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 0
 	},
 	[144] = {
@@ -2709,466 +2709,466 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 1
 	},
 	[145] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01dd,
+	.class_hid = BNXT_ULP_CLASS_HID_01c1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 2
 	},
 	[146] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0315,
+	.class_hid = BNXT_ULP_CLASS_HID_0309,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 3
 	},
 	[147] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01c1,
+	.class_hid = BNXT_ULP_CLASS_HID_01d1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 4
 	},
 	[148] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0309,
+	.class_hid = BNXT_ULP_CLASS_HID_0319,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 5
 	},
 	[149] = {
-	.class_hid = BNXT_ULP_CLASS_HID_003d,
+	.class_hid = BNXT_ULP_CLASS_HID_01e2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 6
 	},
 	[150] = {
-	.class_hid = BNXT_ULP_CLASS_HID_02f5,
+	.class_hid = BNXT_ULP_CLASS_HID_032a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 7
 	},
 	[151] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01d1,
+	.class_hid = BNXT_ULP_CLASS_HID_0650,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 8
 	},
 	[152] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0319,
+	.class_hid = BNXT_ULP_CLASS_HID_0198,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 9
 	},
 	[153] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01cd,
+	.class_hid = BNXT_ULP_CLASS_HID_01c2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 10
 	},
 	[154] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0305,
+	.class_hid = BNXT_ULP_CLASS_HID_030a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 11
 	},
 	[155] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01e2,
+	.class_hid = BNXT_ULP_CLASS_HID_0670,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 12
 	},
 	[156] = {
-	.class_hid = BNXT_ULP_CLASS_HID_032a,
+	.class_hid = BNXT_ULP_CLASS_HID_01b8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 13
 	},
 	[157] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0650,
+	.class_hid = BNXT_ULP_CLASS_HID_01d2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 14
 	},
 	[158] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0198,
+	.class_hid = BNXT_ULP_CLASS_HID_031a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 15
 	},
 	[159] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01de,
+	.class_hid = BNXT_ULP_CLASS_HID_0660,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 16
 	},
 	[160] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0316,
+	.class_hid = BNXT_ULP_CLASS_HID_01a8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
+	.class_tid = 22,
 	.wc_pri = 17
 	},
 	[161] = {
-	.class_hid = BNXT_ULP_CLASS_HID_066c,
+	.class_hid = BNXT_ULP_CLASS_HID_01dd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 18
+	.class_tid = 23,
+	.wc_pri = 0
 	},
 	[162] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01a4,
+	.class_hid = BNXT_ULP_CLASS_HID_0315,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 19
+	.class_tid = 23,
+	.wc_pri = 1
 	},
 	[163] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01c2,
+	.class_hid = BNXT_ULP_CLASS_HID_003d,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 20
+	.class_tid = 23,
+	.wc_pri = 2
 	},
 	[164] = {
-	.class_hid = BNXT_ULP_CLASS_HID_030a,
+	.class_hid = BNXT_ULP_CLASS_HID_02f5,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 21
+	.class_tid = 23,
+	.wc_pri = 3
 	},
 	[165] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0670,
+	.class_hid = BNXT_ULP_CLASS_HID_01cd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 22
+	.class_tid = 23,
+	.wc_pri = 4
 	},
 	[166] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01b8,
+	.class_hid = BNXT_ULP_CLASS_HID_0305,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 23
+	.class_tid = 23,
+	.wc_pri = 5
 	},
 	[167] = {
-	.class_hid = BNXT_ULP_CLASS_HID_003e,
+	.class_hid = BNXT_ULP_CLASS_HID_01de,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 24
+	.class_tid = 23,
+	.wc_pri = 6
 	},
 	[168] = {
-	.class_hid = BNXT_ULP_CLASS_HID_02f6,
+	.class_hid = BNXT_ULP_CLASS_HID_0316,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 25
+	.class_tid = 23,
+	.wc_pri = 7
 	},
 	[169] = {
-	.class_hid = BNXT_ULP_CLASS_HID_078c,
+	.class_hid = BNXT_ULP_CLASS_HID_066c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 26
+	.class_tid = 23,
+	.wc_pri = 8
 	},
 	[170] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0044,
+	.class_hid = BNXT_ULP_CLASS_HID_01a4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 27
+	.class_tid = 23,
+	.wc_pri = 9
 	},
 	[171] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01d2,
+	.class_hid = BNXT_ULP_CLASS_HID_003e,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 28
+	.class_tid = 23,
+	.wc_pri = 10
 	},
 	[172] = {
-	.class_hid = BNXT_ULP_CLASS_HID_031a,
+	.class_hid = BNXT_ULP_CLASS_HID_02f6,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 29
+	.class_tid = 23,
+	.wc_pri = 11
 	},
 	[173] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0660,
+	.class_hid = BNXT_ULP_CLASS_HID_078c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 30
+	.class_tid = 23,
+	.wc_pri = 12
 	},
 	[174] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01a8,
+	.class_hid = BNXT_ULP_CLASS_HID_0044,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 31
+	.class_tid = 23,
+	.wc_pri = 13
 	},
 	[175] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01ce,
@@ -3179,12 +3179,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 32
+	.class_tid = 23,
+	.wc_pri = 14
 	},
 	[176] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0306,
@@ -3195,11 +3195,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 33
+	.class_tid = 23,
+	.wc_pri = 15
 	},
 	[177] = {
 	.class_hid = BNXT_ULP_CLASS_HID_067c,
@@ -3210,13 +3210,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 34
+	.class_tid = 23,
+	.wc_pri = 16
 	},
 	[178] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b4,
@@ -3227,12 +3227,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF21_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF21_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 21,
-	.wc_pri = 35
+	.class_tid = 23,
+	.wc_pri = 17
 	}
 };
 
@@ -3282,7 +3282,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 	[((7 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 5,
+	.num_tbls = 4,
 	.start_tbl_idx = 32,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
@@ -3290,28 +3290,28 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 37,
+	.start_tbl_idx = 36,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((9 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 42,
+	.start_tbl_idx = 41,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((10 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 47,
+	.start_tbl_idx = 46,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((11 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 4,
-	.start_tbl_idx = 52,
+	.num_tbls = 5,
+	.start_tbl_idx = 51,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((12 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
@@ -3352,7 +3352,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 	[((17 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 5,
+	.num_tbls = 4,
 	.start_tbl_idx = 76,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
@@ -3360,28 +3360,42 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 81,
+	.start_tbl_idx = 80,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((19 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 86,
+	.start_tbl_idx = 85,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((20 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 91,
+	.start_tbl_idx = 90,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((21 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 5,
+	.start_tbl_idx = 95,
+	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
+	},
+	[((22 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 4,
+	.start_tbl_idx = 100,
+	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
+	},
+	[((23 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 96,
+	.start_tbl_idx = 104,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	}
 };
@@ -3580,7 +3594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+	.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_TX,
@@ -3883,38 +3897,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.key_start_idx = 177,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
 	.result_start_idx = 315,
-	.result_bit_size = 10,
-	.result_num_fields = 1,
-	.encap_num_fields = 0,
-	.ident_start_idx = 5,
-	.ident_nums = 1
-	},
-	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 178,
-	.blob_key_bit_size = 167,
-	.key_bit_size = 167,
-	.key_num_fields = 13,
-	.result_start_idx = 316,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 6,
-	.ident_nums = 0,
+	.ident_start_idx = 5,
+	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -3924,11 +3921,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 191,
+	.key_start_idx = 190,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 329,
+	.result_start_idx = 328,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3939,13 +3936,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 194,
+	.key_start_idx = 193,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 330,
+	.result_start_idx = 329,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -3958,11 +3955,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 236,
+	.key_start_idx = 235,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 338,
+	.result_start_idx = 337,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -3977,11 +3974,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 247,
+	.key_start_idx = 246,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 347,
+	.result_start_idx = 346,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3994,11 +3991,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 248,
+	.key_start_idx = 247,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 348,
+	.result_start_idx = 347,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4013,11 +4010,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 261,
+	.key_start_idx = 260,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 361,
+	.result_start_idx = 360,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4030,11 +4027,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 264,
+	.key_start_idx = 263,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 362,
+	.result_start_idx = 361,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4047,11 +4044,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 306,
+	.key_start_idx = 305,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 370,
+	.result_start_idx = 369,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4066,11 +4063,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 317,
+	.key_start_idx = 316,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 379,
+	.result_start_idx = 378,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4083,11 +4080,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 318,
+	.key_start_idx = 317,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 380,
+	.result_start_idx = 379,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4102,11 +4099,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 331,
+	.key_start_idx = 330,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 393,
+	.result_start_idx = 392,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4119,11 +4116,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 334,
+	.key_start_idx = 333,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 394,
+	.result_start_idx = 393,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4136,11 +4133,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 376,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.key_start_idx = 375,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 402,
+	.result_start_idx = 401,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4155,11 +4152,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 387,
+	.key_start_idx = 386,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 411,
+	.result_start_idx = 410,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4172,11 +4169,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 388,
+	.key_start_idx = 387,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 412,
+	.result_start_idx = 411,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4191,11 +4188,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 401,
+	.key_start_idx = 400,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 425,
+	.result_start_idx = 424,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4208,11 +4205,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 404,
+	.key_start_idx = 403,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 426,
+	.result_start_idx = 425,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4225,11 +4222,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 446,
+	.key_start_idx = 445,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 434,
+	.result_start_idx = 433,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4239,11 +4236,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 456,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 442,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 13,
+	.ident_nums = 1
+	},
+	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.key_start_idx = 457,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -4252,8 +4266,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 13,
-	.ident_nums = 1,
+	.ident_start_idx = 14,
+	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -4298,8 +4312,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 515,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 465,
 	.result_bit_size = 64,
@@ -4514,8 +4528,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 722,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 558,
 	.result_bit_size = 64,
@@ -4531,7 +4545,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.key_start_idx = 733,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -4586,8 +4600,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 791,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 589,
 	.result_bit_size = 64,
@@ -4603,7 +4617,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.key_start_idx = 802,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -4671,38 +4685,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 871,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
-	.result_start_idx = 629,
-	.result_bit_size = 10,
-	.result_num_fields = 1,
-	.encap_num_fields = 0,
-	.ident_start_idx = 25,
-	.ident_nums = 1
-	},
-	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_TX,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 872,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.key_start_idx = 871,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 630,
+	.result_start_idx = 629,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 26,
-	.ident_nums = 0,
+	.ident_start_idx = 25,
+	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -4711,12 +4708,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 885,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 884,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 643,
+	.result_start_idx = 642,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4726,14 +4723,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-	.direction = TF_DIR_TX,
+	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 888,
+	.key_start_idx = 887,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 644,
+	.result_start_idx = 643,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4745,12 +4742,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 930,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 929,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 652,
+	.result_start_idx = 651,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4765,11 +4762,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 941,
+	.key_start_idx = 940,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 661,
+	.result_start_idx = 660,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4782,11 +4779,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 942,
+	.key_start_idx = 941,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 662,
+	.result_start_idx = 661,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4801,11 +4798,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 955,
+	.key_start_idx = 954,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 675,
+	.result_start_idx = 674,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4818,11 +4815,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 958,
+	.key_start_idx = 957,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 676,
+	.result_start_idx = 675,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4835,11 +4832,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1000,
+	.key_start_idx = 999,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 684,
+	.result_start_idx = 683,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4854,11 +4851,11 @@ st