From: "Chautru, Nicolas" <nicolas.chautru@intel.com> To: "Xu, Rosen" <rosen.xu@intel.com>, "dev@dpdk.org" <dev@dpdk.org>, "akhil.goyal@nxp.com" <akhil.goyal@nxp.com> Cc: "Richardson, Bruce" <bruce.richardson@intel.com> Subject: Re: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add queue configuration Date: Tue, 14 Apr 2020 00:16:22 +0000 Message-ID: <1183128033837D43A851F70F33ED5C576EFEAB6B@FMSMSX109.amr.corp.intel.com> (raw) In-Reply-To: <0E78D399C70DA940A335608C6ED296D73AEF8ECE@SHSMSX104.ccr.corp.intel.com> Thanks Rosen for your thorough code review. Some comments in-line below. > From: Xu, Rosen <rosen.xu@intel.com> > > Hi, > > Could you prefix all functions name with the FPGA IP name? FPGA is a very > common device name. > I don't see such a guideline being used across all other PMDs. Unsure it always help notably as this would create many long function names with fpga_5gnr_fec_ added each time, and these names are not exposed outside of this .c file. Also some of the fpga_ prefixes would apply for either fpga_lte_fec or fpga_5gnr_fec PMD. If this becomes of a new guide lines we can rename every single function in each existing baseband PMD in future release (not just this new PMD). > > /* Read a register of FPGA 5GNR FEC device */ static uint32_t > > fpga_reg_read_32(void *mmio_base, uint32_t offset) @@ -31,9 +106,115 > > @@ > > return rte_le_to_cpu_32(ret); > > } > > Why you didn't use rte_writeXXX() API of DPDK rte library? > rte_write32 includes some memory barriers which are not required here. Also we handle the byte endianness in these internal implementations. Thanks, Nic
next prev parent reply other threads:[~2020-04-14 0:16 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-30 0:02 [dpdk-dev] [PATCH v2 00/13] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 01/13] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 02/13] bbdev: expose device HARQ buffer size at device level Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 03/13] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 04/13] baseband/fpga_5gnr_fec: add register definition file Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 05/13] baseband/fpga_5gnr_fec: add device info_get function Nicolas Chautru 2020-04-16 18:15 ` Akhil Goyal 2020-04-16 21:20 ` Chautru, Nicolas 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add queue configuration Nicolas Chautru 2020-04-11 3:13 ` Xu, Rosen 2020-04-14 0:16 ` Chautru, Nicolas [this message] 2020-04-15 6:13 ` Xu, Rosen 2020-04-15 15:51 ` Chautru, Nicolas 2020-04-16 1:09 ` Xu, Rosen 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 07/13] baseband/fpga_5gnr_fec: add LDPC processing functions Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 08/13] baseband/fpga_5gnr_fec: add HW error capture Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 09/13] baseband/fpga_5gnr_fec: add debug functionality Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 10/13] baseband/fpga_5gnr_fec: add configure function Nicolas Chautru 2020-04-15 15:40 ` Power, Niall 2020-04-16 19:30 ` Akhil Goyal 2020-04-16 21:45 ` Chautru, Nicolas 2020-05-01 23:15 ` Chautru, Nicolas 2020-05-04 17:19 ` Thomas Monjalon 2020-06-25 0:30 ` Chautru, Nicolas 2020-06-25 8:13 ` Thomas Monjalon 2020-06-26 1:14 ` Chautru, Nicolas 2020-06-26 10:08 ` Thomas Monjalon 2020-07-10 22:48 ` Chautru, Nicolas 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 11/13] baseband/fpga_5gnr_fec: add harq loopback capability Nicolas Chautru 2020-03-30 0:02 ` [dpdk-dev] [PATCH v2 12/13] baseband/fpga_5gnr_fec: add interrupt support Nicolas Chautru 2020-04-16 18:43 ` Akhil Goyal 2020-03-30 0:03 ` [dpdk-dev] [PATCH v2 13/13] doc: add feature matrix table for bbdev devices Nicolas Chautru 2020-04-15 15:40 ` [dpdk-dev] [PATCH v2 00/13] drivers/baseband: add PMD for FPGA 5GNR FEC Power, Niall
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