From: "Chautru, Nicolas" <nicolas.chautru@intel.com>
To: Maxime Coquelin <maxime.coquelin@redhat.com>,
"Vargas, Hernan" <hernan.vargas@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>,
"gakhil@marvell.com" <gakhil@marvell.com>,
"trix@redhat.com" <trix@redhat.com>
Cc: "Zhang, Qi Z" <qi.z.zhang@intel.com>
Subject: RE: [PATCH v2 13/37] baseband/acc10x: limit cases for HARQ pruning
Date: Fri, 16 Sep 2022 00:31:58 +0000 [thread overview]
Message-ID: <BY5PR11MB445116E0ED25E02F0B89259EF8489@BY5PR11MB4451.namprd11.prod.outlook.com> (raw)
In-Reply-To: <ba60415d-b8dd-f992-1441-460a39c8e890@redhat.com>
Hi Maxime,
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Thursday, September 15, 2022 12:37 AM
> To: Vargas, Hernan <hernan.vargas@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: Chautru, Nicolas <nicolas.chautru@intel.com>; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: Re: [PATCH v2 13/37] baseband/acc10x: limit cases for HARQ
> pruning
>
>
>
> On 8/20/22 04:31, Hernan Vargas wrote:
> > Add flag ACC101_HARQ_PRUNING_OPTIMIZATION to limit cases when
> HARQ
> > pruning is valid.
> >
> > Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> > ---
> > drivers/baseband/acc100/rte_acc100_pmd.c | 52
> +++++++++++++++++++-----
> > 1 file changed, 41 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index 81bae4d695..e47f7d68c2 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -1370,17 +1370,23 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op
> *op, struct acc100_fcw_ld *fcw,
> > harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
> > #ifdef ACC100_EXT_MEM
> > /* Limit cases when HARQ pruning is valid */
> > +#ifdef ACC100_HARQ_PRUNING_OPTIMIZATION
> > harq_prun = ((op->ldpc_dec.harq_combined_output.offset %
> > - ACC100_HARQ_OFFSET) == 0) &&
> > - (op->ldpc_dec.harq_combined_output.offset <=
> UINT16_MAX
> > - * ACC100_HARQ_OFFSET);
> > + ACC100_HARQ_OFFSET) == 0);
> > +#endif
>
> Optimizations should not be put under #ifdefs, it will become a testing hell
> otherwise. CI will have to run as many builds as there are possible
> combinations, which is not sustainable.
>
> Even if not part of this patch, the "#ifdef ACC100_EXT_MEM" should also be
> removed.
With regards to the ACC100_EXT_MEM, this compilation switch is to be able to use the device using standard memory (not the dedicated one on the card).
I believe there is value notably for debug purpose for user to be able to rebuild with different capability (more like a DEBUG purpose). I understand that only the default value is being built by default.
As you pointed out this is not related to that patchset.
>
> > #endif
> > if (fcw->hcin_en > 0) {
> > harq_in_length = op->ldpc_dec.harq_combined_input.length;
> > if (fcw->hcin_decomp_mode > 0)
> > harq_in_length = harq_in_length * 8 / 6;
> > - harq_in_length = RTE_ALIGN(harq_in_length, 64);
> > - if ((harq_layout[harq_index].offset > 0) & harq_prun) {
> > + harq_in_length = RTE_MIN(harq_in_length, op-
> >ldpc_dec.n_cb
> > + - op->ldpc_dec.n_filler);
> > + /* Alignment on next 64B - Already enforced from HC output
> */
> > + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> > + /* Stronger alignment requirement when in decompression
> mode */
> > + if (fcw->hcin_decomp_mode > 0)
> > + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length,
> 256);
> > + if ((harq_layout[harq_index].offset > 0) && harq_prun) {
> > rte_bbdev_log_debug("HARQ IN offset unexpected
> for now\n");
> > fcw->hcin_size0 = harq_layout[harq_index].size0;
> > fcw->hcin_offset = harq_layout[harq_index].offset;
> @@ -1455,6
> > +1461,7 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct
> acc100_fcw_ld *fcw,
> > uint16_t harq_out_length, harq_in_length, ncb_p, k0_p,
> parity_offset;
> > uint32_t harq_index;
> > uint32_t l;
> > + bool harq_prun = false;
> >
> > fcw->qm = op->ldpc_dec.q_m;
> > fcw->nfiller = op->ldpc_dec.n_filler; @@ -1500,6 +1507,13 @@
> > acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld
> *fcw,
> > fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
> > RTE_BBDEV_LDPC_LLR_COMPRESSION);
> > harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
> > + #ifdef ACC100_EXT_MEM
> > + /* Limit cases when HARQ pruning is valid */ #ifdef
> > +ACC101_HARQ_PRUNING_OPTIMIZATION
> > + harq_prun = ((op->ldpc_dec.harq_combined_output.offset %
> > + ACC101_HARQ_OFFSET) == 0);
> > +#endif
> > +#endif
> > if (fcw->hcin_en > 0) {
> > harq_in_length = op->ldpc_dec.harq_combined_input.length;
> > if (fcw->hcin_decomp_mode > 0)
> > @@ -1508,9 +1522,17 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op
> *op, struct acc100_fcw_ld *fcw,
> > - op->ldpc_dec.n_filler);
> > /* Alignment on next 64B - Already enforced from HC output
> */
> > harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> > - fcw->hcin_size0 = harq_in_length;
> > - fcw->hcin_offset = 0;
> > - fcw->hcin_size1 = 0;
> > + if ((harq_layout[harq_index].offset > 0) && harq_prun) {
> > + rte_bbdev_log_debug("HARQ IN offset unexpected
> for now\n");
> > + fcw->hcin_size0 = harq_layout[harq_index].size0;
> > + fcw->hcin_offset = harq_layout[harq_index].offset;
> > + fcw->hcin_size1 = harq_in_length -
> > + harq_layout[harq_index].offset;
> > + } else {
> > + fcw->hcin_size0 = harq_in_length;
> > + fcw->hcin_offset = 0;
> > + fcw->hcin_size1 = 0;
> > + }
> > } else {
> > fcw->hcin_size0 = 0;
> > fcw->hcin_offset = 0;
> > @@ -1551,9 +1573,17 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op
> *op, struct acc100_fcw_ld *fcw,
> > harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> > /* Alignment on next 64B */
> > harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> > - fcw->hcout_size0 = harq_out_length;
> > - fcw->hcout_size1 = 0;
> > - fcw->hcout_offset = 0;
> > + if ((k0_p > fcw->hcin_size0 +
> ACC100_HARQ_OFFSET_THRESHOLD) &&
> > + harq_prun) {
> > + fcw->hcout_size0 = (uint16_t) fcw->hcin_size0;
> > + fcw->hcout_offset = k0_p & 0xFFC0;
> > + fcw->hcout_size1 = harq_out_length - fcw-
> >hcout_offset;
> > + } else {
> > + fcw->hcout_size0 = harq_out_length;
> > + fcw->hcout_size1 = 0;
> > + fcw->hcout_offset = 0;
> > + }
> > +
> > harq_layout[harq_index].offset = fcw->hcout_offset;
> > harq_layout[harq_index].size0 = fcw->hcout_size0;
> > } else {
next prev parent reply other threads:[~2022-09-16 0:32 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-20 2:31 [PATCH v2 00/37] baseband/acc100: changes for 22.11 Hernan Vargas
2022-08-20 2:31 ` [PATCH v2 01/37] baseband/acc100: add enqueue status Hernan Vargas
2022-09-14 16:26 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 02/37] baseband/acc100: update ring availability calculation Hernan Vargas
2022-09-14 16:43 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 03/37] baseband/acc100: add function to check AQ availability Hernan Vargas
2022-09-14 17:00 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 04/37] baseband/acc100: free SW ring mem for reconfiguration Hernan Vargas
2022-09-14 19:22 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 05/37] baseband/acc100: memory leak fix Hernan Vargas
2022-09-14 8:50 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 06/37] baseband/acc100: add default e value for FCW Hernan Vargas
2022-09-14 19:24 ` Maxime Coquelin
2022-09-15 11:00 ` Thomas Monjalon
2022-09-16 1:12 ` Chautru, Nicolas
2022-09-16 7:11 ` Thomas Monjalon
2022-08-20 2:31 ` [PATCH v2 07/37] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-09-14 19:35 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 08/37] baseband/acc100: add scatter-gather support Hernan Vargas
2022-09-14 20:09 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 09/37] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-09-14 20:16 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 10/37] baseband/acc100: avoid mux for small inbound frames Hernan Vargas
2022-09-14 20:18 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 11/37] baseband/acc100: separate validation functions from debug Hernan Vargas
2022-09-14 20:35 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 12/37] baseband/acc100: add LDPC transport block support Hernan Vargas
2022-09-14 20:47 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 13/37] baseband/acc10x: limit cases for HARQ pruning Hernan Vargas
2022-09-15 7:37 ` Maxime Coquelin
2022-09-16 0:31 ` Chautru, Nicolas [this message]
2022-08-20 2:31 ` [PATCH v2 14/37] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-09-15 7:43 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 15/37] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-09-15 8:15 ` Maxime Coquelin
2022-09-16 1:20 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 16/37] baseband/acc100: add ring companion address Hernan Vargas
2022-09-15 9:09 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 17/37] baseband/acc100: configure PMON control registers Hernan Vargas
2022-09-15 9:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 18/37] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-09-15 9:52 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 19/37] baseband/acc100: add queue stop operation Hernan Vargas
2022-09-15 9:55 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 20/37] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-09-15 10:01 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 21/37] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-09-15 10:02 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 22/37] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-09-15 10:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 23/37] baseband/acc100: update uplink CB input length Hernan Vargas
2022-09-15 10:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 24/37] baseband/acc100: rename ldpc encode function arg Hernan Vargas
2022-09-15 10:14 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 25/37] baseband/acc100: update log messages Hernan Vargas
2022-09-15 10:14 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 26/37] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-09-15 10:15 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 27/37] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-09-15 10:18 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 28/37] baseband/acc100: make desc optimization optional Hernan Vargas
2022-09-15 10:19 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 29/37] baseband/acc100: update device info Hernan Vargas
2022-09-15 10:20 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 30/37] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-09-15 10:21 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 31/37] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-09-15 10:22 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 32/37] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-09-15 10:23 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 33/37] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-09-15 10:24 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 34/37] baseband/acc100: update meson file sdk dependency Hernan Vargas
2022-09-15 10:31 ` Maxime Coquelin
2022-09-15 10:57 ` Thomas Monjalon
2022-09-16 0:39 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 35/37] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-09-15 11:33 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 36/37] baseband/acc100: make HARQ layout memory 4GB Hernan Vargas
2022-09-15 11:33 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 37/37] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-09-15 11:34 ` Maxime Coquelin
2022-08-23 15:59 ` [EXT] [PATCH v2 00/37] baseband/acc100: changes for 22.11 Akhil Goyal
2022-08-24 18:23 ` Chautru, Nicolas
2022-09-06 20:03 ` Chautru, Nicolas
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