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From: Helin Zhang <helin.zhang@intel.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH v2 25/27] igb_uio: add sys files to read/write specific bits in pci config space
Date: Thu,  5 Jun 2014 13:09:09 +0800	[thread overview]
Message-ID: <1401944951-23783-26-git-send-email-helin.zhang@intel.com> (raw)
In-Reply-To: <1401944951-23783-1-git-send-email-helin.zhang@intel.com>

Enabling 'Extended Tag' and resetting 'Max Read Request Size' in PCI
config space have big impacts to i40e performance. They cannot be
changed on some BIOS implementations, though can on others. Two sys
files of 'extended_tag' and 'max_read_request_size' are added to
support changing them by 'echo' in user space.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Signed-off-by: Jing Chen <jing.d.chen@intel.com>
Acked-by: Cunming Liang <cunming.liang@intel.com>
Acked-by: Jijiang Liu <jijiang.liu@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Tested-by: Waterman Cao <waterman.cao@intel.com>
---
 lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 105 ++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
index 79fe97d..55e801d 100644
--- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
+++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
@@ -47,6 +47,15 @@
 #define PCI_MSIX_ENTRY_CTRL_MASKBIT     1
 #endif
 
+#ifdef RTE_PCI_CONFIG
+#define PCI_SYS_FILE_BUF_SIZE      10
+#define PCI_DEV_CAP_REG            0xA4
+#define PCI_DEV_CTRL_REG           0xA8
+#define PCI_DEV_CAP_EXT_TAG_MASK   0x20
+#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
+#define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
+#endif
+
 #define IGBUIO_NUM_MSI_VECTORS 1
 
 /* interrupt mode */
@@ -151,9 +160,105 @@ store_max_vfs(struct device *dev, struct device_attribute *attr,
 	return err ? err : count;							
 }
 
+#ifdef RTE_PCI_CONFIG
+static ssize_t
+show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+	uint32_t val = 0;
+
+	pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
+	if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
+		return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
+
+	val = 0;
+	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
+					PCI_DEV_CTRL_REG, &val);
+
+	return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
+		(val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
+}
+
+static ssize_t
+store_extended_tag(struct device *dev,
+		   struct device_attribute *attr,
+		   const char *buf,
+		   size_t count)
+{
+	struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+	uint32_t val = 0, enable;
+
+	if (strncmp(buf, "on", 2) == 0)
+		enable = 1;
+	else if (strncmp(buf, "off", 3) == 0)
+		enable = 0;
+	else
+		return -EINVAL;
+
+	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
+					PCI_DEV_CAP_REG, &val);
+	if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
+		return -EPERM;
+
+	val = 0;
+	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
+					PCI_DEV_CTRL_REG, &val);
+	if (enable)
+		val |= PCI_DEV_CTRL_EXT_TAG_MASK;
+	else
+		val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
+	pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
+					PCI_DEV_CTRL_REG, val);
+
+	return count;
+}
+
+static ssize_t
+show_max_read_request_size(struct device *dev,
+			   struct device_attribute *attr,
+			   char *buf)
+{
+	struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+	int val = pcie_get_readrq(pci_dev);
+
+	return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
+}
+
+static ssize_t
+store_max_read_request_size(struct device *dev,
+			    struct device_attribute *attr,
+			    const char *buf,
+			    size_t count)
+{
+	struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+	unsigned long size = 0;
+	int ret;
+
+	if (strict_strtoul(buf, 0, &size) != 0)
+		return -EINVAL;
+
+	ret = pcie_set_readrq(pci_dev, (int)size);
+	if (ret < 0)
+		return ret;
+
+	return count;
+}
+#endif
+
 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
+#ifdef RTE_PCI_CONFIG
+static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag, \
+						store_extended_tag);
+static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR, \
+	show_max_read_request_size, store_max_read_request_size);
+#endif
+
 static struct attribute *dev_attrs[] = {
 	&dev_attr_max_vfs.attr,
+#ifdef RTE_PCI_CONFIG
+	&dev_attr_extended_tag.attr,
+	&dev_attr_max_read_request_size.attr,
+#endif
         NULL,
 };
 
-- 
1.8.1.4

  parent reply	other threads:[~2014-06-05  5:11 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-05  5:08 [dpdk-dev] [PATCH v2 00/27] Add i40e PMD support Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 01/27] i40e: add basic shared code Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 02/27] i40e: add PMD source files Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 03/27] pci: add macros and pci device IDs to support i40e Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 04/27] igb_uio: add i40e support Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 05/27] mbuf: add new packet flags for i40e Helin Zhang
2014-06-05 15:30   ` Stephen Hemminger
     [not found]     ` <F35DEAC7BCE34641BA9FAC6BCA4A12E70A735ACB@SHSMSX104.ccr.corp.intel.com>
2014-06-12  1:38       ` Zhang, Helin
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 06/27] ethdev: add i40e support Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 07/27] ethdev: support setting maximum packet length to less than 1518 Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 08/27] vmxnet3: enlarge the hash flags of RSS to 64 bits Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 09/27] ixgbe: " Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 10/27] igb: " Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 11/27] mk: add i40e support Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 12/27] config: add configurations for i40e Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 13/27] app/test-pmd: support displaying 32 bytes RX descriptors Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 14/27] app/test-pmd: add command of 'tx_vlan set pvid port_id vlan_id (on|off)' Helin Zhang
2014-06-05  5:08 ` [dpdk-dev] [PATCH v2 15/27] app/testpmd: enlarge the hash flags of RSS to 64 bits Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 16/27] app/test-pmd: add L3 packet type in offload flags Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 17/27] examples/dpdk_qat: use ETH_RSS_IP to replace IP hash flags of RSS Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 18/27] examples/ip_reassembly: " Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 19/27] examples/l3fwd-power: " Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 20/27] examples/l3fwd-vf: " Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 21/27] examples/l3fwd: " Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 22/27] examples/load_balancer: " Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 23/27] examples/multi_process: " Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 24/27] examples/qos_meter: " Helin Zhang
2014-06-05  5:09 ` Helin Zhang [this message]
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 26/27] pci: support reading/writing sys files of 'extended_tag' and 'max_read_request_size' Helin Zhang
2014-06-05  5:09 ` [dpdk-dev] [PATCH v2 27/27] config: add configurations for enabling 'Extended Tag' or resetting 'Max Read Request Size' Helin Zhang
2014-06-05  8:36 ` [dpdk-dev] [PATCH v2 00/27] Add i40e PMD support Zhu, Heqing
2014-06-17 16:27 ` Thomas Monjalon
2014-06-18  8:51   ` Zhang, Helin
2014-06-18  9:23     ` Thomas Monjalon
2014-06-19  6:24       ` Zhang, Helin

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