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* [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD
@ 2019-09-09 13:27 Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 1/8] crypto/octeontx: add device type mailbox routine Anoob Joseph
                   ` (9 more replies)
  0 siblings, 10 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:27 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara, Thomas Monjalon
  Cc: Anoob Joseph, Jerin Jacob, Narayana Prasad, Fiona Trahe,
	Kanaka Durga Kotamarthy, Shally Verma, Sunila Sahu, dev

This series adds asymmetric crypto support in 'crypto_octeontx' PMD.

Features supported: RSA & modular exponentiation

Kanaka Durga Kotamarthy (4):
  crypto/octeontx: add device type mailbox routine
  crypto/octeontx: add RSA and modexp asym capabilities
  crypto/octeontx: add asymmetric session operations
  common/cpt: add helper functions for asymmetric crypto

Sunila Sahu (4):
  crypto/octeontx: add asymmetric op enqueue function
  crypto/octeontx: add asymmetric op dequeue function
  app/test: register octeontx PMD to asym testsuite
  doc: update octeontx asymmetric features

 app/test/test_cryptodev_asym.c                     |  31 ++
 doc/guides/cryptodevs/features/octeontx.ini        |   6 +-
 doc/guides/cryptodevs/octeontx.rst                 |  25 ++
 drivers/common/cpt/cpt_common.h                    |   4 +-
 drivers/common/cpt/cpt_mcode_defines.h             |  29 ++
 drivers/common/cpt/cpt_pmd_ops_helper.c            |  15 +
 drivers/common/cpt/cpt_pmd_ops_helper.h            |   9 +
 drivers/common/cpt/cpt_ucode_asym.h                | 451 +++++++++++++++++++++
 drivers/common/cpt/rte_common_cpt_version.map      |   8 +
 .../crypto/octeontx/otx_cryptodev_capabilities.c   |  47 ++-
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |   5 +-
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  44 +-
 drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  26 +-
 drivers/crypto/octeontx/otx_cryptodev_mbox.h       |  20 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c        | 260 +++++++++++-
 drivers/crypto/octeontx/otx_cryptodev_ops.h        |   2 +
 16 files changed, 944 insertions(+), 38 deletions(-)
 create mode 100644 drivers/common/cpt/cpt_ucode_asym.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 1/8] crypto/octeontx: add device type mailbox routine
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities Anoob Joseph
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara, Thomas Monjalon
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Anoob Joseph, Fiona Trahe, Shally Verma, Sunila Sahu, dev

From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>

Add mailbox communication to query symmetric or asymmetric device type

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/common/cpt/cpt_common.h                   |  3 ---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 12 ++++-----
 drivers/crypto/octeontx/otx_cryptodev_mbox.c      | 26 ++++++++++++++++--
 drivers/crypto/octeontx/otx_cryptodev_mbox.h      | 20 ++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 33 ++++++++++++++++++-----
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  2 ++
 6 files changed, 78 insertions(+), 18 deletions(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 32f23ac..7ef6b29 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -19,9 +19,6 @@
 #define CPT_COUNT_THOLD		32
 #define CPT_TIMER_THOLD		0x3F
 
-#define AE_TYPE 1
-#define SE_TYPE 2
-
 #ifndef ROUNDUP4
 #define ROUNDUP4(val)	(((val) + 3) & 0xfffffffc)
 #endif
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index eba6293..ad64bf4 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -386,6 +386,12 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
 		return -1;
 	}
 
+	/* Gets device type */
+	if (otx_cpt_get_dev_type(cptvf)) {
+		CPT_LOG_ERR("Failed to get device type");
+		return -1;
+	}
+
 	return 0;
 }
 
@@ -653,12 +659,6 @@ otx_cpt_start_device(void *dev)
 		return -EFAULT;
 	}
 
-	if ((cptvf->vftype != SE_TYPE) && (cptvf->vftype != AE_TYPE)) {
-		CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF "
-			    "device %s", cptvf->vftype, cptvf->dev_name);
-		return -ENOENT;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.c b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
index daba776..a884ad6 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
@@ -42,11 +42,19 @@ otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf)
 	case OTX_CPT_MSG_QBIND_GRP:
 		cptvf->pf_acked = true;
 		cptvf->vftype = mbx.data;
-		CPT_LOG_DP_DEBUG("%s: VF %d type %s group %d",
+		CPT_LOG_DP_DEBUG("%s: VF %d group %d",
 				 cptvf->dev_name, cptvf->vfid,
-				 ((mbx.data == SE_TYPE) ? "SE" : "AE"),
 				 cptvf->vfgrp);
 		break;
+	case OTX_CPT_MSG_PF_TYPE:
+		cptvf->pf_acked = true;
+		if (mbx.data == OTX_CPT_PF_TYPE_AE)
+			cptvf->vftype = OTX_CPT_VF_TYPE_AE;
+		else if (mbx.data == OTX_CPT_PF_TYPE_SE)
+			cptvf->vftype = OTX_CPT_VF_TYPE_SE;
+		else
+			cptvf->vftype = OTX_CPT_VF_TYPE_INVALID;
+		break;
 	case OTX_CPT_MBOX_MSG_TYPE_ACK:
 		cptvf->pf_acked = true;
 		break;
@@ -120,6 +128,20 @@ otx_cpt_check_pf_ready(struct cpt_vf *cptvf)
 }
 
 int
+otx_cpt_get_dev_type(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_PF_TYPE;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to query msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
 otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf)
 {
 	struct cpt_mbox mbx = {0, 0};
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.h b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
index 2d2e0e6..508f3af 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
@@ -23,6 +23,20 @@ struct cpt_mbox {
 	uint64_t data;
 };
 
+/* CPT PF types */
+enum otx_cpt_pf_type {
+	OTX_CPT_PF_TYPE_INVALID = 0,
+	OTX_CPT_PF_TYPE_AE = 2,
+	OTX_CPT_PF_TYPE_SE,
+};
+
+/* CPT VF types */
+enum otx_cpt_vf_type {
+	OTX_CPT_VF_TYPE_AE = 1,
+	OTX_CPT_VF_TYPE_SE,
+	OTX_CPT_VF_TYPE_INVALID,
+};
+
 /* PF-VF message opcodes */
 enum otx_cpt_mbox_opcode {
 	OTX_CPT_MSG_VF_UP = 1,
@@ -63,6 +77,12 @@ int
 otx_cpt_check_pf_ready(struct cpt_vf *cptvf);
 
 /*
+ * Communicate to PF to get VF type
+ */
+int
+otx_cpt_get_dev_type(struct cpt_vf *cptvf);
+
+/*
  * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.
  * Must be ACKed.
  */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 9628ffa..88efed3 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -16,6 +16,7 @@
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_capabilities.h"
 #include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
 #include "otx_cryptodev_ops.h"
 
 /* Forward declarations */
@@ -630,6 +631,28 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 		goto fail;
 	}
 
+	switch (cptvf->vftype) {
+	case OTX_CPT_VF_TYPE_AE:
+		/* Set asymmetric cpt feature flags */
+		c_dev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+				RTE_CRYPTODEV_FF_HW_ACCELERATED;
+		break;
+	case OTX_CPT_VF_TYPE_SE:
+		/* Set symmetric cpt feature flags */
+		c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+				RTE_CRYPTODEV_FF_HW_ACCELERATED |
+				RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
+				RTE_CRYPTODEV_FF_IN_PLACE_SGL |
+				RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
+				RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
+		break;
+	default:
+		/* Feature not supported. Abort */
+		CPT_LOG_ERR("VF type not supported by %s", dev_name);
+		ret = -EIO;
+		goto deinit_dev;
+	}
+
 	/* Start off timer for mailbox interrupts */
 	otx_cpt_periodic_alarm_start(cptvf);
 
@@ -638,18 +661,14 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
 	c_dev->dequeue_burst = otx_cpt_pkt_dequeue;
 
-	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
-			RTE_CRYPTODEV_FF_HW_ACCELERATED |
-			RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
-			RTE_CRYPTODEV_FF_IN_PLACE_SGL |
-			RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
-			RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
-
 	/* Save dev private data */
 	c_dev->data->dev_private = cptvf;
 
 	return 0;
 
+deinit_dev:
+	otx_cpt_deinit_device(cptvf);
+
 fail:
 	if (cptvf) {
 		/* Free private data allocated */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index 768ec4f..fac8a3c 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,8 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+#include <rte_cryptodev.h>
+
 #define OTX_CPT_MIN_HEADROOM_REQ	(24)
 #define OTX_CPT_MIN_TAILROOM_REQ	(8)
 #define CPT_NUM_QS_PER_VF		(1)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 1/8] crypto/octeontx: add device type mailbox routine Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-10-01 12:38   ` Akhil Goyal
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 3/8] crypto/octeontx: add asymmetric session operations Anoob Joseph
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Anoob Joseph, Fiona Trahe, Shally Verma, Sunila Sahu, dev

From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>

Add RSA and modexp capabilities supported by octeontx crypto PMD

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 .../crypto/octeontx/otx_cryptodev_capabilities.c   | 47 ++++++++++++++++++++--
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |  5 +--
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |  5 ++-
 3 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
index c6d94c9..8c0358f 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
@@ -6,7 +6,7 @@
 
 #include "otx_cryptodev_capabilities.h"
 
-static const struct rte_cryptodev_capabilities otx_capabilities[] = {
+static const struct rte_cryptodev_capabilities otx_sym_capabilities[] = {
 	/* Symmetric capabilities */
 	{	/* NULL (AUTH) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -597,8 +597,49 @@ static const struct rte_cryptodev_capabilities otx_capabilities[] = {
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
+static const struct rte_cryptodev_capabilities otx_asym_capabilities[] = {
+	/* Asymmetric capabilities */
+	{	/* RSA */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
+				.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+					(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+					(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+					(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+				{.modlen = {
+					.min = 17,
+					.max = 1024,
+					.increment = 1
+				}, }
+			}
+		}, }
+	},
+	{	/* MOD_EXP */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
+				.op_types = 0,
+				{.modlen = {
+					.min = 17,
+					.max = 1024,
+					.increment = 1
+				}, }
+			}
+		}, }
+	},
+	/* End of asymmetric capabilities */
+	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
 const struct rte_cryptodev_capabilities *
-otx_get_capabilities(void)
+otx_get_capabilities(uint64_t flags)
 {
-	return otx_capabilities;
+	if (flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
+		return otx_asym_capabilities;
+	else
+		return otx_sym_capabilities;
+
 }
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
index fc62821..439b50e 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
@@ -8,10 +8,9 @@
 #include <rte_cryptodev.h>
 
 /*
- * Get capabilities list for the device
- *
+ * Get capabilities list for the device, based on device type
  */
 const struct rte_cryptodev_capabilities *
-otx_get_capabilities(void);
+otx_get_capabilities(uint64_t flags);
 
 #endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 88efed3..b59a001 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -105,7 +105,7 @@ otx_cpt_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)
 	if (info != NULL) {
 		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
 		info->feature_flags = dev->feature_flags;
-		info->capabilities = otx_get_capabilities();
+		info->capabilities = otx_get_capabilities(info->feature_flags);
 		info->sym.max_nb_sessions = 0;
 		info->driver_id = otx_cryptodev_driver_id;
 		info->min_mbuf_headroom_req = OTX_CPT_MIN_HEADROOM_REQ;
@@ -635,7 +635,8 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	case OTX_CPT_VF_TYPE_AE:
 		/* Set asymmetric cpt feature flags */
 		c_dev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
-				RTE_CRYPTODEV_FF_HW_ACCELERATED;
+				RTE_CRYPTODEV_FF_HW_ACCELERATED |
+				RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
 		break;
 	case OTX_CPT_VF_TYPE_SE:
 		/* Set symmetric cpt feature flags */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 3/8] crypto/octeontx: add asymmetric session operations
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 1/8] crypto/octeontx: add device type mailbox routine Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-10-01 12:57   ` Akhil Goyal
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto Anoob Joseph
                   ` (6 subsequent siblings)
  9 siblings, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Anoob Joseph, Fiona Trahe, Shally Verma, Sunila Sahu, dev

From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>

Add asymmetric session setup and free functions

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/common/cpt/cpt_mcode_defines.h      |   9 ++
 drivers/common/cpt/cpt_ucode_asym.h         | 169 ++++++++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c |  66 ++++++++++-
 3 files changed, 243 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cpt/cpt_ucode_asym.h

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index c197c7b..3a373ee 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -6,6 +6,7 @@
 #define _CPT_MCODE_DEFINES_H_
 
 #include <rte_byteorder.h>
+#include <rte_crypto_asym.h>
 #include <rte_memory.h>
 
 /*
@@ -316,6 +317,14 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+struct cpt_asym_sess_misc {
+	enum rte_crypto_asym_xform_type xfrm_type;
+	union {
+		struct rte_crypto_rsa_xform rsa_ctx;
+		struct rte_crypto_modex_xform mod_ctx;
+	};
+};
+
 /* Buffer pointer */
 typedef struct buf_ptr {
 	void *vaddr;
diff --git a/drivers/common/cpt/cpt_ucode_asym.h b/drivers/common/cpt/cpt_ucode_asym.h
new file mode 100644
index 0000000..e6bc257
--- /dev/null
+++ b/drivers/common/cpt/cpt_ucode_asym.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _CPT_UCODE_ASYM_H_
+#define _CPT_UCODE_ASYM_H_
+
+#include <rte_common.h>
+#include <rte_crypto_asym.h>
+#include <rte_malloc.h>
+
+#include "cpt_mcode_defines.h"
+
+static __rte_always_inline void
+cpt_modex_param_normalize(uint8_t **data, size_t *len)
+{
+	size_t i;
+
+	/* Strip leading NUL bytes */
+
+	for (i = 0; i < *len; i++) {
+		if ((*data)[i] != 0)
+			break;
+	}
+
+	*data += i;
+	*len -= i;
+}
+
+static __rte_always_inline int
+cpt_fill_modex_params(struct cpt_asym_sess_misc *sess,
+		      struct rte_crypto_asym_xform *xform)
+{
+	struct rte_crypto_modex_xform *ctx = &sess->mod_ctx;
+	size_t exp_len = xform->modex.exponent.length;
+	size_t mod_len = xform->modex.modulus.length;
+	uint8_t *exp = xform->modex.exponent.data;
+	uint8_t *mod = xform->modex.modulus.data;
+
+	cpt_modex_param_normalize(&mod, &mod_len);
+	cpt_modex_param_normalize(&exp, &exp_len);
+
+	if (unlikely(exp_len == 0 || mod_len == 0))
+		return -EINVAL;
+
+	if (unlikely(exp_len > mod_len)) {
+		CPT_LOG_DP_ERR("Exponent length greater than modulus length is not supported");
+		return -ENOTSUP;
+	}
+
+	/* Allocate buffer to hold modexp params */
+	ctx->modulus.data = rte_malloc(NULL, mod_len + exp_len, 0);
+	if (ctx->modulus.data == NULL) {
+		CPT_LOG_DP_ERR("Could not allocate buffer for modex params");
+		return -ENOMEM;
+	}
+
+	/* Set up modexp prime modulus and private exponent */
+
+	memcpy(ctx->modulus.data, mod, mod_len);
+	ctx->exponent.data = ctx->modulus.data + mod_len;
+	memcpy(ctx->exponent.data, exp, exp_len);
+
+	ctx->modulus.length = mod_len;
+	ctx->exponent.length = exp_len;
+
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_fill_rsa_params(struct cpt_asym_sess_misc *sess,
+		    struct rte_crypto_asym_xform *xform)
+{
+	struct rte_crypto_rsa_priv_key_qt qt = xform->rsa.qt;
+	struct rte_crypto_rsa_xform *xfrm_rsa = &xform->rsa;
+	struct rte_crypto_rsa_xform *rsa = &sess->rsa_ctx;
+	size_t mod_len = xfrm_rsa->n.length;
+	size_t exp_len = xfrm_rsa->e.length;
+	uint64_t total_size;
+	size_t len = 0;
+
+	/* Make sure key length used is not more than mod_len/2 */
+	if (qt.p.data != NULL)
+		len = (((mod_len / 2) < qt.p.length) ? len : qt.p.length);
+
+	/* Total size required for RSA key params(n,e,(q,dQ,p,dP,qInv)) */
+	total_size = mod_len + exp_len + 5 * len;
+
+	/* Allocate buffer to hold all RSA keys */
+	rsa->n.data = rte_malloc(NULL, total_size, 0);
+	if (rsa->n.data == NULL) {
+		CPT_LOG_DP_ERR("Could not allocate buffer for RSA keys");
+		return -ENOMEM;
+	}
+
+	/* Set up RSA prime modulus and public key exponent */
+	memcpy(rsa->n.data, xfrm_rsa->n.data, mod_len);
+	rsa->e.data = rsa->n.data + mod_len;
+	memcpy(rsa->e.data, xfrm_rsa->e.data, exp_len);
+
+	/* Private key in quintuple format */
+	if (len != 0) {
+		rsa->qt.q.data = rsa->e.data + exp_len;
+		memcpy(rsa->qt.q.data, qt.q.data, qt.q.length);
+		rsa->qt.dQ.data = rsa->qt.q.data + qt.q.length;
+		memcpy(rsa->qt.dQ.data, qt.dQ.data, qt.dQ.length);
+		rsa->qt.p.data = rsa->qt.dQ.data + qt.dQ.length;
+		memcpy(rsa->qt.p.data, qt.p.data, qt.p.length);
+		rsa->qt.dP.data = rsa->qt.p.data + qt.p.length;
+		memcpy(rsa->qt.dP.data, qt.dP.data, qt.dP.length);
+		rsa->qt.qInv.data = rsa->qt.dP.data + qt.dP.length;
+		memcpy(rsa->qt.qInv.data, qt.qInv.data, qt.qInv.length);
+
+		rsa->qt.q.length = qt.q.length;
+		rsa->qt.dQ.length = qt.dQ.length;
+		rsa->qt.p.length = qt.p.length;
+		rsa->qt.dP.length = qt.dP.length;
+		rsa->qt.qInv.length = qt.qInv.length;
+	}
+	rsa->n.length = mod_len;
+	rsa->e.length = exp_len;
+
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_fill_asym_session_parameters(struct cpt_asym_sess_misc *sess,
+				 struct rte_crypto_asym_xform *xform)
+{
+	int ret;
+
+	sess->xfrm_type = xform->xform_type;
+
+	switch (xform->xform_type) {
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		ret = cpt_fill_rsa_params(sess, xform);
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		ret = cpt_fill_modex_params(sess, xform);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return ret;
+}
+
+static __rte_always_inline void
+cpt_free_asym_session_parameters(struct cpt_asym_sess_misc *sess)
+{
+	struct rte_crypto_modex_xform *mod;
+	struct rte_crypto_rsa_xform *rsa;
+
+	switch (sess->xfrm_type) {
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		rsa = &sess->rsa_ctx;
+		if (rsa->n.data)
+			rte_free(rsa->n.data);
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		mod = &sess->mod_ctx;
+		if (mod->modulus.data)
+			rte_free(mod->modulus.data);
+		break;
+	default:
+		break;
+	}
+}
+
+#endif /* _CPT_UCODE_ASYM_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index b59a001..5c08bc1 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -12,6 +12,7 @@
 
 #include "cpt_pmd_logs.h"
 #include "cpt_ucode.h"
+#include "cpt_ucode_asym.h"
 
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_capabilities.h"
@@ -285,6 +286,65 @@ otx_cpt_session_clear(struct rte_cryptodev *dev,
 	}
 }
 
+static unsigned int
+otx_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
+{
+	return sizeof(struct cpt_asym_sess_misc);
+}
+
+static int
+otx_cpt_asym_session_cfg(struct rte_cryptodev *dev,
+			 struct rte_crypto_asym_xform *xform __rte_unused,
+			 struct rte_cryptodev_asym_session *sess,
+			 struct rte_mempool *pool)
+{
+	struct cpt_asym_sess_misc *priv;
+	int ret;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (rte_mempool_get(pool, (void **)&priv)) {
+		CPT_LOG_ERR("Could not allocate session private data");
+		return -ENOMEM;
+	}
+
+	memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
+
+	ret = cpt_fill_asym_session_parameters(priv, xform);
+	if (ret) {
+		CPT_LOG_ERR("Could not configure session parameters");
+
+		/* Return session to mempool */
+		rte_mempool_put(pool, priv);
+		return ret;
+	}
+
+	set_asym_session_private_data(sess, dev->driver_id, priv);
+	return 0;
+}
+
+static void
+otx_cpt_asym_session_clear(struct rte_cryptodev *dev,
+			   struct rte_cryptodev_asym_session *sess)
+{
+	struct cpt_asym_sess_misc *priv;
+	struct rte_mempool *sess_mp;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	priv = get_asym_session_private_data(sess, dev->driver_id);
+
+	if (priv == NULL)
+		return;
+
+	/* Free resources allocated during session configure */
+	cpt_free_asym_session_parameters(priv);
+	memset(priv, 0, otx_cpt_asym_session_size_get(dev));
+	sess_mp = rte_mempool_from_obj(priv);
+	set_asym_session_private_data(sess, dev->driver_id, NULL);
+	rte_mempool_put(sess_mp, priv);
+}
+
 static __rte_always_inline int32_t __hot
 otx_cpt_request_enqueue(struct cpt_instance *instance,
 			struct pending_queue *pqueue,
@@ -584,7 +644,11 @@ static struct rte_cryptodev_ops cptvf_ops = {
 	/* Crypto related operations */
 	.sym_session_get_size = otx_cpt_get_session_size,
 	.sym_session_configure = otx_cpt_session_cfg,
-	.sym_session_clear = otx_cpt_session_clear
+	.sym_session_clear = otx_cpt_session_clear,
+
+	.asym_session_get_size = otx_cpt_asym_session_size_get,
+	.asym_session_configure = otx_cpt_asym_session_cfg,
+	.asym_session_clear = otx_cpt_asym_session_clear,
 };
 
 int
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
                   ` (2 preceding siblings ...)
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 3/8] crypto/octeontx: add asymmetric session operations Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-10-01 13:04   ` Akhil Goyal
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 5/8] crypto/octeontx: add asymmetric op enqueue function Anoob Joseph
                   ` (5 subsequent siblings)
  9 siblings, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Anoob Joseph, Fiona Trahe, Shally Verma, Sunila Sahu, dev

From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>

Add helper functions to get meta len for asymmetric operations

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/common/cpt/cpt_pmd_ops_helper.c           | 15 +++++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.h           |  9 +++++++
 drivers/common/cpt/rte_common_cpt_version.map     |  8 ++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 32 +++++++++++++++--------
 4 files changed, 53 insertions(+), 11 deletions(-)

diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.c b/drivers/common/cpt/cpt_pmd_ops_helper.c
index 1c18180..09b762f 100644
--- a/drivers/common/cpt/cpt_pmd_ops_helper.c
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.c
@@ -11,6 +11,8 @@
 
 #define CPT_MAX_IV_LEN 16
 #define CPT_OFFSET_CONTROL_BYTES 8
+#define CPT_MAX_ASYM_OP_NUM_PARAMS 5
+#define CPT_MAX_ASYM_OP_MOD_LEN 1024
 
 int32_t
 cpt_pmd_ops_helper_get_mlen_direct_mode(void)
@@ -39,3 +41,16 @@ cpt_pmd_ops_helper_get_mlen_sg_mode(void)
 	len += 2 * sizeof(cpt_res_s_t);
 	return len;
 }
+
+int
+cpt_pmd_ops_helper_asym_get_mlen(void)
+{
+	uint32_t len;
+
+	/* Get meta len for linear buffer (direct) mode */
+	len = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+	/* Get meta len for asymmetric operations */
+	len += CPT_MAX_ASYM_OP_NUM_PARAMS * CPT_MAX_ASYM_OP_MOD_LEN;
+	return len;
+}
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.h b/drivers/common/cpt/cpt_pmd_ops_helper.h
index dd32f9a..24c3559 100644
--- a/drivers/common/cpt/cpt_pmd_ops_helper.h
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.h
@@ -31,4 +31,13 @@ cpt_pmd_ops_helper_get_mlen_direct_mode(void);
  */
 int
 cpt_pmd_ops_helper_get_mlen_sg_mode(void);
+
+/*
+ * Get size of meta buffer to be allocated for asymmetric crypto operations
+ *
+ * @return
+ *  - length
+ */
+int
+cpt_pmd_ops_helper_asym_get_mlen(void);
 #endif /* _CPT_PMD_OPS_HELPER_H_ */
diff --git a/drivers/common/cpt/rte_common_cpt_version.map b/drivers/common/cpt/rte_common_cpt_version.map
index dec614f..382ec4b 100644
--- a/drivers/common/cpt/rte_common_cpt_version.map
+++ b/drivers/common/cpt/rte_common_cpt_version.map
@@ -4,3 +4,11 @@ DPDK_18.11 {
 	cpt_pmd_ops_helper_get_mlen_direct_mode;
 	cpt_pmd_ops_helper_get_mlen_sg_mode;
 };
+
+DPDK_19.11 {
+	global:
+
+	cpt_pmd_ops_helper_asym_get_mlen;
+
+	local: *;
+};
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index ad64bf4..0543494 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -412,24 +412,34 @@ otx_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
 			       int nb_elements)
 {
 	char mempool_name[RTE_MEMPOOL_NAMESIZE];
-	int sg_mlen, lb_mlen, max_mlen, ret;
 	struct cpt_qp_meta_info *meta_info;
 	struct rte_mempool *pool;
+	int max_mlen = 0;
+	int sg_mlen = 0;
+	int lb_mlen = 0;
+	int ret;
 
-	/* Get meta len for scatter gather mode */
-	sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+	if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
 
-	/* Extra 32B saved for future considerations */
-	sg_mlen += 4 * sizeof(uint64_t);
+		/* Get meta len for scatter gather mode */
+		sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
 
-	/* Get meta len for linear buffer (direct) mode */
-	lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+		/* Extra 32B saved for future considerations */
+		sg_mlen += 4 * sizeof(uint64_t);
 
-	/* Extra 32B saved for future considerations */
-	lb_mlen += 4 * sizeof(uint64_t);
+		/* Get meta len for linear buffer (direct) mode */
+		lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
 
-	/* Check max requirement for meta buffer */
-	max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+		/* Extra 32B saved for future considerations */
+		lb_mlen += 4 * sizeof(uint64_t);
+
+		/* Check max requirement for meta buffer */
+		max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+	} else if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
+
+		/* Get meta len for asymmetric operations */
+		max_mlen = cpt_pmd_ops_helper_asym_get_mlen();
+	}
 
 	/* Allocate mempool */
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 5/8] crypto/octeontx: add asymmetric op enqueue function
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
                   ` (3 preceding siblings ...)
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 6/8] crypto/octeontx: add asymmetric op dequeue function Anoob Joseph
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob, Narayana Prasad, Anoob Joseph,
	Fiona Trahe, Kanaka Durga Kotamarthy, Shally Verma, dev

From: Sunila Sahu <ssahu@marvell.com>

Add asymmetric crypto op enqueue routine

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/common/cpt/cpt_common.h             |   1 +
 drivers/common/cpt/cpt_mcode_defines.h      |  20 ++
 drivers/common/cpt/cpt_ucode_asym.h         | 282 ++++++++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c |  70 +++++++
 4 files changed, 373 insertions(+)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 7ef6b29..dff45f0 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -75,6 +75,7 @@ struct cpt_request_info {
 		uint64_t ei2;
 		uint64_t ei3;
 	} ist;
+	uint8_t *rptr;
 
 	/** Control path fields */
 	uint64_t time_out;
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 3a373ee..f356e62 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -21,6 +21,18 @@
 #define CPT_MAJOR_OP_KASUMI	0x38
 #define CPT_MAJOR_OP_MISC	0x01
 
+/* AE opcodes */
+#define CPT_MAJOR_OP_MODEX	0x03
+#define CPT_MINOR_OP_MODEX	0x01
+#define CPT_MINOR_OP_PKCS_ENC	0x02
+#define CPT_MINOR_OP_PKCS_ENC_CRT	0x03
+#define CPT_MINOR_OP_PKCS_DEC	0x04
+#define CPT_MINOR_OP_PKCS_DEC_CRT	0x05
+#define CPT_MINOR_OP_MODEX_CRT	0x06
+
+#define CPT_BLOCK_TYPE1 0
+#define CPT_BLOCK_TYPE2 1
+
 #define CPT_BYTE_16		16
 #define CPT_BYTE_24		24
 #define CPT_BYTE_32		32
@@ -369,6 +381,14 @@ typedef struct fc_params {
 } fc_params_t;
 
 /*
+ * Parameters for asymmetric operations
+ */
+struct asym_op_params {
+	struct cpt_request_info *req;
+	phys_addr_t meta_buf;
+};
+
+/*
  * Parameters for digest
  * generate requests
  * Only src_iov, op, ctx_buf, mac_buf, prep_req
diff --git a/drivers/common/cpt/cpt_ucode_asym.h b/drivers/common/cpt/cpt_ucode_asym.h
index e6bc257..0b47bd8 100644
--- a/drivers/common/cpt/cpt_ucode_asym.h
+++ b/drivers/common/cpt/cpt_ucode_asym.h
@@ -9,6 +9,8 @@
 #include <rte_crypto_asym.h>
 #include <rte_malloc.h>
 
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
 #include "cpt_mcode_defines.h"
 
 static __rte_always_inline void
@@ -166,4 +168,284 @@ cpt_free_asym_session_parameters(struct cpt_asym_sess_misc *sess)
 	}
 }
 
+static __rte_always_inline void
+cpt_fill_req_comp_addr(struct cpt_request_info *req, buf_ptr_t addr)
+{
+	void *completion_addr = RTE_PTR_ALIGN(addr.vaddr, 16);
+
+	/* Pointer to cpt_res_s, updated by CPT */
+	req->completion_addr = (volatile uint64_t *)completion_addr;
+	req->comp_baddr = addr.dma_addr +
+			  RTE_PTR_DIFF(completion_addr, addr.vaddr);
+	*(req->completion_addr) = COMPLETION_CODE_INIT;
+}
+
+static __rte_always_inline int
+cpt_modex_prep(struct asym_op_params *modex_params,
+	       struct rte_crypto_modex_xform *mod)
+{
+	struct cpt_request_info *req = modex_params->req;
+	phys_addr_t mphys = modex_params->meta_buf;
+	uint32_t exp_len = mod->exponent.length;
+	uint32_t mod_len = mod->modulus.length;
+	struct rte_crypto_mod_op_param mod_op;
+	struct rte_crypto_op **op;
+	vq_cmd_word0_t vq_cmd_w0;
+	uint64_t total_key_len;
+	opcode_info_t opcode;
+	uint32_t dlen, rlen;
+	uint32_t base_len;
+	buf_ptr_t caddr;
+	uint8_t *dptr;
+
+	/* Extracting modex op form params->req->op[1]->asym->modex */
+	op = RTE_PTR_ADD(req->op, sizeof(uintptr_t));
+	mod_op = ((struct rte_crypto_op *)*op)->asym->modex;
+
+	base_len = mod_op.base.length;
+	if (unlikely(base_len > mod_len)) {
+		CPT_LOG_DP_ERR("Base length greater than modulus length is not supported");
+		(*op)->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		return -ENOTSUP;
+	}
+
+	total_key_len = mod_len + exp_len;
+
+	/* Input buffer */
+	dptr = RTE_PTR_ADD(req, sizeof(struct cpt_request_info));
+	memcpy(dptr, mod->modulus.data, total_key_len);
+	dptr += total_key_len;
+	memcpy(dptr, mod_op.base.data, base_len);
+	dptr += base_len;
+	dlen = total_key_len + base_len;
+
+	/* Result buffer */
+	rlen = mod_len;
+
+	/* Setup opcodes */
+	opcode.s.major = CPT_MAJOR_OP_MODEX;
+	opcode.s.minor = CPT_MINOR_OP_MODEX;
+	vq_cmd_w0.s.opcode = opcode.flags;
+
+	/* GP op header */
+	vq_cmd_w0.s.param1 = mod_len;
+	vq_cmd_w0.s.param2 = exp_len;
+	vq_cmd_w0.s.dlen = dlen;
+
+	/* Filling cpt_request_info structure */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei1 = mphys;
+	req->ist.ei2 = mphys + dlen;
+
+	/* Result pointer to store result data */
+	req->rptr = dptr;
+
+	/* alternate_caddr to write completion status of the microcode */
+	req->alternate_caddr = (uint64_t *)(dptr + rlen);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+
+	/* Preparing completion addr, +1 for completion code */
+	caddr.vaddr = dptr + rlen + 1;
+	caddr.dma_addr = mphys + dlen + rlen + 1;
+
+	cpt_fill_req_comp_addr(req, caddr);
+	return 0;
+}
+
+static __rte_always_inline void
+cpt_rsa_prep(struct asym_op_params *rsa_params,
+	     struct rte_crypto_rsa_xform *rsa,
+	     rte_crypto_param *crypto_param)
+{
+	struct cpt_request_info *req = rsa_params->req;
+	phys_addr_t mphys = rsa_params->meta_buf;
+	struct rte_crypto_rsa_op_param rsa_op;
+	uint32_t mod_len = rsa->n.length;
+	uint32_t exp_len = rsa->e.length;
+	struct rte_crypto_op **op;
+	vq_cmd_word0_t vq_cmd_w0;
+	uint64_t total_key_len;
+	opcode_info_t opcode;
+	uint32_t dlen, rlen;
+	uint32_t in_size;
+	buf_ptr_t caddr;
+	uint8_t *dptr;
+
+	/* Extracting rsa op form params->req->op[1]->asym->rsa */
+	op = RTE_PTR_ADD(req->op, sizeof(uintptr_t));
+	rsa_op = ((struct rte_crypto_op *)*op)->asym->rsa;
+	total_key_len  = mod_len + exp_len;
+
+	/* Input buffer */
+	dptr = RTE_PTR_ADD(req, sizeof(struct cpt_request_info));
+	memcpy(dptr, rsa->n.data, total_key_len);
+	dptr += total_key_len;
+
+	in_size = crypto_param->length;
+	memcpy(dptr, crypto_param->data, in_size);
+
+	dptr += in_size;
+	dlen = total_key_len + in_size;
+
+	/* Result buffer */
+	rlen = mod_len;
+
+	if (rsa_op.pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+		/* Use mod_exp operation for no_padding type */
+		opcode.s.minor = CPT_MINOR_OP_MODEX;
+		vq_cmd_w0.s.param2 = exp_len;
+	} else {
+		if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_ENC;
+			/* Public key encrypt, use BT2*/
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE2 |
+					((uint16_t)(exp_len) << 1);
+		} else if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_VERIFY) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_DEC;
+			/* Public key decrypt, use BT1 */
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE1;
+			/* + 2 for decrypted len */
+			rlen += 2;
+		}
+	}
+
+	/* Setup opcodes */
+	opcode.s.major = CPT_MAJOR_OP_MODEX;
+	vq_cmd_w0.s.opcode = opcode.flags;
+
+	/* GP op header */
+	vq_cmd_w0.s.param1 = mod_len;
+	vq_cmd_w0.s.dlen = dlen;
+
+	/* Filling cpt_request_info structure */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei1 = mphys;
+	req->ist.ei2 = mphys + dlen;
+
+	/* Result pointer to store result data */
+	req->rptr = dptr;
+
+	/* alternate_caddr to write completion status of the microcode */
+	req->alternate_caddr = (uint64_t *)(dptr + rlen);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+
+	/* Preparing completion addr, +1 for completion code */
+	caddr.vaddr = dptr + rlen + 1;
+	caddr.dma_addr = mphys + dlen + rlen + 1;
+
+	cpt_fill_req_comp_addr(req, caddr);
+}
+
+static __rte_always_inline void
+cpt_rsa_crt_prep(struct asym_op_params *rsa_params,
+		 struct rte_crypto_rsa_xform *rsa,
+		 rte_crypto_param *crypto_param)
+{
+	struct cpt_request_info *req = rsa_params->req;
+	phys_addr_t mphys = rsa_params->meta_buf;
+	uint32_t qInv_len = rsa->qt.qInv.length;
+	struct rte_crypto_rsa_op_param rsa_op;
+	uint32_t dP_len = rsa->qt.dP.length;
+	uint32_t dQ_len = rsa->qt.dQ.length;
+	uint32_t p_len = rsa->qt.p.length;
+	uint32_t q_len = rsa->qt.q.length;
+	uint32_t mod_len = rsa->n.length;
+	struct rte_crypto_op **op;
+	vq_cmd_word0_t vq_cmd_w0;
+	uint64_t total_key_len;
+	opcode_info_t opcode;
+	uint32_t dlen, rlen;
+	uint32_t in_size;
+	buf_ptr_t caddr;
+	uint8_t *dptr;
+
+	/* Extracting rsa op form params->req->op[1]->asym->rsa */
+	op = RTE_PTR_ADD(req->op, sizeof(uintptr_t));
+	rsa_op = ((struct rte_crypto_op *)*op)->asym->rsa;
+	total_key_len = p_len + q_len + dP_len + dQ_len + qInv_len;
+
+	/* Input buffer */
+	dptr = RTE_PTR_ADD(req, sizeof(struct cpt_request_info));
+	memcpy(dptr, rsa->qt.q.data, total_key_len);
+	dptr += total_key_len;
+
+	in_size = crypto_param->length;
+	memcpy(dptr, crypto_param->data, in_size);
+
+	dptr += in_size;
+	dlen = total_key_len + in_size;
+
+	/* Result buffer */
+	rlen = mod_len;
+
+	if (rsa_op.pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+		/*Use mod_exp operation for no_padding type */
+		opcode.s.minor = CPT_MINOR_OP_MODEX_CRT;
+	} else {
+		if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_SIGN) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_ENC_CRT;
+			/* Private encrypt, use BT1 */
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE1;
+		} else if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_DECRYPT) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_DEC_CRT;
+			/* Private decrypt, use BT2 */
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE2;
+			/* + 2 for decrypted len */
+			rlen += 2;
+		}
+	}
+
+	/* Setup opcodes */
+	opcode.s.major = CPT_MAJOR_OP_MODEX;
+	vq_cmd_w0.s.opcode = opcode.flags;
+
+	/* GP op header */
+	vq_cmd_w0.s.param1 = mod_len;
+	vq_cmd_w0.s.dlen = dlen;
+
+	/* Filling cpt_request_info structure */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei1 = mphys;
+	req->ist.ei2 = mphys + dlen;
+
+	/* Result pointer to store result data */
+	req->rptr = dptr;
+
+	/* alternate_caddr to write completion status of the microcode */
+	req->alternate_caddr = (uint64_t *)(dptr + rlen);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+
+	/* Preparing completion addr, +1 for completion code */
+	caddr.vaddr = dptr + rlen + 1;
+	caddr.dma_addr = mphys + dlen + rlen + 1;
+
+	cpt_fill_req_comp_addr(req, caddr);
+}
+
+static __rte_always_inline int __hot
+cpt_enqueue_rsa_op(struct rte_crypto_op *op,
+	       struct asym_op_params *params,
+	       struct cpt_asym_sess_misc *sess)
+{
+	struct rte_crypto_rsa_op_param *rsa = &op->asym->rsa;
+
+	switch (rsa->op_type) {
+	case RTE_CRYPTO_ASYM_OP_VERIFY:
+		cpt_rsa_prep(params, &sess->rsa_ctx, &rsa->sign);
+		break;
+	case RTE_CRYPTO_ASYM_OP_ENCRYPT:
+		cpt_rsa_prep(params, &sess->rsa_ctx, &rsa->message);
+		break;
+	case RTE_CRYPTO_ASYM_OP_SIGN:
+		cpt_rsa_crt_prep(params, &sess->rsa_ctx, &rsa->message);
+		break;
+	case RTE_CRYPTO_ASYM_OP_DECRYPT:
+		cpt_rsa_crt_prep(params, &sess->rsa_ctx, &rsa->cipher);
+		break;
+	default:
+		op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		return -EINVAL;
+	}
+	return 0;
+}
 #endif /* _CPT_UCODE_ASYM_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 5c08bc1..1f42fe8 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -379,6 +379,74 @@ otx_cpt_request_enqueue(struct cpt_instance *instance,
 }
 
 static __rte_always_inline int __hot
+otx_cpt_enq_single_asym(struct cpt_instance *instance,
+			struct rte_crypto_op *op,
+			struct pending_queue *pqueue)
+{
+	struct cpt_qp_meta_info *minfo = &instance->meta_info;
+	struct rte_crypto_asym_op *asym_op = op->asym;
+	struct asym_op_params params = {0};
+	struct cpt_asym_sess_misc *sess;
+	uintptr_t *cop;
+	void *mdata;
+	int ret;
+
+	if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
+		CPT_LOG_DP_ERR("Could not allocate meta buffer for request");
+		return -ENOMEM;
+	}
+
+	sess = get_asym_session_private_data(asym_op->session,
+					     otx_cryptodev_driver_id);
+
+	/* Store phys_addr of the mdata to meta_buf */
+	params.meta_buf = rte_mempool_virt2iova(mdata);
+
+	cop = mdata;
+	cop[0] = (uintptr_t)mdata;
+	cop[1] = (uintptr_t)op;
+	cop[2] = cop[3] = 0ULL;
+
+	params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
+	params.req->op = cop;
+
+	/* Adjust meta_buf by crypto_op data  and request_info struct */
+	params.meta_buf += (4 * sizeof(uintptr_t)) +
+			   sizeof(struct cpt_request_info);
+
+	switch (sess->xfrm_type) {
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		ret = cpt_modex_prep(&params, &sess->mod_ctx);
+		if (unlikely(ret))
+			goto req_fail;
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		ret = cpt_enqueue_rsa_op(op, &params, sess);
+		if (unlikely(ret))
+			goto req_fail;
+		break;
+	default:
+		op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		ret = -EINVAL;
+		goto req_fail;
+	}
+
+	ret = otx_cpt_request_enqueue(instance, pqueue, params.req);
+
+	if (unlikely(ret)) {
+		CPT_LOG_DP_ERR("Could not enqueue crypto req");
+		goto req_fail;
+	}
+
+	return 0;
+
+req_fail:
+	free_op_meta(mdata, minfo->pool);
+
+	return ret;
+}
+
+static __rte_always_inline int __hot
 otx_cpt_enq_single_sym(struct cpt_instance *instance,
 		       struct rte_crypto_op *op,
 		       struct pending_queue *pqueue)
@@ -484,6 +552,8 @@ otx_cpt_enq_single(struct cpt_instance *inst,
 {
 	/* Check for the type */
 
+	if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC)
+		return otx_cpt_enq_single_asym(inst, op, pqueue);
 	if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
 		return otx_cpt_enq_single_sym(inst, op, pqueue);
 	else if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS))
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 6/8] crypto/octeontx: add asymmetric op dequeue function
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
                   ` (4 preceding siblings ...)
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 5/8] crypto/octeontx: add asymmetric op enqueue function Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 7/8] app/test: register octeontx PMD to asym testsuite Anoob Joseph
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob, Narayana Prasad, Anoob Joseph,
	Fiona Trahe, Kanaka Durga Kotamarthy, Shally Verma, dev

From: Sunila Sahu <ssahu@marvell.com>

Add asymmetric crypto op dequeue routine

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/crypto/octeontx/otx_cryptodev_ops.c | 88 +++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 1f42fe8..ab1ee7e 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -591,6 +591,87 @@ otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 }
 
 static __rte_always_inline void
+otx_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
+		    struct rte_crypto_rsa_xform *rsa_ctx)
+
+{
+	struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
+
+	switch (rsa->op_type) {
+	case RTE_CRYPTO_ASYM_OP_ENCRYPT:
+		rsa->cipher.length = rsa_ctx->n.length;
+		memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
+		break;
+	case RTE_CRYPTO_ASYM_OP_DECRYPT:
+		if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE)
+			rsa->message.length = rsa_ctx->n.length;
+		else {
+			/* Get length of decrypted output */
+			rsa->message.length = rte_cpu_to_be_16
+					(*((uint16_t *)req->rptr));
+
+			/* Offset data pointer by length fields */
+			req->rptr += 2;
+		}
+		memcpy(rsa->message.data, req->rptr, rsa->message.length);
+		break;
+	case RTE_CRYPTO_ASYM_OP_SIGN:
+		rsa->sign.length = rsa_ctx->n.length;
+		memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+		break;
+	case RTE_CRYPTO_ASYM_OP_VERIFY:
+		if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE)
+			rsa->sign.length = rsa_ctx->n.length;
+		else {
+			/* Get length of decrypted output */
+			rsa->sign.length = rte_cpu_to_be_16
+					(*((uint16_t *)req->rptr));
+
+			/* Offset data pointer by length fields */
+			req->rptr += 2;
+		}
+		memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+
+		if (memcmp(rsa->sign.data, rsa->message.data,
+			   rsa->message.length)) {
+			CPT_LOG_DP_ERR("RSA verification failed");
+			cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		}
+		break;
+	default:
+		CPT_LOG_DP_DEBUG("Invalid RSA operation type");
+		cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		break;
+	}
+}
+
+static void
+otx_cpt_asym_post_process(struct rte_crypto_op *cop,
+			  struct cpt_request_info *req)
+{
+	struct rte_crypto_asym_op *op = cop->asym;
+	struct cpt_asym_sess_misc *sess;
+
+	sess = get_asym_session_private_data(op->session,
+					     otx_cryptodev_driver_id);
+
+	switch (sess->xfrm_type) {
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		otx_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		op->modex.result.length = sess->mod_ctx.modulus.length;
+		memcpy(op->modex.result.data, req->rptr,
+		       op->modex.result.length);
+		break;
+	default:
+		CPT_LOG_DP_DEBUG("Invalid crypto xform type");
+		cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		break;
+	}
+}
+
+static __rte_always_inline void
 otx_cpt_dequeue_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
 {
 	/* H/w has returned success */
@@ -604,6 +685,13 @@ otx_cpt_dequeue_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
 			compl_auth_verify(cop, (uint8_t *)rsp[2], rsp[3]);
 		return;
 	}
+
+	if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
+		rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
+		otx_cpt_asym_post_process(cop, (struct cpt_request_info *)rsp);
+	}
+
+	return;
 }
 
 static uint16_t
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 7/8] app/test: register octeontx PMD to asym testsuite
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
                   ` (5 preceding siblings ...)
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 6/8] crypto/octeontx: add asymmetric op dequeue function Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features Anoob Joseph
                   ` (2 subsequent siblings)
  9 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob, Narayana Prasad, Anoob Joseph,
	Fiona Trahe, Kanaka Durga Kotamarthy, Shally Verma, dev

From: Sunila Sahu <ssahu@marvell.com>

Updated asymmetric crypto unit-test application to test
asymmetric crypto operations in octeontx PMD

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 app/test/test_cryptodev_asym.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index e8177e7..241c384 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1791,6 +1791,19 @@ static struct unit_test_suite cryptodev_qat_asym_testsuite  = {
 	}
 };
 
+static struct unit_test_suite cryptodev_octeontx_asym_testsuite  = {
+	.suite_name = "Crypto Device OCTEONTX ASYM Unit Test Suite",
+	.setup = testsuite_setup,
+	.teardown = testsuite_teardown,
+	.unit_test_cases = {
+		TEST_CASE_ST(ut_setup, ut_teardown, test_capability),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_rsa_enc_dec_crt),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_rsa_sign_verify_crt),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_mod_exp),
+		TEST_CASES_END() /**< NULL terminate unit test array */
+	}
+};
+
 static int
 test_cryptodev_openssl_asym(void)
 {
@@ -1823,7 +1836,25 @@ test_cryptodev_qat_asym(void)
 	return unit_test_suite_runner(&cryptodev_qat_asym_testsuite);
 }
 
+static int
+test_cryptodev_octeontx_asym(void)
+{
+	gbl_driver_id = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+	if (gbl_driver_id == -1) {
+		RTE_LOG(ERR, USER1, "OCTEONTX PMD must be loaded. Check if "
+				"CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO is "
+				"enabled in config file to run this "
+				"testsuite.\n");
+		return TEST_FAILED;
+	}
+	return unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);
+}
+
 REGISTER_TEST_COMMAND(cryptodev_openssl_asym_autotest,
 					  test_cryptodev_openssl_asym);
 
 REGISTER_TEST_COMMAND(cryptodev_qat_asym_autotest, test_cryptodev_qat_asym);
+
+REGISTER_TEST_COMMAND(cryptodev_octeontx_asym_autotest,
+					  test_cryptodev_octeontx_asym);
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
                   ` (6 preceding siblings ...)
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 7/8] app/test: register octeontx PMD to asym testsuite Anoob Joseph
@ 2019-09-09 13:28 ` Anoob Joseph
  2019-10-01 13:27   ` Akhil Goyal
  2019-09-09 15:51 ` [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Shally Verma
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
  9 siblings, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-09-09 13:28 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob, Narayana Prasad, Anoob Joseph,
	Fiona Trahe, Kanaka Durga Kotamarthy, Shally Verma, dev

From: Sunila Sahu <ssahu@marvell.com>

Update documentation with supported asymmetric features for octeontx

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 doc/guides/cryptodevs/features/octeontx.ini |  6 +++++-
 doc/guides/cryptodevs/octeontx.rst          | 25 +++++++++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/doc/guides/cryptodevs/features/octeontx.ini b/doc/guides/cryptodevs/features/octeontx.ini
index 1735b8f..1c036c5 100644
--- a/doc/guides/cryptodevs/features/octeontx.ini
+++ b/doc/guides/cryptodevs/features/octeontx.ini
@@ -5,11 +5,13 @@
 ;
 [Features]
 Symmetric crypto       = Y
+Asymmetric crypto      = Y
 Sym operation chaining = Y
 HW Accelerated         = Y
 In Place SGL           = Y
 OOP SGL In LB  Out     = Y
 OOP SGL In SGL Out     = Y
+RSA PRIV OP KEY QT     = Y
 
 ;
 ; Supported crypto algorithms of 'octeontx' crypto driver.
@@ -64,4 +66,6 @@ AES GCM (256) = Y
 ;
 ; Supported Asymmetric algorithms of the 'octeontx' crypto driver.
 ;
-[Asymmetric]
\ No newline at end of file
+[Asymmetric]
+RSA                    = Y
+Modular Exponentiation = Y
diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst
index 1600a56..a26882b 100644
--- a/doc/guides/cryptodevs/octeontx.rst
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -53,6 +53,12 @@ AEAD Algorithms
 
 * ``RTE_CRYPTO_AEAD_AES_GCM``
 
+Asymmetric Crypto Algorithms
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_ASYM_XFORM_RSA``
+* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
+
 Config flags
 ------------
 
@@ -120,3 +126,22 @@ OCTEON TX crypto PMD.
 
         ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
         "(1,0,0),(0,0,0)" -f ep1.cfg
+
+Testing
+-------
+
+The symmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+        ./test
+        RTE>>cryptodev_octeontx_autotest
+
+The asymmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+        ./test
+        RTE>>cryptodev_octeontx_asym_autotest
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
                   ` (7 preceding siblings ...)
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features Anoob Joseph
@ 2019-09-09 15:51 ` Shally Verma
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
  9 siblings, 0 replies; 31+ messages in thread
From: Shally Verma @ 2019-09-09 15:51 UTC (permalink / raw)
  To: Anoob Joseph, Akhil Goyal, Pablo de Lara, Thomas Monjalon
  Cc: Anoob Joseph, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe,
	Kanaka Durga Kotamarthy, Sunila Sahu, dev



> -----Original Message-----
> From: Anoob Joseph <anoobj@marvell.com>
> Sent: Monday, September 9, 2019 6:58 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon
> <thomas@monjalon.net>
> Cc: Anoob Joseph <anoobj@marvell.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>; Kanaka
> Durga Kotamarthy <kkotamarthy@marvell.com>; Shally Verma
> <shallyv@marvell.com>; Sunila Sahu <ssahu@marvell.com>; dev@dpdk.org
> Subject: [PATCH 0/8] add asym support in crypto_octeontx PMD
> 
> This series adds asymmetric crypto support in 'crypto_octeontx' PMD.
> 
> Features supported: RSA & modular exponentiation
> 
> Kanaka Durga Kotamarthy (4):
>   crypto/octeontx: add device type mailbox routine
>   crypto/octeontx: add RSA and modexp asym capabilities
>   crypto/octeontx: add asymmetric session operations
>   common/cpt: add helper functions for asymmetric crypto
> 
> Sunila Sahu (4):
>   crypto/octeontx: add asymmetric op enqueue function
>   crypto/octeontx: add asymmetric op dequeue function
>   app/test: register octeontx PMD to asym testsuite
>   doc: update octeontx asymmetric features
> 
>  app/test/test_cryptodev_asym.c                     |  31 ++
>  doc/guides/cryptodevs/features/octeontx.ini        |   6 +-
>  doc/guides/cryptodevs/octeontx.rst                 |  25 ++
>  drivers/common/cpt/cpt_common.h                    |   4 +-
>  drivers/common/cpt/cpt_mcode_defines.h             |  29 ++
>  drivers/common/cpt/cpt_pmd_ops_helper.c            |  15 +
>  drivers/common/cpt/cpt_pmd_ops_helper.h            |   9 +
>  drivers/common/cpt/cpt_ucode_asym.h                | 451
> +++++++++++++++++++++
>  drivers/common/cpt/rte_common_cpt_version.map      |   8 +
>  .../crypto/octeontx/otx_cryptodev_capabilities.c   |  47 ++-
>  .../crypto/octeontx/otx_cryptodev_capabilities.h   |   5 +-
>  drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  44 +-
>  drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  26 +-
>  drivers/crypto/octeontx/otx_cryptodev_mbox.h       |  20 +
>  drivers/crypto/octeontx/otx_cryptodev_ops.c        | 260 +++++++++++-
>  drivers/crypto/octeontx/otx_cryptodev_ops.h        |   2 +
>  16 files changed, 944 insertions(+), 38 deletions(-)  create mode 100644
> drivers/common/cpt/cpt_ucode_asym.h
> 
> --
> 2.7.4
Series Ack-by: Shally Verma <shallyv@marvell.com>


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities Anoob Joseph
@ 2019-10-01 12:38   ` Akhil Goyal
  2019-10-02 10:48     ` Anoob Joseph
  0 siblings, 1 reply; 31+ messages in thread
From: Akhil Goyal @ 2019-10-01 12:38 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Fiona Trahe, Shally Verma, Sunila Sahu, dev

Hi Anoob,

>  const struct rte_cryptodev_capabilities *
> -otx_get_capabilities(void)
> +otx_get_capabilities(uint64_t flags)
>  {
> -	return otx_capabilities;
> +	if (flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
> +		return otx_asym_capabilities;
> +	else
> +		return otx_sym_capabilities;
> +
>  }

I believe this will give Asym capabilities always. As the feature flag
RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO will always be set, as the flags are set in init.

It will never go in else.

> diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> index fc62821..439b50e 100644
> --- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> +++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> @@ -8,10 +8,9 @@
>  #include <rte_cryptodev.h>
> 
>  /*
> - * Get capabilities list for the device
> - *
> + * Get capabilities list for the device, based on device type
>   */
>  const struct rte_cryptodev_capabilities *
> -otx_get_capabilities(void);
> +otx_get_capabilities(uint64_t flags);
> 
>  #endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */
> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c
> b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> index 88efed3..b59a001 100644
> --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> @@ -105,7 +105,7 @@ otx_cpt_dev_info_get(struct rte_cryptodev *dev, struct
> rte_cryptodev_info *info)
>  	if (info != NULL) {
>  		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
>  		info->feature_flags = dev->feature_flags;
> -		info->capabilities = otx_get_capabilities();
> +		info->capabilities = otx_get_capabilities(info->feature_flags);
>  		info->sym.max_nb_sessions = 0;
>  		info->driver_id = otx_cryptodev_driver_id;
>  		info->min_mbuf_headroom_req =
> OTX_CPT_MIN_HEADROOM_REQ;
> @@ -635,7 +635,8 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
>  	case OTX_CPT_VF_TYPE_AE:
>  		/* Set asymmetric cpt feature flags */
>  		c_dev->feature_flags =
> RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
> -				RTE_CRYPTODEV_FF_HW_ACCELERATED;
> +				RTE_CRYPTODEV_FF_HW_ACCELERATED |
> +				RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
>  		break;
>  	case OTX_CPT_VF_TYPE_SE:
>  		/* Set symmetric cpt feature flags */
> --
> 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 3/8] crypto/octeontx: add asymmetric session operations
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 3/8] crypto/octeontx: add asymmetric session operations Anoob Joseph
@ 2019-10-01 12:57   ` Akhil Goyal
  2019-10-02 11:18     ` Anoob Joseph
  0 siblings, 1 reply; 31+ messages in thread
From: Akhil Goyal @ 2019-10-01 12:57 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Fiona Trahe, Shally Verma, Sunila Sahu, dev

Hi Anoob,

Just a couple of nits

> +
> +static __rte_always_inline void
> +cpt_modex_param_normalize(uint8_t **data, size_t *len)
> +{
> +	size_t i;
> +
> +	/* Strip leading NUL bytes */

Typo NULL

> +
> +	for (i = 0; i < *len; i++) {
> +		if ((*data)[i] != 0)
> +			break;
> +	}
> +
> +	*data += i;
> +	*len -= i;
> +}
> +

<.snip.>

> +static __rte_always_inline void
> +cpt_free_asym_session_parameters(struct cpt_asym_sess_misc *sess)
> +{
> +	struct rte_crypto_modex_xform *mod;
> +	struct rte_crypto_rsa_xform *rsa;
> +
> +	switch (sess->xfrm_type) {
> +	case RTE_CRYPTO_ASYM_XFORM_RSA:
> +		rsa = &sess->rsa_ctx;
> +		if (rsa->n.data)
> +			rte_free(rsa->n.data);
> +		break;
> +	case RTE_CRYPTO_ASYM_XFORM_MODEX:
> +		mod = &sess->mod_ctx;
> +		if (mod->modulus.data)
> +			rte_free(mod->modulus.data);
> +		break;
> +	default:
> +		break;


Do we need an error print here?

> +	}
> +}
> +


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto Anoob Joseph
@ 2019-10-01 13:04   ` Akhil Goyal
  2019-10-02 11:13     ` Anoob Joseph
  0 siblings, 1 reply; 31+ messages in thread
From: Akhil Goyal @ 2019-10-01 13:04 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Fiona Trahe, Shally Verma, Sunila Sahu, dev

Hi Anoob,
> 
> From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> 
> Add helper functions to get meta len for asymmetric operations
> 
> Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> Signed-off-by: Sunila Sahu <ssahu@marvell.com>
> ---

<snip>

> diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> index ad64bf4..0543494 100644
> --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> @@ -412,24 +412,34 @@ otx_cpt_metabuf_mempool_create(const struct
> rte_cryptodev *dev,
>  			       int nb_elements)
>  {
>  	char mempool_name[RTE_MEMPOOL_NAMESIZE];
> -	int sg_mlen, lb_mlen, max_mlen, ret;
>  	struct cpt_qp_meta_info *meta_info;
>  	struct rte_mempool *pool;
> +	int max_mlen = 0;
> +	int sg_mlen = 0;
> +	int lb_mlen = 0;
> +	int ret;
> 
> -	/* Get meta len for scatter gather mode */
> -	sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
> +	if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
> 
> -	/* Extra 32B saved for future considerations */
> -	sg_mlen += 4 * sizeof(uint64_t);
> +		/* Get meta len for scatter gather mode */
> +		sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
> 
> -	/* Get meta len for linear buffer (direct) mode */
> -	lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
> +		/* Extra 32B saved for future considerations */
> +		sg_mlen += 4 * sizeof(uint64_t);
> 
> -	/* Extra 32B saved for future considerations */
> -	lb_mlen += 4 * sizeof(uint64_t);
> +		/* Get meta len for linear buffer (direct) mode */
> +		lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
> 
> -	/* Check max requirement for meta buffer */
> -	max_mlen = RTE_MAX(lb_mlen, sg_mlen);
> +		/* Extra 32B saved for future considerations */
> +		lb_mlen += 4 * sizeof(uint64_t);
> +
> +		/* Check max requirement for meta buffer */
> +		max_mlen = RTE_MAX(lb_mlen, sg_mlen);
> +	} else if (dev->feature_flags &
> RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
> +
> +		/* Get meta len for asymmetric operations */
> +		max_mlen = cpt_pmd_ops_helper_asym_get_mlen();
> +	}

I am not sure how this is working.
In your octeontx device, you will have both RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO
and RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO will be set together. So it will not go in else
in any case.
Please check in rest of the PMD also if this assumption is made somewhere else also.

> 
>  	/* Allocate mempool */
> 
> --
> 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features
  2019-09-09 13:28 ` [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features Anoob Joseph
@ 2019-10-01 13:27   ` Akhil Goyal
  2019-10-02 11:04     ` Anoob Joseph
  0 siblings, 1 reply; 31+ messages in thread
From: Akhil Goyal @ 2019-10-01 13:27 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob, Narayana Prasad, Fiona Trahe,
	Kanaka Durga Kotamarthy, Shally Verma, dev

Hi Anoob,

> 
> From: Sunila Sahu <ssahu@marvell.com>
> 
> Update documentation with supported asymmetric features for octeontx
> 
> Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> Signed-off-by: Sunila Sahu <ssahu@marvell.com>
> ---
>  doc/guides/cryptodevs/features/octeontx.ini |  6 +++++-
>  doc/guides/cryptodevs/octeontx.rst          | 25 +++++++++++++++++++++++++
>  2 files changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/doc/guides/cryptodevs/features/octeontx.ini
> b/doc/guides/cryptodevs/features/octeontx.ini
> index 1735b8f..1c036c5 100644
> --- a/doc/guides/cryptodevs/features/octeontx.ini
> +++ b/doc/guides/cryptodevs/features/octeontx.ini
> @@ -5,11 +5,13 @@
>  ;
>  [Features]
>  Symmetric crypto       = Y
> +Asymmetric crypto      = Y
>  Sym operation chaining = Y
>  HW Accelerated         = Y
>  In Place SGL           = Y
>  OOP SGL In LB  Out     = Y
>  OOP SGL In SGL Out     = Y
> +RSA PRIV OP KEY QT     = Y
> 
>  ;
>  ; Supported crypto algorithms of 'octeontx' crypto driver.
> @@ -64,4 +66,6 @@ AES GCM (256) = Y
>  ;
>  ; Supported Asymmetric algorithms of the 'octeontx' crypto driver.
>  ;
> -[Asymmetric]
> \ No newline at end of file
> +[Asymmetric]
> +RSA                    = Y
> +Modular Exponentiation = Y
> diff --git a/doc/guides/cryptodevs/octeontx.rst
> b/doc/guides/cryptodevs/octeontx.rst
> index 1600a56..a26882b 100644
> --- a/doc/guides/cryptodevs/octeontx.rst
> +++ b/doc/guides/cryptodevs/octeontx.rst
> @@ -53,6 +53,12 @@ AEAD Algorithms
> 
>  * ``RTE_CRYPTO_AEAD_AES_GCM``
> 
> +Asymmetric Crypto Algorithms
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Probably you should have some heading to specify Symmetric crypto Algorithms also.

> +
> +* ``RTE_CRYPTO_ASYM_XFORM_RSA``
> +* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
> +
>  Config flags
>  ------------
> 
> @@ -120,3 +126,22 @@ OCTEON TX crypto PMD.
> 
>          ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
>          "(1,0,0),(0,0,0)" -f ep1.cfg
> +
> +Testing
> +-------
> +
> +The symmetric crypto operations on OCTEON TX crypto PMD may be verified
> by running the test
> +application:
> +
> +.. code-block:: console
> +
> +        ./test
> +        RTE>>cryptodev_octeontx_autotest
> +
> +The asymmetric crypto operations on OCTEON TX crypto PMD may be verified
> by running the test
> +application:
> +
> +.. code-block:: console
> +
> +        ./test
> +        RTE>>cryptodev_octeontx_asym_autotest
> --
> 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities
  2019-10-01 12:38   ` Akhil Goyal
@ 2019-10-02 10:48     ` Anoob Joseph
  2019-10-03  8:03       ` Akhil Goyal
  0 siblings, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-10-02 10:48 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe, Shally Verma,
	Sunila Sahu, dev

Hi Akhil,

Please see inline.

Thanks,
Anoob

> -----Original Message-----
> From: Akhil Goyal <akhil.goyal@nxp.com>
> Sent: Tuesday, October 1, 2019 6:08 PM
> To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>; Jerin Jacob
> Kollanukkaran <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>; Shally Verma
> <shallyv@marvell.com>; Sunila Sahu <ssahu@marvell.com>; dev@dpdk.org
> Subject: RE: [PATCH 2/8] crypto/octeontx: add RSA and modexp asym
> capabilities
> 
> Hi Anoob,
> 
> >  const struct rte_cryptodev_capabilities *
> > -otx_get_capabilities(void)
> > +otx_get_capabilities(uint64_t flags)
> >  {
> > -	return otx_capabilities;
> > +	if (flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
> > +		return otx_asym_capabilities;
> > +	else
> > +		return otx_sym_capabilities;
> > +
> >  }
> 
> I believe this will give Asym capabilities always. As the feature flag
> RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO will always be set, as the flags are
> set in init.
> 
> It will never go in else.

[Anoob] The flags is set based on the type of underlying device. The crypto module on OCTEONTX exposes two kinds of VFs. One which does only symmetric and one which does only asymmetric. Both are never supported together for a VF, and hence the if...else.

From the first patch, crypto/octeontx: add device type mailbox routine

	switch (cptvf->vftype) {
	case OTX_CPT_VF_TYPE_AE:
		/* Set asymmetric cpt feature flags */
		c_dev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
				RTE_CRYPTODEV_FF_HW_ACCELERATED;
		break;
	case OTX_CPT_VF_TYPE_SE:
		/* Set symmetric cpt feature flags */
		c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
				RTE_CRYPTODEV_FF_HW_ACCELERATED |
				RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
				RTE_CRYPTODEV_FF_IN_PLACE_SGL |
				RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
				RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
		break;

Hope this clarifies. 

> 
> > diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > index fc62821..439b50e 100644
> > --- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > +++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > @@ -8,10 +8,9 @@
> >  #include <rte_cryptodev.h>
> >
> >  /*
> > - * Get capabilities list for the device
> > - *
> > + * Get capabilities list for the device, based on device type
> >   */
> >  const struct rte_cryptodev_capabilities *
> > -otx_get_capabilities(void);
> > +otx_get_capabilities(uint64_t flags);
> >
> >  #endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */ diff --git
> > a/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > index 88efed3..b59a001 100644
> > --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > @@ -105,7 +105,7 @@ otx_cpt_dev_info_get(struct rte_cryptodev *dev,
> > struct rte_cryptodev_info *info)
> >  	if (info != NULL) {
> >  		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
> >  		info->feature_flags = dev->feature_flags;
> > -		info->capabilities = otx_get_capabilities();
> > +		info->capabilities = otx_get_capabilities(info->feature_flags);
> >  		info->sym.max_nb_sessions = 0;
> >  		info->driver_id = otx_cryptodev_driver_id;
> >  		info->min_mbuf_headroom_req =
> > OTX_CPT_MIN_HEADROOM_REQ;
> > @@ -635,7 +635,8 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
> >  	case OTX_CPT_VF_TYPE_AE:
> >  		/* Set asymmetric cpt feature flags */
> >  		c_dev->feature_flags =
> > RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
> > -				RTE_CRYPTODEV_FF_HW_ACCELERATED;
> > +				RTE_CRYPTODEV_FF_HW_ACCELERATED |
> > +				RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
> >  		break;
> >  	case OTX_CPT_VF_TYPE_SE:
> >  		/* Set symmetric cpt feature flags */
> > --
> > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features
  2019-10-01 13:27   ` Akhil Goyal
@ 2019-10-02 11:04     ` Anoob Joseph
  2019-10-03  8:01       ` Akhil Goyal
  0 siblings, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-10-02 11:04 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe,
	Kanaka Durga Kotamarthy, Shally Verma, dev

Hi Akhil,

Please see inline.

Thanks,
Anoob

> -----Original Message-----
> From: Akhil Goyal <akhil.goyal@nxp.com>
> Sent: Tuesday, October 1, 2019 6:58 PM
> To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Sunila Sahu <ssahu@marvell.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>; Kanaka Durga
> Kotamarthy <kkotamarthy@marvell.com>; Shally Verma
> <shallyv@marvell.com>; dev@dpdk.org
> Subject: RE: [PATCH 8/8] doc: update octeontx asymmetric features
> 
> Hi Anoob,
> 
> >
> > From: Sunila Sahu <ssahu@marvell.com>
> >
> > Update documentation with supported asymmetric features for octeontx
> >
> > Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> > Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> > Signed-off-by: Sunila Sahu <ssahu@marvell.com>
> > ---
> >  doc/guides/cryptodevs/features/octeontx.ini |  6 +++++-
> >  doc/guides/cryptodevs/octeontx.rst          | 25 +++++++++++++++++++++++++
> >  2 files changed, 30 insertions(+), 1 deletion(-)
> >
> > diff --git a/doc/guides/cryptodevs/features/octeontx.ini
> > b/doc/guides/cryptodevs/features/octeontx.ini
> > index 1735b8f..1c036c5 100644
> > --- a/doc/guides/cryptodevs/features/octeontx.ini
> > +++ b/doc/guides/cryptodevs/features/octeontx.ini
> > @@ -5,11 +5,13 @@
> >  ;
> >  [Features]
> >  Symmetric crypto       = Y
> > +Asymmetric crypto      = Y
> >  Sym operation chaining = Y
> >  HW Accelerated         = Y
> >  In Place SGL           = Y
> >  OOP SGL In LB  Out     = Y
> >  OOP SGL In SGL Out     = Y
> > +RSA PRIV OP KEY QT     = Y
> >
> >  ;
> >  ; Supported crypto algorithms of 'octeontx' crypto driver.
> > @@ -64,4 +66,6 @@ AES GCM (256) = Y
> >  ;
> >  ; Supported Asymmetric algorithms of the 'octeontx' crypto driver.
> >  ;
> > -[Asymmetric]
> > \ No newline at end of file
> > +[Asymmetric]
> > +RSA                    = Y
> > +Modular Exponentiation = Y
> > diff --git a/doc/guides/cryptodevs/octeontx.rst
> > b/doc/guides/cryptodevs/octeontx.rst
> > index 1600a56..a26882b 100644
> > --- a/doc/guides/cryptodevs/octeontx.rst
> > +++ b/doc/guides/cryptodevs/octeontx.rst
> > @@ -53,6 +53,12 @@ AEAD Algorithms
> >
> >  * ``RTE_CRYPTO_AEAD_AES_GCM``
> >
> > +Asymmetric Crypto Algorithms
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 
> Probably you should have some heading to specify Symmetric crypto Algorithms
> also.

[Anoob] Do you recommend adding that change also in this patch or should I submit a separate patch for redesigning that. FYI. For crypto_octeontx2, following is the list we are adding. Do you suggest a similar change there also?

The OCTEON TX2 crypto PMD has support for:

Cipher algorithms:

* ``RTE_CRYPTO_CIPHER_NULL``
* ``RTE_CRYPTO_CIPHER_3DES_CBC``
* ``RTE_CRYPTO_CIPHER_3DES_ECB``
* ``RTE_CRYPTO_CIPHER_AES_CBC``
* ``RTE_CRYPTO_CIPHER_AES_CTR``
* ``RTE_CRYPTO_CIPHER_AES_XTS``
* ``RTE_CRYPTO_CIPHER_DES_CBC``
* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``

Hash algorithms:

* ``RTE_CRYPTO_AUTH_NULL``
* ``RTE_CRYPTO_AUTH_AES_GMAC``
* ``RTE_CRYPTO_AUTH_KASUMI_F9``
* ``RTE_CRYPTO_AUTH_MD5``
* ``RTE_CRYPTO_AUTH_MD5_HMAC``
* ``RTE_CRYPTO_AUTH_SHA1``
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
* ``RTE_CRYPTO_AUTH_SHA224``
* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA384``
* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
* ``RTE_CRYPTO_AUTH_ZUC_EIA3``

AEAD algorithms:

* ``RTE_CRYPTO_AEAD_AES_GCM``
	
Asymmetric algorithms:

* ``RTE_CRYPTO_ASYM_XFORM_RSA``
* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
 
> 
> > +
> > +* ``RTE_CRYPTO_ASYM_XFORM_RSA``
> > +* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
> > +
> >  Config flags
> >  ------------
> >
> > @@ -120,3 +126,22 @@ OCTEON TX crypto PMD.
> >
> >          ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
> >          "(1,0,0),(0,0,0)" -f ep1.cfg
> > +
> > +Testing
> > +-------
> > +
> > +The symmetric crypto operations on OCTEON TX crypto PMD may be verified
> > by running the test
> > +application:
> > +
> > +.. code-block:: console
> > +
> > +        ./test
> > +        RTE>>cryptodev_octeontx_autotest
> > +
> > +The asymmetric crypto operations on OCTEON TX crypto PMD may be
> verified
> > by running the test
> > +application:
> > +
> > +.. code-block:: console
> > +
> > +        ./test
> > +        RTE>>cryptodev_octeontx_asym_autotest
> > --
> > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto
  2019-10-01 13:04   ` Akhil Goyal
@ 2019-10-02 11:13     ` Anoob Joseph
  2019-10-04  7:32       ` Anoob Joseph
  0 siblings, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-10-02 11:13 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe, Shally Verma,
	Sunila Sahu, dev

Hi Akhil,

Please see inline.

Thanks,
Anoob

> -----Original Message-----
> From: Akhil Goyal <akhil.goyal@nxp.com>
> Sent: Tuesday, October 1, 2019 6:35 PM
> To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>; Jerin Jacob
> Kollanukkaran <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>; Shally Verma
> <shallyv@marvell.com>; Sunila Sahu <ssahu@marvell.com>; dev@dpdk.org
> Subject: RE: [PATCH 4/8] common/cpt: add helper functions for asymmetric
> crypto
> 
> Hi Anoob,
> >
> > From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> >
> > Add helper functions to get meta len for asymmetric operations
> >
> > Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> > Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> > Signed-off-by: Sunila Sahu <ssahu@marvell.com>
> > ---
> 
> <snip>
> 
> > diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > index ad64bf4..0543494 100644
> > --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > @@ -412,24 +412,34 @@ otx_cpt_metabuf_mempool_create(const struct
> > rte_cryptodev *dev,
> >  			       int nb_elements)
> >  {
> >  	char mempool_name[RTE_MEMPOOL_NAMESIZE];
> > -	int sg_mlen, lb_mlen, max_mlen, ret;
> >  	struct cpt_qp_meta_info *meta_info;
> >  	struct rte_mempool *pool;
> > +	int max_mlen = 0;
> > +	int sg_mlen = 0;
> > +	int lb_mlen = 0;
> > +	int ret;
> >
> > -	/* Get meta len for scatter gather mode */
> > -	sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
> > +	if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
> >
> > -	/* Extra 32B saved for future considerations */
> > -	sg_mlen += 4 * sizeof(uint64_t);
> > +		/* Get meta len for scatter gather mode */
> > +		sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
> >
> > -	/* Get meta len for linear buffer (direct) mode */
> > -	lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
> > +		/* Extra 32B saved for future considerations */
> > +		sg_mlen += 4 * sizeof(uint64_t);
> >
> > -	/* Extra 32B saved for future considerations */
> > -	lb_mlen += 4 * sizeof(uint64_t);
> > +		/* Get meta len for linear buffer (direct) mode */
> > +		lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
> >
> > -	/* Check max requirement for meta buffer */
> > -	max_mlen = RTE_MAX(lb_mlen, sg_mlen);
> > +		/* Extra 32B saved for future considerations */
> > +		lb_mlen += 4 * sizeof(uint64_t);
> > +
> > +		/* Check max requirement for meta buffer */
> > +		max_mlen = RTE_MAX(lb_mlen, sg_mlen);
> > +	} else if (dev->feature_flags &
> > RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
> > +
> > +		/* Get meta len for asymmetric operations */
> > +		max_mlen = cpt_pmd_ops_helper_asym_get_mlen();
> > +	}
> 
> I am not sure how this is working.
> In your octeontx device, you will have both
> RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO
> and RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO will be set together. So it will
> not go in else in any case.
> Please check in rest of the PMD also if this assumption is made somewhere else
> also.
> 

[Anoob] The crypto VFs on octeontx would be either sym/asym and cannot be both. Hence the above would work. But, you are right. In the above, it should be,

sym_lens = 0;
asym_lens = 0;

If (SYM) {
    /* set various lens for sym */
}

If (ASYM) {
    /* set various lens for asym */
}

len = MAX(sym_len, asym_len);

I'll make the required changes in v2. Hope this clarifies.
 
> >
> >  	/* Allocate mempool */
> >
> > --
> > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 3/8] crypto/octeontx: add asymmetric session operations
  2019-10-01 12:57   ` Akhil Goyal
@ 2019-10-02 11:18     ` Anoob Joseph
  0 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-02 11:18 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe, Shally Verma,
	Sunila Sahu, dev

Hi Akhil,

Please see inline.

Thanks,
Anoob

> -----Original Message-----
> From: Akhil Goyal <akhil.goyal@nxp.com>
> Sent: Tuesday, October 1, 2019 6:27 PM
> To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>; Jerin Jacob
> Kollanukkaran <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>; Shally Verma
> <shallyv@marvell.com>; Sunila Sahu <ssahu@marvell.com>; dev@dpdk.org
> Subject: RE: [PATCH 3/8] crypto/octeontx: add asymmetric session operations
> 
> Hi Anoob,
> 
> Just a couple of nits
> 
> > +
> > +static __rte_always_inline void
> > +cpt_modex_param_normalize(uint8_t **data, size_t *len) {
> > +	size_t i;
> > +
> > +	/* Strip leading NUL bytes */
> 
> Typo NULL

[Anoob] It is intentional.

"NUL is a ASCII character which ascii value is 0 whereas NULL is a macro defined in stddef.h and several more header file with value of ((void *)0)."
 
> 
> > +
> > +	for (i = 0; i < *len; i++) {
> > +		if ((*data)[i] != 0)
> > +			break;
> > +	}
> > +
> > +	*data += i;
> > +	*len -= i;
> > +}
> > +
> 
> <.snip.>
> 
> > +static __rte_always_inline void
> > +cpt_free_asym_session_parameters(struct cpt_asym_sess_misc *sess) {
> > +	struct rte_crypto_modex_xform *mod;
> > +	struct rte_crypto_rsa_xform *rsa;
> > +
> > +	switch (sess->xfrm_type) {
> > +	case RTE_CRYPTO_ASYM_XFORM_RSA:
> > +		rsa = &sess->rsa_ctx;
> > +		if (rsa->n.data)
> > +			rte_free(rsa->n.data);
> > +		break;
> > +	case RTE_CRYPTO_ASYM_XFORM_MODEX:
> > +		mod = &sess->mod_ctx;
> > +		if (mod->modulus.data)
> > +			rte_free(mod->modulus.data);
> > +		break;
> > +	default:
> > +		break;
> 
> 
> Do we need an error print here?

[Anoob] I'll add DP logs here.
 
> 
> > +	}
> > +}
> > +


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features
  2019-10-02 11:04     ` Anoob Joseph
@ 2019-10-03  8:01       ` Akhil Goyal
  0 siblings, 0 replies; 31+ messages in thread
From: Akhil Goyal @ 2019-10-03  8:01 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe,
	Kanaka Durga Kotamarthy, Shally Verma, dev


> >
> > Hi Anoob,
> >
> > >
> > > From: Sunila Sahu <ssahu@marvell.com>
> > >
> > > Update documentation with supported asymmetric features for octeontx
> > >
> > > Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> > > Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> > > Signed-off-by: Sunila Sahu <ssahu@marvell.com>
> > > ---
> > >  doc/guides/cryptodevs/features/octeontx.ini |  6 +++++-
> > >  doc/guides/cryptodevs/octeontx.rst          | 25
> +++++++++++++++++++++++++
> > >  2 files changed, 30 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/doc/guides/cryptodevs/features/octeontx.ini
> > > b/doc/guides/cryptodevs/features/octeontx.ini
> > > index 1735b8f..1c036c5 100644
> > > --- a/doc/guides/cryptodevs/features/octeontx.ini
> > > +++ b/doc/guides/cryptodevs/features/octeontx.ini
> > > @@ -5,11 +5,13 @@
> > >  ;
> > >  [Features]
> > >  Symmetric crypto       = Y
> > > +Asymmetric crypto      = Y
> > >  Sym operation chaining = Y
> > >  HW Accelerated         = Y
> > >  In Place SGL           = Y
> > >  OOP SGL In LB  Out     = Y
> > >  OOP SGL In SGL Out     = Y
> > > +RSA PRIV OP KEY QT     = Y
> > >
> > >  ;
> > >  ; Supported crypto algorithms of 'octeontx' crypto driver.
> > > @@ -64,4 +66,6 @@ AES GCM (256) = Y
> > >  ;
> > >  ; Supported Asymmetric algorithms of the 'octeontx' crypto driver.
> > >  ;
> > > -[Asymmetric]
> > > \ No newline at end of file
> > > +[Asymmetric]
> > > +RSA                    = Y
> > > +Modular Exponentiation = Y
> > > diff --git a/doc/guides/cryptodevs/octeontx.rst
> > > b/doc/guides/cryptodevs/octeontx.rst
> > > index 1600a56..a26882b 100644
> > > --- a/doc/guides/cryptodevs/octeontx.rst
> > > +++ b/doc/guides/cryptodevs/octeontx.rst
> > > @@ -53,6 +53,12 @@ AEAD Algorithms
> > >
> > >  * ``RTE_CRYPTO_AEAD_AES_GCM``
> > >
> > > +Asymmetric Crypto Algorithms
> > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >
> > Probably you should have some heading to specify Symmetric crypto
> Algorithms
> > also.
> 
> [Anoob] Do you recommend adding that change also in this patch or should I
> submit a separate patch for redesigning that. FYI. For crypto_octeontx2,
> following is the list we are adding. Do you suggest a similar change there also?

You can refer to qat.rst.
I believe it will not be a big change and is totally relevant in this patchset, so you can have
That in this patchset.
Yes you should do this in octeontx2 as well.

> 
> The OCTEON TX2 crypto PMD has support for:
> 
> Cipher algorithms:
> 
> * ``RTE_CRYPTO_CIPHER_NULL``
> * ``RTE_CRYPTO_CIPHER_3DES_CBC``
> * ``RTE_CRYPTO_CIPHER_3DES_ECB``
> * ``RTE_CRYPTO_CIPHER_AES_CBC``
> * ``RTE_CRYPTO_CIPHER_AES_CTR``
> * ``RTE_CRYPTO_CIPHER_AES_XTS``
> * ``RTE_CRYPTO_CIPHER_DES_CBC``
> * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
> * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
> * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
> 
> Hash algorithms:
> 
> * ``RTE_CRYPTO_AUTH_NULL``
> * ``RTE_CRYPTO_AUTH_AES_GMAC``
> * ``RTE_CRYPTO_AUTH_KASUMI_F9``
> * ``RTE_CRYPTO_AUTH_MD5``
> * ``RTE_CRYPTO_AUTH_MD5_HMAC``
> * ``RTE_CRYPTO_AUTH_SHA1``
> * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
> * ``RTE_CRYPTO_AUTH_SHA224``
> * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
> * ``RTE_CRYPTO_AUTH_SHA256``
> * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
> * ``RTE_CRYPTO_AUTH_SHA384``
> * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
> * ``RTE_CRYPTO_AUTH_SHA512``
> * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
> * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
> * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
> 
> AEAD algorithms:
> 
> * ``RTE_CRYPTO_AEAD_AES_GCM``
> 
> Asymmetric algorithms:
> 
> * ``RTE_CRYPTO_ASYM_XFORM_RSA``
> * ``RTE_CRYPTO_ASYM_XFORM_MODEX``
> 
> >
> > > +
> > > +* ``RTE_CRYPTO_ASYM_XFORM_RSA``
> > > +* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
> > > +
> > >  Config flags
> > >  ------------
> > >
> > > @@ -120,3 +126,22 @@ OCTEON TX crypto PMD.
> > >
> > >          ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
> > >          "(1,0,0),(0,0,0)" -f ep1.cfg
> > > +
> > > +Testing
> > > +-------
> > > +
> > > +The symmetric crypto operations on OCTEON TX crypto PMD may be
> verified
> > > by running the test
> > > +application:
> > > +
> > > +.. code-block:: console
> > > +
> > > +        ./test
> > > +        RTE>>cryptodev_octeontx_autotest
> > > +
> > > +The asymmetric crypto operations on OCTEON TX crypto PMD may be
> > verified
> > > by running the test
> > > +application:
> > > +
> > > +.. code-block:: console
> > > +
> > > +        ./test
> > > +        RTE>>cryptodev_octeontx_asym_autotest
> > > --
> > > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities
  2019-10-02 10:48     ` Anoob Joseph
@ 2019-10-03  8:03       ` Akhil Goyal
  0 siblings, 0 replies; 31+ messages in thread
From: Akhil Goyal @ 2019-10-03  8:03 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe, Shally Verma,
	Sunila Sahu, dev

> >
> > Hi Anoob,
> >
> > >  const struct rte_cryptodev_capabilities *
> > > -otx_get_capabilities(void)
> > > +otx_get_capabilities(uint64_t flags)
> > >  {
> > > -	return otx_capabilities;
> > > +	if (flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
> > > +		return otx_asym_capabilities;
> > > +	else
> > > +		return otx_sym_capabilities;
> > > +
> > >  }
> >
> > I believe this will give Asym capabilities always. As the feature flag
> > RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO will always be set, as the flags
> are
> > set in init.
> >
> > It will never go in else.
> 
> [Anoob] The flags is set based on the type of underlying device. The crypto
> module on OCTEONTX exposes two kinds of VFs. One which does only
> symmetric and one which does only asymmetric. Both are never supported
> together for a VF, and hence the if...else.

OK probably a comment should be added to avoid this confusion while calling infos_get.
And add this info in doc as well if not already there.

> 
> From the first patch, crypto/octeontx: add device type mailbox routine
> 
> 	switch (cptvf->vftype) {
> 	case OTX_CPT_VF_TYPE_AE:
> 		/* Set asymmetric cpt feature flags */
> 		c_dev->feature_flags =
> RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
> 				RTE_CRYPTODEV_FF_HW_ACCELERATED;
> 		break;
> 	case OTX_CPT_VF_TYPE_SE:
> 		/* Set symmetric cpt feature flags */
> 		c_dev->feature_flags =
> RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
> 				RTE_CRYPTODEV_FF_HW_ACCELERATED |
> 
> 	RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
> 				RTE_CRYPTODEV_FF_IN_PLACE_SGL |
> 				RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
> 				RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
> 		break;
> 
> Hope this clarifies.
> 
> >
> > > diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > > b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > > index fc62821..439b50e 100644
> > > --- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > > +++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
> > > @@ -8,10 +8,9 @@
> > >  #include <rte_cryptodev.h>
> > >
> > >  /*
> > > - * Get capabilities list for the device
> > > - *
> > > + * Get capabilities list for the device, based on device type
> > >   */
> > >  const struct rte_cryptodev_capabilities *
> > > -otx_get_capabilities(void);
> > > +otx_get_capabilities(uint64_t flags);
> > >
> > >  #endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */ diff --git
> > > a/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > > b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > > index 88efed3..b59a001 100644
> > > --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > > +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> > > @@ -105,7 +105,7 @@ otx_cpt_dev_info_get(struct rte_cryptodev *dev,
> > > struct rte_cryptodev_info *info)
> > >  	if (info != NULL) {
> > >  		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
> > >  		info->feature_flags = dev->feature_flags;
> > > -		info->capabilities = otx_get_capabilities();
> > > +		info->capabilities = otx_get_capabilities(info->feature_flags);
> > >  		info->sym.max_nb_sessions = 0;
> > >  		info->driver_id = otx_cryptodev_driver_id;
> > >  		info->min_mbuf_headroom_req =
> > > OTX_CPT_MIN_HEADROOM_REQ;
> > > @@ -635,7 +635,8 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
> > >  	case OTX_CPT_VF_TYPE_AE:
> > >  		/* Set asymmetric cpt feature flags */
> > >  		c_dev->feature_flags =
> > > RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
> > > -				RTE_CRYPTODEV_FF_HW_ACCELERATED;
> > > +				RTE_CRYPTODEV_FF_HW_ACCELERATED |
> > > +				RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
> > >  		break;
> > >  	case OTX_CPT_VF_TYPE_SE:
> > >  		/* Set symmetric cpt feature flags */
> > > --
> > > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto
  2019-10-02 11:13     ` Anoob Joseph
@ 2019-10-04  7:32       ` Anoob Joseph
  0 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-04  7:32 UTC (permalink / raw)
  To: Akhil Goyal
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob Kollanukkaran,
	Narayana Prasad Raju Athreya, Fiona Trahe, Shally Verma,
	Sunila Sahu, dev, Pablo de Lara

Hi Akhil,

Minor correction. Please see inline.

Thanks,
Anoob

> -----Original Message-----
> From: Anoob Joseph
> Sent: Wednesday, October 2, 2019 4:44 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>; Jerin Jacob
> Kollanukkaran <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>; Shally
> Verma <shallyv@marvell.com>; Sunila Sahu <ssahu@marvell.com>;
> dev@dpdk.org
> Subject: RE: [PATCH 4/8] common/cpt: add helper functions for asymmetric
> crypto
> 
> Hi Akhil,
> 
> Please see inline.
> 
> Thanks,
> Anoob
> 
> > -----Original Message-----
> > From: Akhil Goyal <akhil.goyal@nxp.com>
> > Sent: Tuesday, October 1, 2019 6:35 PM
> > To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> > <pablo.de.lara.guarch@intel.com>
> > Cc: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>; Jerin Jacob
> > Kollanukkaran <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> > <pathreya@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>; Shally
> > Verma <shallyv@marvell.com>; Sunila Sahu <ssahu@marvell.com>;
> > dev@dpdk.org
> > Subject: RE: [PATCH 4/8] common/cpt: add helper functions for
> > asymmetric crypto
> >
> > Hi Anoob,
> > >
> > > From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> > >
> > > Add helper functions to get meta len for asymmetric operations
> > >
> > > Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> > > Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
> > > Signed-off-by: Sunila Sahu <ssahu@marvell.com>
> > > ---
> >
> > <snip>
> >
> > > diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > > b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > > index ad64bf4..0543494 100644
> > > --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > > +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
> > > @@ -412,24 +412,34 @@ otx_cpt_metabuf_mempool_create(const
> struct
> > > rte_cryptodev *dev,
> > >  			       int nb_elements)
> > >  {
> > >  	char mempool_name[RTE_MEMPOOL_NAMESIZE];
> > > -	int sg_mlen, lb_mlen, max_mlen, ret;
> > >  	struct cpt_qp_meta_info *meta_info;
> > >  	struct rte_mempool *pool;
> > > +	int max_mlen = 0;
> > > +	int sg_mlen = 0;
> > > +	int lb_mlen = 0;
> > > +	int ret;
> > >
> > > -	/* Get meta len for scatter gather mode */
> > > -	sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
> > > +	if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO)
> {
> > >
> > > -	/* Extra 32B saved for future considerations */
> > > -	sg_mlen += 4 * sizeof(uint64_t);
> > > +		/* Get meta len for scatter gather mode */
> > > +		sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
> > >
> > > -	/* Get meta len for linear buffer (direct) mode */
> > > -	lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
> > > +		/* Extra 32B saved for future considerations */
> > > +		sg_mlen += 4 * sizeof(uint64_t);
> > >
> > > -	/* Extra 32B saved for future considerations */
> > > -	lb_mlen += 4 * sizeof(uint64_t);
> > > +		/* Get meta len for linear buffer (direct) mode */
> > > +		lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
> > >
> > > -	/* Check max requirement for meta buffer */
> > > -	max_mlen = RTE_MAX(lb_mlen, sg_mlen);
> > > +		/* Extra 32B saved for future considerations */
> > > +		lb_mlen += 4 * sizeof(uint64_t);
> > > +
> > > +		/* Check max requirement for meta buffer */
> > > +		max_mlen = RTE_MAX(lb_mlen, sg_mlen);
> > > +	} else if (dev->feature_flags &
> > > RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
> > > +
> > > +		/* Get meta len for asymmetric operations */
> > > +		max_mlen = cpt_pmd_ops_helper_asym_get_mlen();
> > > +	}
> >
> > I am not sure how this is working.
> > In your octeontx device, you will have both
> > RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO
> > and RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO will be set together. So it
> will
> > not go in else in any case.
> > Please check in rest of the PMD also if this assumption is made
> > somewhere else also.
> >
> 
> [Anoob] The crypto VFs on octeontx would be either sym/asym and cannot
> be both. Hence the above would work. But, you are right. In the above, it
> should be,
> 
> sym_lens = 0;
> asym_lens = 0;
> 
> If (SYM) {
>     /* set various lens for sym */
> }
> 
> If (ASYM) {
>     /* set various lens for asym */
> }
> 
> len = MAX(sym_len, asym_len);
> 
> I'll make the required changes in v2. Hope this clarifies.

[Anoob] The above code snippet is only applicable for crypto_octeontx PMD. And hence the current code should be fine. Initially, I mistook that the suggestion was for a common routine. Nevertheless, I'll add a comment stating that only one feature is supported. 
 
> 
> > >
> > >  	/* Allocate mempool */
> > >
> > > --
> > > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD
  2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
                   ` (8 preceding siblings ...)
  2019-09-09 15:51 ` [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Shally Verma
@ 2019-10-11 13:01 ` " Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 1/5] crypto/octeontx: add device type mailbox routine Anoob Joseph
                     ` (5 more replies)
  9 siblings, 6 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-11 13:01 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Anoob Joseph, Jerin Jacob, Narayana Prasad,
	Kanaka Durga Kotamarthy, Sunila Sahu, Shally Verma, Fiona Trahe,
	dev

This series adds asymmetric crypto support in 'crypto_octoentx' PMD.

Changes in v2:
* Squashed patches as directed by Akhil
* Split the doc patch and added documentation along with feature
* Added check for ASYM SESSIONLESS (not supported currently)
* Made separate enqueue & dequeue routines for sym & asym
* Minor updates to documentation

Kanaka Durga Kotamarthy (3):
  crypto/octeontx: add device type mailbox routine
  crypto/octeontx: add asymmetric session operations
  common/cpt: add helper functions for asymmetric crypto

Sunila Sahu (2):
  crypto/octeontx: add asymmetric enqueue/dequeue ops
  app/test: register octeontx PMD to asym testsuite

 app/test/test_cryptodev_asym.c                     |  31 ++
 doc/guides/cryptodevs/features/octeontx.ini        |   6 +-
 doc/guides/cryptodevs/octeontx.rst                 |  29 +-
 drivers/common/cpt/cpt_common.h                    |   4 +-
 drivers/common/cpt/cpt_mcode_defines.h             |  29 ++
 drivers/common/cpt/cpt_pmd_ops_helper.c            |  15 +
 drivers/common/cpt/cpt_pmd_ops_helper.h            |   9 +
 drivers/common/cpt/cpt_ucode_asym.h                | 453 +++++++++++++++++++++
 drivers/common/cpt/rte_common_cpt_version.map      |   8 +
 .../crypto/octeontx/otx_cryptodev_capabilities.c   |  47 ++-
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |   5 +-
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  51 ++-
 drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  26 +-
 drivers/crypto/octeontx/otx_cryptodev_mbox.h       |  20 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c        | 338 +++++++++++++--
 drivers/crypto/octeontx/otx_cryptodev_ops.h        |   2 +
 16 files changed, 1016 insertions(+), 57 deletions(-)
 create mode 100644 drivers/common/cpt/cpt_ucode_asym.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH v2 1/5] crypto/octeontx: add device type mailbox routine
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
@ 2019-10-11 13:01   ` Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 2/5] crypto/octeontx: add asymmetric session operations Anoob Joseph
                     ` (4 subsequent siblings)
  5 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-11 13:01 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Sunila Sahu, Shally Verma, Fiona Trahe, dev, Anoob Joseph

From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>

Add mailbox communication to query symmetric or asymmetric device type

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/common/cpt/cpt_common.h                   |  3 ---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 12 ++++-----
 drivers/crypto/octeontx/otx_cryptodev_mbox.c      | 26 ++++++++++++++++--
 drivers/crypto/octeontx/otx_cryptodev_mbox.h      | 20 ++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 33 ++++++++++++++++++-----
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  2 ++
 6 files changed, 78 insertions(+), 18 deletions(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 32f23ac..7ef6b29 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -19,9 +19,6 @@
 #define CPT_COUNT_THOLD		32
 #define CPT_TIMER_THOLD		0x3F
 
-#define AE_TYPE 1
-#define SE_TYPE 2
-
 #ifndef ROUNDUP4
 #define ROUNDUP4(val)	(((val) + 3) & 0xfffffffc)
 #endif
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index eba6293..ad64bf4 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -386,6 +386,12 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
 		return -1;
 	}
 
+	/* Gets device type */
+	if (otx_cpt_get_dev_type(cptvf)) {
+		CPT_LOG_ERR("Failed to get device type");
+		return -1;
+	}
+
 	return 0;
 }
 
@@ -653,12 +659,6 @@ otx_cpt_start_device(void *dev)
 		return -EFAULT;
 	}
 
-	if ((cptvf->vftype != SE_TYPE) && (cptvf->vftype != AE_TYPE)) {
-		CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF "
-			    "device %s", cptvf->vftype, cptvf->dev_name);
-		return -ENOENT;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.c b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
index daba776..a884ad6 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
@@ -42,11 +42,19 @@ otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf)
 	case OTX_CPT_MSG_QBIND_GRP:
 		cptvf->pf_acked = true;
 		cptvf->vftype = mbx.data;
-		CPT_LOG_DP_DEBUG("%s: VF %d type %s group %d",
+		CPT_LOG_DP_DEBUG("%s: VF %d group %d",
 				 cptvf->dev_name, cptvf->vfid,
-				 ((mbx.data == SE_TYPE) ? "SE" : "AE"),
 				 cptvf->vfgrp);
 		break;
+	case OTX_CPT_MSG_PF_TYPE:
+		cptvf->pf_acked = true;
+		if (mbx.data == OTX_CPT_PF_TYPE_AE)
+			cptvf->vftype = OTX_CPT_VF_TYPE_AE;
+		else if (mbx.data == OTX_CPT_PF_TYPE_SE)
+			cptvf->vftype = OTX_CPT_VF_TYPE_SE;
+		else
+			cptvf->vftype = OTX_CPT_VF_TYPE_INVALID;
+		break;
 	case OTX_CPT_MBOX_MSG_TYPE_ACK:
 		cptvf->pf_acked = true;
 		break;
@@ -120,6 +128,20 @@ otx_cpt_check_pf_ready(struct cpt_vf *cptvf)
 }
 
 int
+otx_cpt_get_dev_type(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_PF_TYPE;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to query msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
 otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf)
 {
 	struct cpt_mbox mbx = {0, 0};
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.h b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
index 2d2e0e6..508f3af 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
@@ -23,6 +23,20 @@ struct cpt_mbox {
 	uint64_t data;
 };
 
+/* CPT PF types */
+enum otx_cpt_pf_type {
+	OTX_CPT_PF_TYPE_INVALID = 0,
+	OTX_CPT_PF_TYPE_AE = 2,
+	OTX_CPT_PF_TYPE_SE,
+};
+
+/* CPT VF types */
+enum otx_cpt_vf_type {
+	OTX_CPT_VF_TYPE_AE = 1,
+	OTX_CPT_VF_TYPE_SE,
+	OTX_CPT_VF_TYPE_INVALID,
+};
+
 /* PF-VF message opcodes */
 enum otx_cpt_mbox_opcode {
 	OTX_CPT_MSG_VF_UP = 1,
@@ -63,6 +77,12 @@ int
 otx_cpt_check_pf_ready(struct cpt_vf *cptvf);
 
 /*
+ * Communicate to PF to get VF type
+ */
+int
+otx_cpt_get_dev_type(struct cpt_vf *cptvf);
+
+/*
  * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.
  * Must be ACKed.
  */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 118168a..4c6e266 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -13,6 +13,7 @@
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_capabilities.h"
 #include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
 #include "otx_cryptodev_ops.h"
 
 #include "cpt_pmd_logs.h"
@@ -630,6 +631,28 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 		goto fail;
 	}
 
+	switch (cptvf->vftype) {
+	case OTX_CPT_VF_TYPE_AE:
+		/* Set asymmetric cpt feature flags */
+		c_dev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+				RTE_CRYPTODEV_FF_HW_ACCELERATED;
+		break;
+	case OTX_CPT_VF_TYPE_SE:
+		/* Set symmetric cpt feature flags */
+		c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+				RTE_CRYPTODEV_FF_HW_ACCELERATED |
+				RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
+				RTE_CRYPTODEV_FF_IN_PLACE_SGL |
+				RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
+				RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
+		break;
+	default:
+		/* Feature not supported. Abort */
+		CPT_LOG_ERR("VF type not supported by %s", dev_name);
+		ret = -EIO;
+		goto deinit_dev;
+	}
+
 	/* Start off timer for mailbox interrupts */
 	otx_cpt_periodic_alarm_start(cptvf);
 
@@ -638,18 +661,14 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
 	c_dev->dequeue_burst = otx_cpt_pkt_dequeue;
 
-	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
-			RTE_CRYPTODEV_FF_HW_ACCELERATED |
-			RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
-			RTE_CRYPTODEV_FF_IN_PLACE_SGL |
-			RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
-			RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
-
 	/* Save dev private data */
 	c_dev->data->dev_private = cptvf;
 
 	return 0;
 
+deinit_dev:
+	otx_cpt_deinit_device(cptvf);
+
 fail:
 	if (cptvf) {
 		/* Free private data allocated */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index 768ec4f..fac8a3c 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,8 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+#include <rte_cryptodev.h>
+
 #define OTX_CPT_MIN_HEADROOM_REQ	(24)
 #define OTX_CPT_MIN_TAILROOM_REQ	(8)
 #define CPT_NUM_QS_PER_VF		(1)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH v2 2/5] crypto/octeontx: add asymmetric session operations
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 1/5] crypto/octeontx: add device type mailbox routine Anoob Joseph
@ 2019-10-11 13:01   ` Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 3/5] common/cpt: add helper functions for asymmetric crypto Anoob Joseph
                     ` (3 subsequent siblings)
  5 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-11 13:01 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Sunila Sahu, Shally Verma, Fiona Trahe, dev, Anoob Joseph

From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>

Add asymmetric session setup and free functions. RSA and modexp
operations are supported.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 doc/guides/cryptodevs/features/octeontx.ini        |   6 +-
 doc/guides/cryptodevs/octeontx.rst                 |  10 +-
 drivers/common/cpt/cpt_mcode_defines.h             |   9 ++
 drivers/common/cpt/cpt_ucode_asym.h                | 171 +++++++++++++++++++++
 .../crypto/octeontx/otx_cryptodev_capabilities.c   |  47 +++++-
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |   5 +-
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |  71 ++++++++-
 7 files changed, 307 insertions(+), 12 deletions(-)
 create mode 100644 drivers/common/cpt/cpt_ucode_asym.h

diff --git a/doc/guides/cryptodevs/features/octeontx.ini b/doc/guides/cryptodevs/features/octeontx.ini
index 1735b8f..1c036c5 100644
--- a/doc/guides/cryptodevs/features/octeontx.ini
+++ b/doc/guides/cryptodevs/features/octeontx.ini
@@ -5,11 +5,13 @@
 ;
 [Features]
 Symmetric crypto       = Y
+Asymmetric crypto      = Y
 Sym operation chaining = Y
 HW Accelerated         = Y
 In Place SGL           = Y
 OOP SGL In LB  Out     = Y
 OOP SGL In SGL Out     = Y
+RSA PRIV OP KEY QT     = Y
 
 ;
 ; Supported crypto algorithms of 'octeontx' crypto driver.
@@ -64,4 +66,6 @@ AES GCM (256) = Y
 ;
 ; Supported Asymmetric algorithms of the 'octeontx' crypto driver.
 ;
-[Asymmetric]
\ No newline at end of file
+[Asymmetric]
+RSA                    = Y
+Modular Exponentiation = Y
diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst
index 1600a56..8f8126b 100644
--- a/doc/guides/cryptodevs/octeontx.rst
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -10,8 +10,8 @@ cryptographic operations to cryptographic accelerator units on
 poll mode driver enqueues the crypto request to this accelerator and dequeues
 the response once the operation is completed.
 
-Supported Algorithms
---------------------
+Supported Symmetric Crypto Algorithms
+-------------------------------------
 
 Cipher Algorithms
 ~~~~~~~~~~~~~~~~~
@@ -53,6 +53,12 @@ AEAD Algorithms
 
 * ``RTE_CRYPTO_AEAD_AES_GCM``
 
+Supported Asymmetric Crypto Algorithms
+--------------------------------------
+
+* ``RTE_CRYPTO_ASYM_XFORM_RSA``
+* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
+
 Config flags
 ------------
 
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index b7c3feb..d5b3c59 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -6,6 +6,7 @@
 #define _CPT_MCODE_DEFINES_H_
 
 #include <rte_byteorder.h>
+#include <rte_crypto_asym.h>
 #include <rte_memory.h>
 
 /*
@@ -314,6 +315,14 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+struct cpt_asym_sess_misc {
+	enum rte_crypto_asym_xform_type xfrm_type;
+	union {
+		struct rte_crypto_rsa_xform rsa_ctx;
+		struct rte_crypto_modex_xform mod_ctx;
+	};
+};
+
 /* Buffer pointer */
 typedef struct buf_ptr {
 	void *vaddr;
diff --git a/drivers/common/cpt/cpt_ucode_asym.h b/drivers/common/cpt/cpt_ucode_asym.h
new file mode 100644
index 0000000..e0311f1
--- /dev/null
+++ b/drivers/common/cpt/cpt_ucode_asym.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _CPT_UCODE_ASYM_H_
+#define _CPT_UCODE_ASYM_H_
+
+#include <rte_common.h>
+#include <rte_crypto_asym.h>
+#include <rte_malloc.h>
+
+#include "cpt_mcode_defines.h"
+
+static __rte_always_inline void
+cpt_modex_param_normalize(uint8_t **data, size_t *len)
+{
+	size_t i;
+
+	/* Strip leading NUL bytes */
+
+	for (i = 0; i < *len; i++) {
+		if ((*data)[i] != 0)
+			break;
+	}
+
+	*data += i;
+	*len -= i;
+}
+
+static __rte_always_inline int
+cpt_fill_modex_params(struct cpt_asym_sess_misc *sess,
+		      struct rte_crypto_asym_xform *xform)
+{
+	struct rte_crypto_modex_xform *ctx = &sess->mod_ctx;
+	size_t exp_len = xform->modex.exponent.length;
+	size_t mod_len = xform->modex.modulus.length;
+	uint8_t *exp = xform->modex.exponent.data;
+	uint8_t *mod = xform->modex.modulus.data;
+
+	cpt_modex_param_normalize(&mod, &mod_len);
+	cpt_modex_param_normalize(&exp, &exp_len);
+
+	if (unlikely(exp_len == 0 || mod_len == 0))
+		return -EINVAL;
+
+	if (unlikely(exp_len > mod_len)) {
+		CPT_LOG_DP_ERR("Exponent length greater than modulus length is not supported");
+		return -ENOTSUP;
+	}
+
+	/* Allocate buffer to hold modexp params */
+	ctx->modulus.data = rte_malloc(NULL, mod_len + exp_len, 0);
+	if (ctx->modulus.data == NULL) {
+		CPT_LOG_DP_ERR("Could not allocate buffer for modex params");
+		return -ENOMEM;
+	}
+
+	/* Set up modexp prime modulus and private exponent */
+
+	memcpy(ctx->modulus.data, mod, mod_len);
+	ctx->exponent.data = ctx->modulus.data + mod_len;
+	memcpy(ctx->exponent.data, exp, exp_len);
+
+	ctx->modulus.length = mod_len;
+	ctx->exponent.length = exp_len;
+
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_fill_rsa_params(struct cpt_asym_sess_misc *sess,
+		    struct rte_crypto_asym_xform *xform)
+{
+	struct rte_crypto_rsa_priv_key_qt qt = xform->rsa.qt;
+	struct rte_crypto_rsa_xform *xfrm_rsa = &xform->rsa;
+	struct rte_crypto_rsa_xform *rsa = &sess->rsa_ctx;
+	size_t mod_len = xfrm_rsa->n.length;
+	size_t exp_len = xfrm_rsa->e.length;
+	uint64_t total_size;
+	size_t len = 0;
+
+	/* Make sure key length used is not more than mod_len/2 */
+	if (qt.p.data != NULL)
+		len = (((mod_len / 2) < qt.p.length) ? len : qt.p.length);
+
+	/* Total size required for RSA key params(n,e,(q,dQ,p,dP,qInv)) */
+	total_size = mod_len + exp_len + 5 * len;
+
+	/* Allocate buffer to hold all RSA keys */
+	rsa->n.data = rte_malloc(NULL, total_size, 0);
+	if (rsa->n.data == NULL) {
+		CPT_LOG_DP_ERR("Could not allocate buffer for RSA keys");
+		return -ENOMEM;
+	}
+
+	/* Set up RSA prime modulus and public key exponent */
+	memcpy(rsa->n.data, xfrm_rsa->n.data, mod_len);
+	rsa->e.data = rsa->n.data + mod_len;
+	memcpy(rsa->e.data, xfrm_rsa->e.data, exp_len);
+
+	/* Private key in quintuple format */
+	if (len != 0) {
+		rsa->qt.q.data = rsa->e.data + exp_len;
+		memcpy(rsa->qt.q.data, qt.q.data, qt.q.length);
+		rsa->qt.dQ.data = rsa->qt.q.data + qt.q.length;
+		memcpy(rsa->qt.dQ.data, qt.dQ.data, qt.dQ.length);
+		rsa->qt.p.data = rsa->qt.dQ.data + qt.dQ.length;
+		memcpy(rsa->qt.p.data, qt.p.data, qt.p.length);
+		rsa->qt.dP.data = rsa->qt.p.data + qt.p.length;
+		memcpy(rsa->qt.dP.data, qt.dP.data, qt.dP.length);
+		rsa->qt.qInv.data = rsa->qt.dP.data + qt.dP.length;
+		memcpy(rsa->qt.qInv.data, qt.qInv.data, qt.qInv.length);
+
+		rsa->qt.q.length = qt.q.length;
+		rsa->qt.dQ.length = qt.dQ.length;
+		rsa->qt.p.length = qt.p.length;
+		rsa->qt.dP.length = qt.dP.length;
+		rsa->qt.qInv.length = qt.qInv.length;
+	}
+	rsa->n.length = mod_len;
+	rsa->e.length = exp_len;
+
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_fill_asym_session_parameters(struct cpt_asym_sess_misc *sess,
+				 struct rte_crypto_asym_xform *xform)
+{
+	int ret;
+
+	sess->xfrm_type = xform->xform_type;
+
+	switch (xform->xform_type) {
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		ret = cpt_fill_rsa_params(sess, xform);
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		ret = cpt_fill_modex_params(sess, xform);
+		break;
+	default:
+		CPT_LOG_DP_ERR("Unsupported transform type");
+		return -ENOTSUP;
+	}
+	return ret;
+}
+
+static __rte_always_inline void
+cpt_free_asym_session_parameters(struct cpt_asym_sess_misc *sess)
+{
+	struct rte_crypto_modex_xform *mod;
+	struct rte_crypto_rsa_xform *rsa;
+
+	switch (sess->xfrm_type) {
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		rsa = &sess->rsa_ctx;
+		if (rsa->n.data)
+			rte_free(rsa->n.data);
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		mod = &sess->mod_ctx;
+		if (mod->modulus.data)
+			rte_free(mod->modulus.data);
+		break;
+	default:
+		CPT_LOG_DP_ERR("Invalid transform type");
+		break;
+	}
+}
+
+#endif /* _CPT_UCODE_ASYM_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
index c6d94c9..8c0358f 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
@@ -6,7 +6,7 @@
 
 #include "otx_cryptodev_capabilities.h"
 
-static const struct rte_cryptodev_capabilities otx_capabilities[] = {
+static const struct rte_cryptodev_capabilities otx_sym_capabilities[] = {
 	/* Symmetric capabilities */
 	{	/* NULL (AUTH) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -597,8 +597,49 @@ static const struct rte_cryptodev_capabilities otx_capabilities[] = {
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
+static const struct rte_cryptodev_capabilities otx_asym_capabilities[] = {
+	/* Asymmetric capabilities */
+	{	/* RSA */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
+				.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+					(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+					(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+					(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+				{.modlen = {
+					.min = 17,
+					.max = 1024,
+					.increment = 1
+				}, }
+			}
+		}, }
+	},
+	{	/* MOD_EXP */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
+				.op_types = 0,
+				{.modlen = {
+					.min = 17,
+					.max = 1024,
+					.increment = 1
+				}, }
+			}
+		}, }
+	},
+	/* End of asymmetric capabilities */
+	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
 const struct rte_cryptodev_capabilities *
-otx_get_capabilities(void)
+otx_get_capabilities(uint64_t flags)
 {
-	return otx_capabilities;
+	if (flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
+		return otx_asym_capabilities;
+	else
+		return otx_sym_capabilities;
+
 }
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
index fc62821..439b50e 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
@@ -8,10 +8,9 @@
 #include <rte_cryptodev.h>
 
 /*
- * Get capabilities list for the device
- *
+ * Get capabilities list for the device, based on device type
  */
 const struct rte_cryptodev_capabilities *
-otx_get_capabilities(void);
+otx_get_capabilities(uint64_t flags);
 
 #endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 4c6e266..4b58c85 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -18,6 +18,7 @@
 
 #include "cpt_pmd_logs.h"
 #include "cpt_ucode.h"
+#include "cpt_ucode_asym.h"
 
 /* Forward declarations */
 
@@ -105,7 +106,7 @@ otx_cpt_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)
 	if (info != NULL) {
 		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
 		info->feature_flags = dev->feature_flags;
-		info->capabilities = otx_get_capabilities();
+		info->capabilities = otx_get_capabilities(info->feature_flags);
 		info->sym.max_nb_sessions = 0;
 		info->driver_id = otx_cryptodev_driver_id;
 		info->min_mbuf_headroom_req = OTX_CPT_MIN_HEADROOM_REQ;
@@ -285,6 +286,65 @@ otx_cpt_session_clear(struct rte_cryptodev *dev,
 	}
 }
 
+static unsigned int
+otx_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
+{
+	return sizeof(struct cpt_asym_sess_misc);
+}
+
+static int
+otx_cpt_asym_session_cfg(struct rte_cryptodev *dev,
+			 struct rte_crypto_asym_xform *xform __rte_unused,
+			 struct rte_cryptodev_asym_session *sess,
+			 struct rte_mempool *pool)
+{
+	struct cpt_asym_sess_misc *priv;
+	int ret;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (rte_mempool_get(pool, (void **)&priv)) {
+		CPT_LOG_ERR("Could not allocate session private data");
+		return -ENOMEM;
+	}
+
+	memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
+
+	ret = cpt_fill_asym_session_parameters(priv, xform);
+	if (ret) {
+		CPT_LOG_ERR("Could not configure session parameters");
+
+		/* Return session to mempool */
+		rte_mempool_put(pool, priv);
+		return ret;
+	}
+
+	set_asym_session_private_data(sess, dev->driver_id, priv);
+	return 0;
+}
+
+static void
+otx_cpt_asym_session_clear(struct rte_cryptodev *dev,
+			   struct rte_cryptodev_asym_session *sess)
+{
+	struct cpt_asym_sess_misc *priv;
+	struct rte_mempool *sess_mp;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	priv = get_asym_session_private_data(sess, dev->driver_id);
+
+	if (priv == NULL)
+		return;
+
+	/* Free resources allocated during session configure */
+	cpt_free_asym_session_parameters(priv);
+	memset(priv, 0, otx_cpt_asym_session_size_get(dev));
+	sess_mp = rte_mempool_from_obj(priv);
+	set_asym_session_private_data(sess, dev->driver_id, NULL);
+	rte_mempool_put(sess_mp, priv);
+}
+
 static __rte_always_inline int32_t __hot
 otx_cpt_request_enqueue(struct cpt_instance *instance,
 			struct pending_queue *pqueue,
@@ -584,7 +644,11 @@ static struct rte_cryptodev_ops cptvf_ops = {
 	/* Crypto related operations */
 	.sym_session_get_size = otx_cpt_get_session_size,
 	.sym_session_configure = otx_cpt_session_cfg,
-	.sym_session_clear = otx_cpt_session_clear
+	.sym_session_clear = otx_cpt_session_clear,
+
+	.asym_session_get_size = otx_cpt_asym_session_size_get,
+	.asym_session_configure = otx_cpt_asym_session_cfg,
+	.asym_session_clear = otx_cpt_asym_session_clear,
 };
 
 int
@@ -635,7 +699,8 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	case OTX_CPT_VF_TYPE_AE:
 		/* Set asymmetric cpt feature flags */
 		c_dev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
-				RTE_CRYPTODEV_FF_HW_ACCELERATED;
+				RTE_CRYPTODEV_FF_HW_ACCELERATED |
+				RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
 		break;
 	case OTX_CPT_VF_TYPE_SE:
 		/* Set symmetric cpt feature flags */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH v2 3/5] common/cpt: add helper functions for asymmetric crypto
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 1/5] crypto/octeontx: add device type mailbox routine Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 2/5] crypto/octeontx: add asymmetric session operations Anoob Joseph
@ 2019-10-11 13:01   ` Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 4/5] crypto/octeontx: add asymmetric enqueue/dequeue ops Anoob Joseph
                     ` (2 subsequent siblings)
  5 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-11 13:01 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Kanaka Durga Kotamarthy, Jerin Jacob, Narayana Prasad,
	Sunila Sahu, Shally Verma, Fiona Trahe, dev, Anoob Joseph

From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>

Add helper functions to get meta len for asymmetric operations

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/common/cpt/cpt_pmd_ops_helper.c           | 15 +++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.h           |  9 ++++++
 drivers/common/cpt/rte_common_cpt_version.map     |  8 +++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 39 ++++++++++++++++-------
 4 files changed, 60 insertions(+), 11 deletions(-)

diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.c b/drivers/common/cpt/cpt_pmd_ops_helper.c
index 1c18180..09b762f 100644
--- a/drivers/common/cpt/cpt_pmd_ops_helper.c
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.c
@@ -11,6 +11,8 @@
 
 #define CPT_MAX_IV_LEN 16
 #define CPT_OFFSET_CONTROL_BYTES 8
+#define CPT_MAX_ASYM_OP_NUM_PARAMS 5
+#define CPT_MAX_ASYM_OP_MOD_LEN 1024
 
 int32_t
 cpt_pmd_ops_helper_get_mlen_direct_mode(void)
@@ -39,3 +41,16 @@ cpt_pmd_ops_helper_get_mlen_sg_mode(void)
 	len += 2 * sizeof(cpt_res_s_t);
 	return len;
 }
+
+int
+cpt_pmd_ops_helper_asym_get_mlen(void)
+{
+	uint32_t len;
+
+	/* Get meta len for linear buffer (direct) mode */
+	len = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+	/* Get meta len for asymmetric operations */
+	len += CPT_MAX_ASYM_OP_NUM_PARAMS * CPT_MAX_ASYM_OP_MOD_LEN;
+	return len;
+}
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.h b/drivers/common/cpt/cpt_pmd_ops_helper.h
index dd32f9a..24c3559 100644
--- a/drivers/common/cpt/cpt_pmd_ops_helper.h
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.h
@@ -31,4 +31,13 @@ cpt_pmd_ops_helper_get_mlen_direct_mode(void);
  */
 int
 cpt_pmd_ops_helper_get_mlen_sg_mode(void);
+
+/*
+ * Get size of meta buffer to be allocated for asymmetric crypto operations
+ *
+ * @return
+ *  - length
+ */
+int
+cpt_pmd_ops_helper_asym_get_mlen(void);
 #endif /* _CPT_PMD_OPS_HELPER_H_ */
diff --git a/drivers/common/cpt/rte_common_cpt_version.map b/drivers/common/cpt/rte_common_cpt_version.map
index dec614f..382ec4b 100644
--- a/drivers/common/cpt/rte_common_cpt_version.map
+++ b/drivers/common/cpt/rte_common_cpt_version.map
@@ -4,3 +4,11 @@ DPDK_18.11 {
 	cpt_pmd_ops_helper_get_mlen_direct_mode;
 	cpt_pmd_ops_helper_get_mlen_sg_mode;
 };
+
+DPDK_19.11 {
+	global:
+
+	cpt_pmd_ops_helper_asym_get_mlen;
+
+	local: *;
+};
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index ad64bf4..ce546c2 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -412,24 +412,41 @@ otx_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
 			       int nb_elements)
 {
 	char mempool_name[RTE_MEMPOOL_NAMESIZE];
-	int sg_mlen, lb_mlen, max_mlen, ret;
 	struct cpt_qp_meta_info *meta_info;
 	struct rte_mempool *pool;
+	int max_mlen = 0;
+	int sg_mlen = 0;
+	int lb_mlen = 0;
+	int ret;
 
-	/* Get meta len for scatter gather mode */
-	sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+	/*
+	 * Calculate metabuf length required. The 'crypto_octeontx' device
+	 * would be either SYMMETRIC or ASYMMETRIC.
+	 */
 
-	/* Extra 32B saved for future considerations */
-	sg_mlen += 4 * sizeof(uint64_t);
+	if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
 
-	/* Get meta len for linear buffer (direct) mode */
-	lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+		/* Get meta len for scatter gather mode */
+		sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
 
-	/* Extra 32B saved for future considerations */
-	lb_mlen += 4 * sizeof(uint64_t);
+		/* Extra 32B saved for future considerations */
+		sg_mlen += 4 * sizeof(uint64_t);
 
-	/* Check max requirement for meta buffer */
-	max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+		/* Get meta len for linear buffer (direct) mode */
+		lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+		/* Extra 32B saved for future considerations */
+		lb_mlen += 4 * sizeof(uint64_t);
+
+		/* Check max requirement for meta buffer */
+		max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+	} else {
+
+		/* Asymmetric device */
+
+		/* Get meta len for asymmetric operations */
+		max_mlen = cpt_pmd_ops_helper_asym_get_mlen();
+	}
 
 	/* Allocate mempool */
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH v2 4/5] crypto/octeontx: add asymmetric enqueue/dequeue ops
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
                     ` (2 preceding siblings ...)
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 3/5] common/cpt: add helper functions for asymmetric crypto Anoob Joseph
@ 2019-10-11 13:01   ` Anoob Joseph
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 5/5] app/test: register octeontx PMD to asym testsuite Anoob Joseph
  2019-10-15 12:46   ` [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD Akhil Goyal
  5 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-11 13:01 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob, Narayana Prasad,
	Kanaka Durga Kotamarthy, Shally Verma, Fiona Trahe, dev,
	Anoob Joseph

From: Sunila Sahu <ssahu@marvell.com>

Add asymmetric crypto op enqueue & dequeue routines

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 drivers/common/cpt/cpt_common.h             |   1 +
 drivers/common/cpt/cpt_mcode_defines.h      |  20 ++
 drivers/common/cpt/cpt_ucode_asym.h         | 282 ++++++++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c | 236 +++++++++++++++++++++--
 4 files changed, 522 insertions(+), 17 deletions(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 7ef6b29..dff45f0 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -75,6 +75,7 @@ struct cpt_request_info {
 		uint64_t ei2;
 		uint64_t ei3;
 	} ist;
+	uint8_t *rptr;
 
 	/** Control path fields */
 	uint64_t time_out;
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index d5b3c59..91d30a5 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -21,6 +21,18 @@
 #define CPT_MAJOR_OP_KASUMI	0x38
 #define CPT_MAJOR_OP_MISC	0x01
 
+/* AE opcodes */
+#define CPT_MAJOR_OP_MODEX	0x03
+#define CPT_MINOR_OP_MODEX	0x01
+#define CPT_MINOR_OP_PKCS_ENC	0x02
+#define CPT_MINOR_OP_PKCS_ENC_CRT	0x03
+#define CPT_MINOR_OP_PKCS_DEC	0x04
+#define CPT_MINOR_OP_PKCS_DEC_CRT	0x05
+#define CPT_MINOR_OP_MODEX_CRT	0x06
+
+#define CPT_BLOCK_TYPE1 0
+#define CPT_BLOCK_TYPE2 1
+
 #define CPT_BYTE_16		16
 #define CPT_BYTE_24		24
 #define CPT_BYTE_32		32
@@ -367,6 +379,14 @@ typedef struct fc_params {
 } fc_params_t;
 
 /*
+ * Parameters for asymmetric operations
+ */
+struct asym_op_params {
+	struct cpt_request_info *req;
+	phys_addr_t meta_buf;
+};
+
+/*
  * Parameters for digest
  * generate requests
  * Only src_iov, op, ctx_buf, mac_buf, prep_req
diff --git a/drivers/common/cpt/cpt_ucode_asym.h b/drivers/common/cpt/cpt_ucode_asym.h
index e0311f1..00e01b5 100644
--- a/drivers/common/cpt/cpt_ucode_asym.h
+++ b/drivers/common/cpt/cpt_ucode_asym.h
@@ -9,6 +9,8 @@
 #include <rte_crypto_asym.h>
 #include <rte_malloc.h>
 
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
 #include "cpt_mcode_defines.h"
 
 static __rte_always_inline void
@@ -168,4 +170,284 @@ cpt_free_asym_session_parameters(struct cpt_asym_sess_misc *sess)
 	}
 }
 
+static __rte_always_inline void
+cpt_fill_req_comp_addr(struct cpt_request_info *req, buf_ptr_t addr)
+{
+	void *completion_addr = RTE_PTR_ALIGN(addr.vaddr, 16);
+
+	/* Pointer to cpt_res_s, updated by CPT */
+	req->completion_addr = (volatile uint64_t *)completion_addr;
+	req->comp_baddr = addr.dma_addr +
+			  RTE_PTR_DIFF(completion_addr, addr.vaddr);
+	*(req->completion_addr) = COMPLETION_CODE_INIT;
+}
+
+static __rte_always_inline int
+cpt_modex_prep(struct asym_op_params *modex_params,
+	       struct rte_crypto_modex_xform *mod)
+{
+	struct cpt_request_info *req = modex_params->req;
+	phys_addr_t mphys = modex_params->meta_buf;
+	uint32_t exp_len = mod->exponent.length;
+	uint32_t mod_len = mod->modulus.length;
+	struct rte_crypto_mod_op_param mod_op;
+	struct rte_crypto_op **op;
+	vq_cmd_word0_t vq_cmd_w0;
+	uint64_t total_key_len;
+	opcode_info_t opcode;
+	uint32_t dlen, rlen;
+	uint32_t base_len;
+	buf_ptr_t caddr;
+	uint8_t *dptr;
+
+	/* Extracting modex op form params->req->op[1]->asym->modex */
+	op = RTE_PTR_ADD(req->op, sizeof(uintptr_t));
+	mod_op = ((struct rte_crypto_op *)*op)->asym->modex;
+
+	base_len = mod_op.base.length;
+	if (unlikely(base_len > mod_len)) {
+		CPT_LOG_DP_ERR("Base length greater than modulus length is not supported");
+		(*op)->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		return -ENOTSUP;
+	}
+
+	total_key_len = mod_len + exp_len;
+
+	/* Input buffer */
+	dptr = RTE_PTR_ADD(req, sizeof(struct cpt_request_info));
+	memcpy(dptr, mod->modulus.data, total_key_len);
+	dptr += total_key_len;
+	memcpy(dptr, mod_op.base.data, base_len);
+	dptr += base_len;
+	dlen = total_key_len + base_len;
+
+	/* Result buffer */
+	rlen = mod_len;
+
+	/* Setup opcodes */
+	opcode.s.major = CPT_MAJOR_OP_MODEX;
+	opcode.s.minor = CPT_MINOR_OP_MODEX;
+	vq_cmd_w0.s.opcode = opcode.flags;
+
+	/* GP op header */
+	vq_cmd_w0.s.param1 = mod_len;
+	vq_cmd_w0.s.param2 = exp_len;
+	vq_cmd_w0.s.dlen = dlen;
+
+	/* Filling cpt_request_info structure */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei1 = mphys;
+	req->ist.ei2 = mphys + dlen;
+
+	/* Result pointer to store result data */
+	req->rptr = dptr;
+
+	/* alternate_caddr to write completion status of the microcode */
+	req->alternate_caddr = (uint64_t *)(dptr + rlen);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+
+	/* Preparing completion addr, +1 for completion code */
+	caddr.vaddr = dptr + rlen + 1;
+	caddr.dma_addr = mphys + dlen + rlen + 1;
+
+	cpt_fill_req_comp_addr(req, caddr);
+	return 0;
+}
+
+static __rte_always_inline void
+cpt_rsa_prep(struct asym_op_params *rsa_params,
+	     struct rte_crypto_rsa_xform *rsa,
+	     rte_crypto_param *crypto_param)
+{
+	struct cpt_request_info *req = rsa_params->req;
+	phys_addr_t mphys = rsa_params->meta_buf;
+	struct rte_crypto_rsa_op_param rsa_op;
+	uint32_t mod_len = rsa->n.length;
+	uint32_t exp_len = rsa->e.length;
+	struct rte_crypto_op **op;
+	vq_cmd_word0_t vq_cmd_w0;
+	uint64_t total_key_len;
+	opcode_info_t opcode;
+	uint32_t dlen, rlen;
+	uint32_t in_size;
+	buf_ptr_t caddr;
+	uint8_t *dptr;
+
+	/* Extracting rsa op form params->req->op[1]->asym->rsa */
+	op = RTE_PTR_ADD(req->op, sizeof(uintptr_t));
+	rsa_op = ((struct rte_crypto_op *)*op)->asym->rsa;
+	total_key_len  = mod_len + exp_len;
+
+	/* Input buffer */
+	dptr = RTE_PTR_ADD(req, sizeof(struct cpt_request_info));
+	memcpy(dptr, rsa->n.data, total_key_len);
+	dptr += total_key_len;
+
+	in_size = crypto_param->length;
+	memcpy(dptr, crypto_param->data, in_size);
+
+	dptr += in_size;
+	dlen = total_key_len + in_size;
+
+	/* Result buffer */
+	rlen = mod_len;
+
+	if (rsa_op.pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+		/* Use mod_exp operation for no_padding type */
+		opcode.s.minor = CPT_MINOR_OP_MODEX;
+		vq_cmd_w0.s.param2 = exp_len;
+	} else {
+		if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_ENC;
+			/* Public key encrypt, use BT2*/
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE2 |
+					((uint16_t)(exp_len) << 1);
+		} else if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_VERIFY) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_DEC;
+			/* Public key decrypt, use BT1 */
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE1;
+			/* + 2 for decrypted len */
+			rlen += 2;
+		}
+	}
+
+	/* Setup opcodes */
+	opcode.s.major = CPT_MAJOR_OP_MODEX;
+	vq_cmd_w0.s.opcode = opcode.flags;
+
+	/* GP op header */
+	vq_cmd_w0.s.param1 = mod_len;
+	vq_cmd_w0.s.dlen = dlen;
+
+	/* Filling cpt_request_info structure */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei1 = mphys;
+	req->ist.ei2 = mphys + dlen;
+
+	/* Result pointer to store result data */
+	req->rptr = dptr;
+
+	/* alternate_caddr to write completion status of the microcode */
+	req->alternate_caddr = (uint64_t *)(dptr + rlen);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+
+	/* Preparing completion addr, +1 for completion code */
+	caddr.vaddr = dptr + rlen + 1;
+	caddr.dma_addr = mphys + dlen + rlen + 1;
+
+	cpt_fill_req_comp_addr(req, caddr);
+}
+
+static __rte_always_inline void
+cpt_rsa_crt_prep(struct asym_op_params *rsa_params,
+		 struct rte_crypto_rsa_xform *rsa,
+		 rte_crypto_param *crypto_param)
+{
+	struct cpt_request_info *req = rsa_params->req;
+	phys_addr_t mphys = rsa_params->meta_buf;
+	uint32_t qInv_len = rsa->qt.qInv.length;
+	struct rte_crypto_rsa_op_param rsa_op;
+	uint32_t dP_len = rsa->qt.dP.length;
+	uint32_t dQ_len = rsa->qt.dQ.length;
+	uint32_t p_len = rsa->qt.p.length;
+	uint32_t q_len = rsa->qt.q.length;
+	uint32_t mod_len = rsa->n.length;
+	struct rte_crypto_op **op;
+	vq_cmd_word0_t vq_cmd_w0;
+	uint64_t total_key_len;
+	opcode_info_t opcode;
+	uint32_t dlen, rlen;
+	uint32_t in_size;
+	buf_ptr_t caddr;
+	uint8_t *dptr;
+
+	/* Extracting rsa op form params->req->op[1]->asym->rsa */
+	op = RTE_PTR_ADD(req->op, sizeof(uintptr_t));
+	rsa_op = ((struct rte_crypto_op *)*op)->asym->rsa;
+	total_key_len = p_len + q_len + dP_len + dQ_len + qInv_len;
+
+	/* Input buffer */
+	dptr = RTE_PTR_ADD(req, sizeof(struct cpt_request_info));
+	memcpy(dptr, rsa->qt.q.data, total_key_len);
+	dptr += total_key_len;
+
+	in_size = crypto_param->length;
+	memcpy(dptr, crypto_param->data, in_size);
+
+	dptr += in_size;
+	dlen = total_key_len + in_size;
+
+	/* Result buffer */
+	rlen = mod_len;
+
+	if (rsa_op.pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+		/*Use mod_exp operation for no_padding type */
+		opcode.s.minor = CPT_MINOR_OP_MODEX_CRT;
+	} else {
+		if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_SIGN) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_ENC_CRT;
+			/* Private encrypt, use BT1 */
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE1;
+		} else if (rsa_op.op_type == RTE_CRYPTO_ASYM_OP_DECRYPT) {
+			opcode.s.minor = CPT_MINOR_OP_PKCS_DEC_CRT;
+			/* Private decrypt, use BT2 */
+			vq_cmd_w0.s.param2 = CPT_BLOCK_TYPE2;
+			/* + 2 for decrypted len */
+			rlen += 2;
+		}
+	}
+
+	/* Setup opcodes */
+	opcode.s.major = CPT_MAJOR_OP_MODEX;
+	vq_cmd_w0.s.opcode = opcode.flags;
+
+	/* GP op header */
+	vq_cmd_w0.s.param1 = mod_len;
+	vq_cmd_w0.s.dlen = dlen;
+
+	/* Filling cpt_request_info structure */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei1 = mphys;
+	req->ist.ei2 = mphys + dlen;
+
+	/* Result pointer to store result data */
+	req->rptr = dptr;
+
+	/* alternate_caddr to write completion status of the microcode */
+	req->alternate_caddr = (uint64_t *)(dptr + rlen);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+
+	/* Preparing completion addr, +1 for completion code */
+	caddr.vaddr = dptr + rlen + 1;
+	caddr.dma_addr = mphys + dlen + rlen + 1;
+
+	cpt_fill_req_comp_addr(req, caddr);
+}
+
+static __rte_always_inline int __hot
+cpt_enqueue_rsa_op(struct rte_crypto_op *op,
+	       struct asym_op_params *params,
+	       struct cpt_asym_sess_misc *sess)
+{
+	struct rte_crypto_rsa_op_param *rsa = &op->asym->rsa;
+
+	switch (rsa->op_type) {
+	case RTE_CRYPTO_ASYM_OP_VERIFY:
+		cpt_rsa_prep(params, &sess->rsa_ctx, &rsa->sign);
+		break;
+	case RTE_CRYPTO_ASYM_OP_ENCRYPT:
+		cpt_rsa_prep(params, &sess->rsa_ctx, &rsa->message);
+		break;
+	case RTE_CRYPTO_ASYM_OP_SIGN:
+		cpt_rsa_crt_prep(params, &sess->rsa_ctx, &rsa->message);
+		break;
+	case RTE_CRYPTO_ASYM_OP_DECRYPT:
+		cpt_rsa_crt_prep(params, &sess->rsa_ctx, &rsa->cipher);
+		break;
+	default:
+		op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		return -EINVAL;
+	}
+	return 0;
+}
 #endif /* _CPT_UCODE_ASYM_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 4b58c85..ba56b21 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -379,6 +379,74 @@ otx_cpt_request_enqueue(struct cpt_instance *instance,
 }
 
 static __rte_always_inline int __hot
+otx_cpt_enq_single_asym(struct cpt_instance *instance,
+			struct rte_crypto_op *op,
+			struct pending_queue *pqueue)
+{
+	struct cpt_qp_meta_info *minfo = &instance->meta_info;
+	struct rte_crypto_asym_op *asym_op = op->asym;
+	struct asym_op_params params = {0};
+	struct cpt_asym_sess_misc *sess;
+	uintptr_t *cop;
+	void *mdata;
+	int ret;
+
+	if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
+		CPT_LOG_DP_ERR("Could not allocate meta buffer for request");
+		return -ENOMEM;
+	}
+
+	sess = get_asym_session_private_data(asym_op->session,
+					     otx_cryptodev_driver_id);
+
+	/* Store phys_addr of the mdata to meta_buf */
+	params.meta_buf = rte_mempool_virt2iova(mdata);
+
+	cop = mdata;
+	cop[0] = (uintptr_t)mdata;
+	cop[1] = (uintptr_t)op;
+	cop[2] = cop[3] = 0ULL;
+
+	params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
+	params.req->op = cop;
+
+	/* Adjust meta_buf by crypto_op data  and request_info struct */
+	params.meta_buf += (4 * sizeof(uintptr_t)) +
+			   sizeof(struct cpt_request_info);
+
+	switch (sess->xfrm_type) {
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		ret = cpt_modex_prep(&params, &sess->mod_ctx);
+		if (unlikely(ret))
+			goto req_fail;
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		ret = cpt_enqueue_rsa_op(op, &params, sess);
+		if (unlikely(ret))
+			goto req_fail;
+		break;
+	default:
+		op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		ret = -EINVAL;
+		goto req_fail;
+	}
+
+	ret = otx_cpt_request_enqueue(instance, pqueue, params.req);
+
+	if (unlikely(ret)) {
+		CPT_LOG_DP_ERR("Could not enqueue crypto req");
+		goto req_fail;
+	}
+
+	return 0;
+
+req_fail:
+	free_op_meta(mdata, minfo->pool);
+
+	return ret;
+}
+
+static __rte_always_inline int __hot
 otx_cpt_enq_single_sym(struct cpt_instance *instance,
 		       struct rte_crypto_op *op,
 		       struct pending_queue *pqueue)
@@ -477,24 +545,37 @@ otx_cpt_enq_single_sym_sessless(struct cpt_instance *instance,
 	return ret;
 }
 
+#define OP_TYPE_SYM		0
+#define OP_TYPE_ASYM		1
+
 static __rte_always_inline int __hot
 otx_cpt_enq_single(struct cpt_instance *inst,
 		   struct rte_crypto_op *op,
-		   struct pending_queue *pqueue)
+		   struct pending_queue *pqueue,
+		   const uint8_t op_type)
 {
 	/* Check for the type */
 
-	if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
-		return otx_cpt_enq_single_sym(inst, op, pqueue);
-	else if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS))
-		return otx_cpt_enq_single_sym_sessless(inst, op, pqueue);
+	if (op_type == OP_TYPE_SYM) {
+		if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
+			return otx_cpt_enq_single_sym(inst, op, pqueue);
+		else
+			return otx_cpt_enq_single_sym_sessless(inst, op,
+							       pqueue);
+	}
+
+	if (op_type == OP_TYPE_ASYM) {
+		if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
+			return otx_cpt_enq_single_asym(inst, op, pqueue);
+	}
 
 	/* Should not reach here */
-	return -EINVAL;
+	return -ENOTSUP;
 }
 
-static uint16_t
-otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+static  __rte_always_inline uint16_t __hot
+otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,
+		    const uint8_t op_type)
 {
 	struct cpt_instance *instance = (struct cpt_instance *)qptr;
 	uint16_t count;
@@ -510,7 +591,7 @@ otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 	while (likely(count < nb_ops)) {
 
 		/* Enqueue single op */
-		ret = otx_cpt_enq_single(instance, ops[count], pqueue);
+		ret = otx_cpt_enq_single(instance, ops[count], pqueue, op_type);
 
 		if (unlikely(ret))
 			break;
@@ -520,24 +601,128 @@ otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 	return count;
 }
 
-static __rte_always_inline void
-otx_cpt_dequeue_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
+static uint16_t
+otx_cpt_enqueue_asym(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	return otx_cpt_pkt_enqueue(qptr, ops, nb_ops, OP_TYPE_ASYM);
+}
+
+static uint16_t
+otx_cpt_enqueue_sym(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	return otx_cpt_pkt_enqueue(qptr, ops, nb_ops, OP_TYPE_SYM);
+}
+
+static inline void
+otx_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
+		    struct rte_crypto_rsa_xform *rsa_ctx)
+
+{
+	struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
+
+	switch (rsa->op_type) {
+	case RTE_CRYPTO_ASYM_OP_ENCRYPT:
+		rsa->cipher.length = rsa_ctx->n.length;
+		memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
+		break;
+	case RTE_CRYPTO_ASYM_OP_DECRYPT:
+		if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE)
+			rsa->message.length = rsa_ctx->n.length;
+		else {
+			/* Get length of decrypted output */
+			rsa->message.length = rte_cpu_to_be_16
+					(*((uint16_t *)req->rptr));
+
+			/* Offset data pointer by length fields */
+			req->rptr += 2;
+		}
+		memcpy(rsa->message.data, req->rptr, rsa->message.length);
+		break;
+	case RTE_CRYPTO_ASYM_OP_SIGN:
+		rsa->sign.length = rsa_ctx->n.length;
+		memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+		break;
+	case RTE_CRYPTO_ASYM_OP_VERIFY:
+		if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE)
+			rsa->sign.length = rsa_ctx->n.length;
+		else {
+			/* Get length of decrypted output */
+			rsa->sign.length = rte_cpu_to_be_16
+					(*((uint16_t *)req->rptr));
+
+			/* Offset data pointer by length fields */
+			req->rptr += 2;
+		}
+		memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+
+		if (memcmp(rsa->sign.data, rsa->message.data,
+			   rsa->message.length)) {
+			CPT_LOG_DP_ERR("RSA verification failed");
+			cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		}
+		break;
+	default:
+		CPT_LOG_DP_DEBUG("Invalid RSA operation type");
+		cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		break;
+	}
+}
+
+static __rte_always_inline void __hot
+otx_cpt_asym_post_process(struct rte_crypto_op *cop,
+			  struct cpt_request_info *req)
+{
+	struct rte_crypto_asym_op *op = cop->asym;
+	struct cpt_asym_sess_misc *sess;
+
+	sess = get_asym_session_private_data(op->session,
+					     otx_cryptodev_driver_id);
+
+	switch (sess->xfrm_type) {
+	case RTE_CRYPTO_ASYM_XFORM_RSA:
+		otx_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
+		break;
+	case RTE_CRYPTO_ASYM_XFORM_MODEX:
+		op->modex.result.length = sess->mod_ctx.modulus.length;
+		memcpy(op->modex.result.data, req->rptr,
+		       op->modex.result.length);
+		break;
+	default:
+		CPT_LOG_DP_DEBUG("Invalid crypto xform type");
+		cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+		break;
+	}
+}
+
+static __rte_always_inline void __hot
+otx_cpt_dequeue_post_process(struct rte_crypto_op *cop, uintptr_t *rsp,
+			     const uint8_t op_type)
 {
 	/* H/w has returned success */
 	cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 
 	/* Perform further post processing */
 
-	if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
+	if ((op_type == OP_TYPE_SYM) &&
+	    (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 		/* Check if auth verify need to be completed */
 		if (unlikely(rsp[2]))
 			compl_auth_verify(cop, (uint8_t *)rsp[2], rsp[3]);
 		return;
 	}
+
+	if ((op_type == OP_TYPE_ASYM) &&
+	    (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC)) {
+		rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
+		otx_cpt_asym_post_process(cop, (struct cpt_request_info *)rsp);
+	}
+
+	return;
 }
 
-static uint16_t
-otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+static __rte_always_inline uint16_t __hot
+otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,
+		    const uint8_t op_type)
 {
 	struct cpt_instance *instance = (struct cpt_instance *)qptr;
 	struct cpt_request_info *user_req;
@@ -598,7 +783,7 @@ otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 
 		if (likely(cc[i] == 0)) {
 			/* H/w success pkt. Post process */
-			otx_cpt_dequeue_post_process(cop, rsp);
+			otx_cpt_dequeue_post_process(cop, rsp, op_type);
 		} else if (cc[i] == ERR_GC_ICV_MISCOMPARE) {
 			/* auth data mismatch */
 			cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
@@ -627,6 +812,18 @@ otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 	return nb_completed;
 }
 
+static uint16_t
+otx_cpt_dequeue_asym(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	return otx_cpt_pkt_dequeue(qptr, ops, nb_ops, OP_TYPE_ASYM);
+}
+
+static uint16_t
+otx_cpt_dequeue_sym(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	return otx_cpt_pkt_dequeue(qptr, ops, nb_ops, OP_TYPE_SYM);
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -723,8 +920,13 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 
 	c_dev->dev_ops = &cptvf_ops;
 
-	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
-	c_dev->dequeue_burst = otx_cpt_pkt_dequeue;
+	if (c_dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
+		c_dev->enqueue_burst = otx_cpt_enqueue_sym;
+		c_dev->dequeue_burst = otx_cpt_dequeue_sym;
+	} else {
+		c_dev->enqueue_burst = otx_cpt_enqueue_asym;
+		c_dev->dequeue_burst = otx_cpt_dequeue_asym;
+	}
 
 	/* Save dev private data */
 	c_dev->data->dev_private = cptvf;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [dpdk-dev] [PATCH v2 5/5] app/test: register octeontx PMD to asym testsuite
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
                     ` (3 preceding siblings ...)
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 4/5] crypto/octeontx: add asymmetric enqueue/dequeue ops Anoob Joseph
@ 2019-10-11 13:01   ` Anoob Joseph
  2019-10-15 12:46   ` [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD Akhil Goyal
  5 siblings, 0 replies; 31+ messages in thread
From: Anoob Joseph @ 2019-10-11 13:01 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Sunila Sahu, Jerin Jacob, Narayana Prasad,
	Kanaka Durga Kotamarthy, Shally Verma, Fiona Trahe, dev,
	Anoob Joseph

From: Sunila Sahu <ssahu@marvell.com>

Updated asymmetric crypto unit-test application to test
asymmetric crypto operations in octeontx PMD

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
 app/test/test_cryptodev_asym.c     | 31 +++++++++++++++++++++++++++++++
 doc/guides/cryptodevs/octeontx.rst | 19 +++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index e8177e7..241c384 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1791,6 +1791,19 @@ static struct unit_test_suite cryptodev_qat_asym_testsuite  = {
 	}
 };
 
+static struct unit_test_suite cryptodev_octeontx_asym_testsuite  = {
+	.suite_name = "Crypto Device OCTEONTX ASYM Unit Test Suite",
+	.setup = testsuite_setup,
+	.teardown = testsuite_teardown,
+	.unit_test_cases = {
+		TEST_CASE_ST(ut_setup, ut_teardown, test_capability),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_rsa_enc_dec_crt),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_rsa_sign_verify_crt),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_mod_exp),
+		TEST_CASES_END() /**< NULL terminate unit test array */
+	}
+};
+
 static int
 test_cryptodev_openssl_asym(void)
 {
@@ -1823,7 +1836,25 @@ test_cryptodev_qat_asym(void)
 	return unit_test_suite_runner(&cryptodev_qat_asym_testsuite);
 }
 
+static int
+test_cryptodev_octeontx_asym(void)
+{
+	gbl_driver_id = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+	if (gbl_driver_id == -1) {
+		RTE_LOG(ERR, USER1, "OCTEONTX PMD must be loaded. Check if "
+				"CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO is "
+				"enabled in config file to run this "
+				"testsuite.\n");
+		return TEST_FAILED;
+	}
+	return unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);
+}
+
 REGISTER_TEST_COMMAND(cryptodev_openssl_asym_autotest,
 					  test_cryptodev_openssl_asym);
 
 REGISTER_TEST_COMMAND(cryptodev_qat_asym_autotest, test_cryptodev_qat_asym);
+
+REGISTER_TEST_COMMAND(cryptodev_octeontx_asym_autotest,
+					  test_cryptodev_octeontx_asym);
diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst
index 8f8126b..4fa199e 100644
--- a/doc/guides/cryptodevs/octeontx.rst
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -126,3 +126,22 @@ OCTEON TX crypto PMD.
 
         ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
         "(1,0,0),(0,0,0)" -f ep1.cfg
+
+Testing
+-------
+
+The symmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+        ./test
+        RTE>>cryptodev_octeontx_autotest
+
+The asymmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+        ./test
+        RTE>>cryptodev_octeontx_asym_autotest
-- 
2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD
  2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
                     ` (4 preceding siblings ...)
  2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 5/5] app/test: register octeontx PMD to asym testsuite Anoob Joseph
@ 2019-10-15 12:46   ` Akhil Goyal
  2019-10-15 13:31     ` Akhil Goyal
  2019-10-16  4:57     ` Anoob Joseph
  5 siblings, 2 replies; 31+ messages in thread
From: Akhil Goyal @ 2019-10-15 12:46 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Jerin Jacob, Narayana Prasad, Kanaka Durga Kotamarthy,
	Sunila Sahu, Shally Verma, Fiona Trahe, dev

Hi Anoob,

I believe this should also be updated in the release notes.
If yes, please reply to this mail with appropriate description.
I will update it while merging.

> 
> This series adds asymmetric crypto support in 'crypto_octoentx' PMD.
> 
> Changes in v2:
> * Squashed patches as directed by Akhil
> * Split the doc patch and added documentation along with feature
> * Added check for ASYM SESSIONLESS (not supported currently)
> * Made separate enqueue & dequeue routines for sym & asym
> * Minor updates to documentation
> 
> Kanaka Durga Kotamarthy (3):
>   crypto/octeontx: add device type mailbox routine
>   crypto/octeontx: add asymmetric session operations
>   common/cpt: add helper functions for asymmetric crypto
> 
> Sunila Sahu (2):
>   crypto/octeontx: add asymmetric enqueue/dequeue ops
>   app/test: register octeontx PMD to asym testsuite
> 
>  app/test/test_cryptodev_asym.c                     |  31 ++
>  doc/guides/cryptodevs/features/octeontx.ini        |   6 +-
>  doc/guides/cryptodevs/octeontx.rst                 |  29 +-
>  drivers/common/cpt/cpt_common.h                    |   4 +-
>  drivers/common/cpt/cpt_mcode_defines.h             |  29 ++
>  drivers/common/cpt/cpt_pmd_ops_helper.c            |  15 +
>  drivers/common/cpt/cpt_pmd_ops_helper.h            |   9 +
>  drivers/common/cpt/cpt_ucode_asym.h                | 453
> +++++++++++++++++++++
>  drivers/common/cpt/rte_common_cpt_version.map      |   8 +
>  .../crypto/octeontx/otx_cryptodev_capabilities.c   |  47 ++-
>  .../crypto/octeontx/otx_cryptodev_capabilities.h   |   5 +-
>  drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  51 ++-
>  drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  26 +-
>  drivers/crypto/octeontx/otx_cryptodev_mbox.h       |  20 +
>  drivers/crypto/octeontx/otx_cryptodev_ops.c        | 338 +++++++++++++--
>  drivers/crypto/octeontx/otx_cryptodev_ops.h        |   2 +
>  16 files changed, 1016 insertions(+), 57 deletions(-)
>  create mode 100644 drivers/common/cpt/cpt_ucode_asym.h
> 
> --
> 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD
  2019-10-15 12:46   ` [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD Akhil Goyal
@ 2019-10-15 13:31     ` Akhil Goyal
  2019-10-16  4:57     ` Anoob Joseph
  1 sibling, 0 replies; 31+ messages in thread
From: Akhil Goyal @ 2019-10-15 13:31 UTC (permalink / raw)
  To: Akhil Goyal, Anoob Joseph, Pablo de Lara
  Cc: Jerin Jacob, Narayana Prasad, Kanaka Durga Kotamarthy,
	Sunila Sahu, Shally Verma, Fiona Trahe, dev



> 
> Hi Anoob,
> 
> I believe this should also be updated in the release notes.
> If yes, please reply to this mail with appropriate description.
> I will update it while merging.
> 
Please send the release note update. I will squash the change with this patchset.
Applied to dpdk-next-crypto

Thanks.

> >
> > This series adds asymmetric crypto support in 'crypto_octoentx' PMD.
> >
> > Changes in v2:
> > * Squashed patches as directed by Akhil
> > * Split the doc patch and added documentation along with feature
> > * Added check for ASYM SESSIONLESS (not supported currently)
> > * Made separate enqueue & dequeue routines for sym & asym
> > * Minor updates to documentation
> >
> > Kanaka Durga Kotamarthy (3):
> >   crypto/octeontx: add device type mailbox routine
> >   crypto/octeontx: add asymmetric session operations
> >   common/cpt: add helper functions for asymmetric crypto
> >
> > Sunila Sahu (2):
> >   crypto/octeontx: add asymmetric enqueue/dequeue ops
> >   app/test: register octeontx PMD to asym testsuite
> >
> >  app/test/test_cryptodev_asym.c                     |  31 ++
> >  doc/guides/cryptodevs/features/octeontx.ini        |   6 +-
> >  doc/guides/cryptodevs/octeontx.rst                 |  29 +-
> >  drivers/common/cpt/cpt_common.h                    |   4 +-
> >  drivers/common/cpt/cpt_mcode_defines.h             |  29 ++
> >  drivers/common/cpt/cpt_pmd_ops_helper.c            |  15 +
> >  drivers/common/cpt/cpt_pmd_ops_helper.h            |   9 +
> >  drivers/common/cpt/cpt_ucode_asym.h                | 453
> > +++++++++++++++++++++
> >  drivers/common/cpt/rte_common_cpt_version.map      |   8 +
> >  .../crypto/octeontx/otx_cryptodev_capabilities.c   |  47 ++-
> >  .../crypto/octeontx/otx_cryptodev_capabilities.h   |   5 +-
> >  drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  51 ++-
> >  drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  26 +-
> >  drivers/crypto/octeontx/otx_cryptodev_mbox.h       |  20 +
> >  drivers/crypto/octeontx/otx_cryptodev_ops.c        | 338 +++++++++++++--
> >  drivers/crypto/octeontx/otx_cryptodev_ops.h        |   2 +
> >  16 files changed, 1016 insertions(+), 57 deletions(-)
> >  create mode 100644 drivers/common/cpt/cpt_ucode_asym.h
> >
> > --
> > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD
  2019-10-15 12:46   ` [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD Akhil Goyal
  2019-10-15 13:31     ` Akhil Goyal
@ 2019-10-16  4:57     ` Anoob Joseph
  2019-10-16  5:57       ` Akhil Goyal
  1 sibling, 1 reply; 31+ messages in thread
From: Anoob Joseph @ 2019-10-16  4:57 UTC (permalink / raw)
  To: Akhil Goyal, Pablo de Lara
  Cc: Jerin Jacob Kollanukkaran, Narayana Prasad Raju Athreya,
	Kanaka Durga Kotamarthy, Sunila Sahu, Shally Verma, Fiona Trahe,
	dev

Hi Akhil

You can use the following description.

+* **Added asymmetric support to Marvell OCTEON TX crypto PMD.**
+
+  Added support for asymmetric operations in Marvell OCTEON TX cypto PMD. Supports RSA
+  and modexp operations.
+

Thanks,
Anoob

> -----Original Message-----
> From: Akhil Goyal <akhil.goyal@nxp.com>
> Sent: Tuesday, October 15, 2019 6:17 PM
> To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; Narayana Prasad Raju
> Athreya <pathreya@marvell.com>; Kanaka Durga Kotamarthy
> <kkotamarthy@marvell.com>; Sunila Sahu <ssahu@marvell.com>; Shally
> Verma <shallyv@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>;
> dev@dpdk.org
> Subject: [EXT] RE: [PATCH v2 0/5] add asym support in crypto_octeontx PMD
> 
> External Email
> 
> ----------------------------------------------------------------------
> Hi Anoob,
> 
> I believe this should also be updated in the release notes.
> If yes, please reply to this mail with appropriate description.
> I will update it while merging.
> 
> >
> > This series adds asymmetric crypto support in 'crypto_octoentx' PMD.
> >
> > Changes in v2:
> > * Squashed patches as directed by Akhil
> > * Split the doc patch and added documentation along with feature
> > * Added check for ASYM SESSIONLESS (not supported currently)
> > * Made separate enqueue & dequeue routines for sym & asym
> > * Minor updates to documentation
> >
> > Kanaka Durga Kotamarthy (3):
> >   crypto/octeontx: add device type mailbox routine
> >   crypto/octeontx: add asymmetric session operations
> >   common/cpt: add helper functions for asymmetric crypto
> >
> > Sunila Sahu (2):
> >   crypto/octeontx: add asymmetric enqueue/dequeue ops
> >   app/test: register octeontx PMD to asym testsuite
> >
> >  app/test/test_cryptodev_asym.c                     |  31 ++
> >  doc/guides/cryptodevs/features/octeontx.ini        |   6 +-
> >  doc/guides/cryptodevs/octeontx.rst                 |  29 +-
> >  drivers/common/cpt/cpt_common.h                    |   4 +-
> >  drivers/common/cpt/cpt_mcode_defines.h             |  29 ++
> >  drivers/common/cpt/cpt_pmd_ops_helper.c            |  15 +
> >  drivers/common/cpt/cpt_pmd_ops_helper.h            |   9 +
> >  drivers/common/cpt/cpt_ucode_asym.h                | 453
> > +++++++++++++++++++++
> >  drivers/common/cpt/rte_common_cpt_version.map      |   8 +
> >  .../crypto/octeontx/otx_cryptodev_capabilities.c   |  47 ++-
> >  .../crypto/octeontx/otx_cryptodev_capabilities.h   |   5 +-
> >  drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  51 ++-
> >  drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  26 +-
> >  drivers/crypto/octeontx/otx_cryptodev_mbox.h       |  20 +
> >  drivers/crypto/octeontx/otx_cryptodev_ops.c        | 338 +++++++++++++--
> >  drivers/crypto/octeontx/otx_cryptodev_ops.h        |   2 +
> >  16 files changed, 1016 insertions(+), 57 deletions(-)  create mode
> > 100644 drivers/common/cpt/cpt_ucode_asym.h
> >
> > --
> > 2.7.4


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD
  2019-10-16  4:57     ` Anoob Joseph
@ 2019-10-16  5:57       ` Akhil Goyal
  0 siblings, 0 replies; 31+ messages in thread
From: Akhil Goyal @ 2019-10-16  5:57 UTC (permalink / raw)
  To: Anoob Joseph, Pablo de Lara
  Cc: Jerin Jacob Kollanukkaran, Narayana Prasad Raju Athreya,
	Kanaka Durga Kotamarthy, Sunila Sahu, Shally Verma, Fiona Trahe,
	dev



> 
> Hi Akhil
> 
> You can use the following description.
> 
> +* **Added asymmetric support to Marvell OCTEON TX crypto PMD.**
> +
> +  Added support for asymmetric operations in Marvell OCTEON TX cypto PMD.
> Supports RSA
> +  and modexp operations.
> +
> 

Updated with enq/deq patch.

Thanks.


^ permalink raw reply	[flat|nested] 31+ messages in thread

end of thread, back to index

Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-09 13:27 [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Anoob Joseph
2019-09-09 13:28 ` [dpdk-dev] [PATCH 1/8] crypto/octeontx: add device type mailbox routine Anoob Joseph
2019-09-09 13:28 ` [dpdk-dev] [PATCH 2/8] crypto/octeontx: add RSA and modexp asym capabilities Anoob Joseph
2019-10-01 12:38   ` Akhil Goyal
2019-10-02 10:48     ` Anoob Joseph
2019-10-03  8:03       ` Akhil Goyal
2019-09-09 13:28 ` [dpdk-dev] [PATCH 3/8] crypto/octeontx: add asymmetric session operations Anoob Joseph
2019-10-01 12:57   ` Akhil Goyal
2019-10-02 11:18     ` Anoob Joseph
2019-09-09 13:28 ` [dpdk-dev] [PATCH 4/8] common/cpt: add helper functions for asymmetric crypto Anoob Joseph
2019-10-01 13:04   ` Akhil Goyal
2019-10-02 11:13     ` Anoob Joseph
2019-10-04  7:32       ` Anoob Joseph
2019-09-09 13:28 ` [dpdk-dev] [PATCH 5/8] crypto/octeontx: add asymmetric op enqueue function Anoob Joseph
2019-09-09 13:28 ` [dpdk-dev] [PATCH 6/8] crypto/octeontx: add asymmetric op dequeue function Anoob Joseph
2019-09-09 13:28 ` [dpdk-dev] [PATCH 7/8] app/test: register octeontx PMD to asym testsuite Anoob Joseph
2019-09-09 13:28 ` [dpdk-dev] [PATCH 8/8] doc: update octeontx asymmetric features Anoob Joseph
2019-10-01 13:27   ` Akhil Goyal
2019-10-02 11:04     ` Anoob Joseph
2019-10-03  8:01       ` Akhil Goyal
2019-09-09 15:51 ` [dpdk-dev] [PATCH 0/8] add asym support in crypto_octeontx PMD Shally Verma
2019-10-11 13:01 ` [dpdk-dev] [PATCH v2 0/5] " Anoob Joseph
2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 1/5] crypto/octeontx: add device type mailbox routine Anoob Joseph
2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 2/5] crypto/octeontx: add asymmetric session operations Anoob Joseph
2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 3/5] common/cpt: add helper functions for asymmetric crypto Anoob Joseph
2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 4/5] crypto/octeontx: add asymmetric enqueue/dequeue ops Anoob Joseph
2019-10-11 13:01   ` [dpdk-dev] [PATCH v2 5/5] app/test: register octeontx PMD to asym testsuite Anoob Joseph
2019-10-15 12:46   ` [dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD Akhil Goyal
2019-10-15 13:31     ` Akhil Goyal
2019-10-16  4:57     ` Anoob Joseph
2019-10-16  5:57       ` Akhil Goyal

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