DPDK patches and discussions
 help / color / mirror / Atom feed
* [dpdk-dev] [PATCH] common/cnxk: add REE support
@ 2021-10-03  6:23 lironh
  2021-10-28  9:30 ` Jerin Jacob
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
  0 siblings, 2 replies; 31+ messages in thread
From: lironh @ 2021-10-03  6:23 UTC (permalink / raw)
  To: jerinj, ndabilpuram, kirankumark, skori, skoteshwar; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

Adding REE definitions and related ROC code

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/hw/ree.h        | 165 +++++++
 drivers/common/cnxk/hw/rvu.h        |   5 +
 drivers/common/cnxk/meson.build     |   1 +
 drivers/common/cnxk/roc_api.h       |   4 +
 drivers/common/cnxk/roc_constants.h |   2 +
 drivers/common/cnxk/roc_mbox.h      | 100 +++++
 drivers/common/cnxk/roc_platform.c  |   1 +
 drivers/common/cnxk/roc_platform.h  |   2 +
 drivers/common/cnxk/roc_priv.h      |   3 +
 drivers/common/cnxk/roc_ree.c       | 647 ++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ree.h       | 137 ++++++
 drivers/common/cnxk/roc_ree_priv.h  |  18 +
 drivers/common/cnxk/version.map     |  18 +-
 13 files changed, 1102 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 0000000000..0766d35e52
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BIT	   (1 << 14)
+#define REE_STATUS_PMI_SOJ_BIT	   (1 << 13)
+#define REE_STATUS_MP_CNT_DET_BIT  (1 << 7)
+#define REE_STATUS_MM_CNT_DET_BIT  (1 << 6)
+#define REE_STATUS_ML_CNT_DET_BIT  (1 << 5)
+#define REE_STATUS_MST_CNT_DET_BIT (1 << 4)
+#define REE_STATUS_MPT_CNT_DET_BIT (1 << 3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT		0x120ull
+#define REE_LF_DONE_INT_W1S	0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT		0x300ull
+#define REE_LF_MISC_INT_W1S	0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA		0x10ull
+#define REE_LF_SBUF_ADDR	0x20ull
+#define REE_LF_DONE		0x100ull
+#define REE_LF_DONE_ACK		0x110ull
+#define REE_LF_DONE_WAIT	0x148ull
+#define REE_LF_DOORBELL		0x400ull
+#define REE_LF_OUTSTAND_JOB	0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a)     (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS	(0x0ull)
+#define REE_AF_INT_VEC_RVU	(0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ	(0x3ull)
+
+/* ENUMS */
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC	(0x1ull)
+
+#define REE_LF_BAR2(vf, q_id)                                                  \
+	((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+	REE_TYPE_JOB_DESC = 0x0,
+	REE_TYPE_RESULT_DESC = 0x1,
+	REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_priv_lf_cfg {
+	uint64_t u;
+	struct {
+		uint64_t slot : 8;
+		uint64_t pf_func : 16;
+		uint64_t reserved_24_62 : 39;
+		uint64_t ena : 1;
+	} s;
+};
+
+union ree_lf_sbuf_addr {
+	uint64_t u;
+	struct {
+		uint64_t off : 7;
+		uint64_t ptr : 46;
+		uint64_t reserved_53_63 : 11;
+	} s;
+};
+
+union ree_lf_ena {
+	uint64_t u;
+	struct {
+		uint64_t ena : 1;
+		uint64_t reserved_1_63 : 63;
+	} s;
+};
+
+union ree_af_reexm_max_match {
+	uint64_t u;
+	struct {
+		uint64_t max : 8;
+		uint64_t reserved_8_63 : 56;
+	} s;
+};
+
+union ree_lf_done {
+	uint64_t u;
+	struct {
+		uint64_t done : 20;
+		uint64_t reserved_20_63 : 44;
+	} s;
+};
+
+union ree_res_status {
+	uint64_t u;
+	struct {
+		uint64_t job_type : 3;
+		uint64_t mpt_cnt_det : 1;
+		uint64_t mst_cnt_det : 1;
+		uint64_t ml_cnt_det : 1;
+		uint64_t mm_cnt_det : 1;
+		uint64_t mp_cnt_det : 1;
+		uint64_t mode : 2;
+		uint64_t reserved_10_11 : 2;
+		uint64_t reserved_12_12 : 1;
+		uint64_t pmi_soj : 1;
+		uint64_t pmi_eoj : 1;
+		uint64_t reserved_15_15 : 1;
+		uint64_t reserved_16_63 : 48;
+	} s;
+};
+
+union ree_res {
+	uint64_t u[8];
+	struct ree_res_s_98 {
+		uint64_t done : 1;
+		uint64_t hwjid : 7;
+		uint64_t ree_res_job_id : 24;
+		uint64_t ree_res_status : 16;
+		uint64_t ree_res_dmcnt : 8;
+		uint64_t ree_res_mcnt : 8;
+		uint64_t ree_meta_ptcnt : 16;
+		uint64_t ree_meta_icnt : 16;
+		uint64_t ree_meta_lcnt : 16;
+		uint64_t ree_pmi_min_byte_ptr : 16;
+		uint64_t ree_err : 1;
+		uint64_t reserved_129_190 : 62;
+		uint64_t doneint : 1;
+		uint64_t reserved_192_255 : 64;
+		uint64_t reserved_256_319 : 64;
+		uint64_t reserved_320_383 : 64;
+		uint64_t reserved_384_447 : 64;
+		uint64_t reserved_448_511 : 64;
+	} s;
+};
+
+union ree_match {
+	uint64_t u;
+	struct {
+		uint64_t ree_rule_id : 32;
+		uint64_t start_ptr : 14;
+		uint64_t reserved_46_47 : 2;
+		uint64_t match_length : 15;
+		uint64_t reserved_63_6 : 1;
+	} s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM    (0x0ull)
 #define RVU_BLOCK_ADDR_LMT     (0x1ull)
@@ -147,6 +148,8 @@
 #define RVU_BLOCK_ADDR_NDC2    (0xeull)
 #define RVU_BLOCK_ADDR_R_END   (0x1full)
 #define RVU_BLOCK_ADDR_R_START (0x14ull)
+#define RVU_BLOCK_ADDR_REE0    (0x14ull)
+#define RVU_BLOCK_ADDR_REE1    (0x15ull)
 
 #define RVU_VF_INT_VEC_MBOX (0x0ull)
 
@@ -167,6 +170,7 @@
 #define NPA_AF_BAR2_SEL	 (0x9000000ull)
 #define CPT_AF_BAR2_SEL	 (0x9000000ull)
 #define RVU_AF_BAR2_SEL	 (0x9000000ull)
+#define REE_AF_BAR2_SEL	 (0x9000000ull)
 
 #define AF_BAR2_ALIASX(a, b)                                                   \
 	(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))
@@ -177,6 +181,7 @@
 #define NPA_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(0, b)
 #define CPT_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 #define RVU_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
+#define REE_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 
 /* Structures definitions */
 
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 97db5f087b..fa24f385a3 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -59,6 +59,7 @@ sources = files(
         'roc_tim.c',
         'roc_tim_irq.c',
         'roc_utils.c',
+        'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index b8f3667c6c..abf72077f8 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -36,6 +36,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -86,6 +87,9 @@
 #include "roc_ie_ot.h"
 #include "roc_se.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
index 1e6427cf91..e1ffca31d4 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY	      0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF     0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF     0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 75d1ff1ef3..4924620084 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -148,6 +148,16 @@ struct mbox_msghdr {
 	M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)        \
 	M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,            \
 	  cpt_eng_grp_rsp)                                                     \
+	/* REE mbox IDs (range 0xE00 - 0xFFF) */                               \
+	M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)        \
+	M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,    \
+	  ree_rd_wr_reg_msg)                                                   \
+	M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+	  msg_rsp)                                                             \
+	M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,        \
+	  ree_rule_db_len_rsp_msg)                                             \
+	M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,    \
+	  ree_rule_db_get_rsp_msg)                                             \
 	/* SDP mbox IDs (range 0x1000 - 0x11FF) */                             \
 	M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg,     \
 	  msg_rsp)                                                             \
@@ -1394,6 +1404,96 @@ struct cpt_eng_grp_rsp {
 	uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+	REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+	REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+	REE_AF_ERR_LF_INVALID = -1003,
+	REE_AF_ERR_ACCESS_DENIED = -1004,
+	REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+	REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+	REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+	REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+	REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+	REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+	REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+	REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+	REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+	REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+	REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+	REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+	REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+	REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+	REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+	REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+	REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+	REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+	REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io size;
+	uint8_t __io lf;
+	uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+	uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+	uint32_t __io blkaddr;	     /* REE0 or REE1 */
+	uint32_t __io total_len;     /* total len of rule db */
+	uint32_t __io offset;	     /* offset of current rule db block */
+	uint16_t __io len;	     /* length of rule db block */
+	uint8_t __io is_last;	     /* is this the last block */
+	uint8_t __io is_incremental; /* is incremental flow */
+	uint8_t __io is_dbi;	     /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io offset; /* retrieve db from this offset */
+	uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+	struct mbox_msghdr hdr;
+	uint64_t __io reg_offset;
+	uint64_t __io *ret_val;
+	uint64_t __io val;
+	uint32_t __io blkaddr;
+	uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io len;
+	uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+	uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+	uint32_t __io total_len; /* total len of rule db */
+	uint32_t __io offset;	 /* offset of current rule db block */
+	uint16_t __io len;	 /* length of rule db block */
+	uint8_t __io is_last;	 /* is this the last block */
+};
+
 /* NPC mbox message structs */
 
 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 241655b334..4f48a8e282 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -152,6 +152,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)                                                  \
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -176,6 +177,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)	plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)	plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)	plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)	plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)                                               \
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index f72bbd568f..b091d519cb 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -41,4 +41,7 @@
 /* NIX Inline dev */
 #include "roc_nix_inl_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 0000000000..35ed9ab3d5
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+/* This is temporarily here */
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+	struct free_rsrcs_rsp *rsp;
+	struct dev *dev = vf->dev;
+	int ret;
+
+	mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+		*nb_queues = rsp->ree0;
+	else
+		*nb_queues = rsp->ree1;
+	return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+	uint64_t val;
+	int ret;
+
+	ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+	if (ret)
+		return ret;
+
+	*max_matches = val;
+	return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+	struct rsrc_attach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	/* Ask AF to attach required LFs */
+	req = mbox_alloc_msg_attach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	/* 1 LF = 1 queue */
+	req->reelfs = nb_queues;
+	req->ree_blkaddr = vf->block_address;
+
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Update number of attached queues */
+	vf->nb_queues = nb_queues;
+
+	return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+	struct rsrc_detach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_detach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+	req->reelfs = true;
+	req->partial = true;
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Queues have been detached */
+	vf->nb_queues = 0;
+
+	return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+	struct msix_offset_rsp *rsp;
+	struct mbox *mbox;
+	uint32_t i, ret;
+
+	/* Get REE MSI-X vector offsets */
+	mbox = vf->dev->mbox;
+	mbox_alloc_msg_msix_offset(mbox);
+
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+		else
+			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+		plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+	}
+
+	return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+	struct mbox *mbox = vf->dev->mbox;
+	int ret;
+
+	mbox_msg_send(mbox, 0);
+
+	ret = mbox_wait_for_rsp(mbox, 0);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+
+	return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t size)
+{
+	struct ree_lf_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_ree_config_lf(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->lf = lf;
+	req->pri = pri ? 1 : 0;
+	req->size = size;
+	req->blkaddr = vf->block_address;
+
+	ret = mbox_process(mbox);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+	return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox_dev *mdev;
+	struct mbox *mbox;
+	int ret, off;
+
+	mbox = vf->dev->mbox;
+	mdev = &mbox->dev[0];
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 0;
+	msg->reg_offset = reg;
+	msg->ret_val = val;
+	msg->blkaddr = vf->block_address;
+
+	ret = ree_send_mbox_msg(vf);
+	if (ret < 0)
+		return ret;
+
+	off = mbox->rx_start +
+	      RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+	msg = (struct ree_rd_wr_reg_msg *)((uintptr_t)mdev->mbase + off);
+
+	*val = msg->val;
+
+	return 0;
+}
+
+int
+roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg, uint64_t val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 1;
+	msg->reg_offset = reg;
+	msg->val = val;
+	msg->blkaddr = vf->block_address;
+
+	return ree_send_mbox_msg(vf);
+}
+
+int
+roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db, uint32_t rule_db_len,
+		    char *rule_dbi, uint32_t rule_dbi_len)
+{
+	struct ree_rule_db_get_req_msg *req;
+	struct ree_rule_db_get_rsp_msg *rsp;
+	char *rule_db_ptr = (char *)rule_db;
+	struct mbox *mbox;
+	int ret, last = 0;
+	uint32_t len = 0;
+
+	mbox = vf->dev->mbox;
+	if (!rule_db) {
+		plt_err("Couldn't return rule db due to NULL pointer");
+		return -EFAULT;
+	}
+
+	while (!last) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 0;
+		req->offset = len;
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_db_len < len + rsp->len) {
+			plt_err("Rule db size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
+		len += rsp->len;
+		rule_db_ptr = rule_db_ptr + rsp->len;
+		last = rsp->is_last;
+	}
+
+	if (rule_dbi) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 1;
+		req->offset = 0;
+
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_dbi_len < rsp->len) {
+			plt_err("Rule dbi size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_len_get(struct roc_ree_vf *vf, uint32_t *rule_db_len,
+			uint32_t *rule_dbi_len)
+{
+	struct ree_rule_db_len_rsp_msg *rsp;
+	struct ree_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = (struct ree_req_msg *)mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
+						       sizeof(*rsp));
+	if (!req) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
+	req->hdr.sig = MBOX_REQ_SIG;
+	req->hdr.pcifunc = vf->dev->pf_func;
+	req->blkaddr = vf->block_address;
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+	if (rule_db_len != NULL)
+		*rule_db_len = rsp->len;
+	if (rule_dbi_len != NULL)
+		*rule_dbi_len = rsp->inc_len;
+
+	return 0;
+}
+
+static int
+ree_db_msg(struct roc_ree_vf *vf, const char *db, uint32_t db_len, int inc,
+	   int dbi)
+{
+	uint32_t len_left = db_len, offset = 0;
+	struct ree_rule_db_prog_req_msg *req;
+	const char *rule_db_ptr = db;
+	struct mbox *mbox;
+	struct msg_rsp *rsp;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	while (len_left) {
+		req = (struct ree_rule_db_prog_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->offset = offset;
+		req->total_len = db_len;
+		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
+		req->is_incremental = inc;
+		req->is_dbi = dbi;
+		req->blkaddr = vf->block_address;
+
+		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
+			req->is_last = true;
+			req->len = len_left;
+		}
+		mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret) {
+			plt_err("Programming mailbox processing failed");
+			return ret;
+		}
+		len_left -= req->len;
+		offset += req->len;
+		rule_db_ptr = rule_db_ptr + req->len;
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+		     uint32_t rule_db_len, const char *rule_dbi,
+		     uint32_t rule_dbi_len)
+{
+	int inc, ret;
+
+	if (rule_db_len == 0) {
+		plt_err("Couldn't program empty rule db");
+		return -EFAULT;
+	}
+	inc = (rule_dbi_len != 0);
+	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
+		plt_err("Couldn't program NULL rule db");
+		return -EFAULT;
+	}
+	if (inc) {
+		ret = ree_db_msg(vf, rule_dbi, rule_dbi_len, inc, 1);
+		if (ret)
+			return ret;
+	}
+	return ree_db_msg(vf, rule_db, rule_db_len, inc, 0);
+}
+
+static int
+ree_get_blkaddr(struct dev *dev)
+{
+	int pf;
+
+	pf = dev_get_pf(dev->pf_func);
+	if (pf == REE0_PF)
+		return RVU_BLOCK_ADDR_REE0;
+	else if (pf == REE1_PF)
+		return RVU_BLOCK_ADDR_REE1;
+	else
+		return 0;
+}
+
+uintptr_t
+roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id)
+{
+	return REE_LF_BAR2(vf, qp_id);
+}
+
+static void
+roc_ree_lf_err_intr_handler(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint8_t lf_id;
+	uint64_t intr;
+
+	lf_id = (base >> 12) & 0xFF;
+
+	intr = plt_read64(base + REE_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
+
+	/* Clear interrupt */
+	plt_write64(intr, base + REE_LF_MISC_INT);
+}
+
+static void
+roc_ree_lf_err_intr_unregister(struct roc_ree_vf *vf, uint16_t msix_off,
+			       uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	dev_irq_unregister(handle, roc_ree_lf_err_intr_handler, (void *)base,
+			   msix_off);
+}
+
+void
+roc_ree_err_intr_unregister(struct roc_ree_vf *vf)
+{
+	uintptr_t base;
+	uint32_t i;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base);
+	}
+
+	vf->err_intr_registered = 0;
+}
+
+static int
+roc_ree_lf_err_intr_register(struct roc_ree_vf *vf, uint16_t msix_off,
+			     uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int ret;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	/* Register error interrupt handler */
+	ret = dev_irq_register(handle, roc_ree_lf_err_intr_handler,
+			       (void *)base, msix_off);
+	if (ret)
+		return ret;
+
+	/* Enable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1S);
+
+	return 0;
+}
+
+int
+roc_ree_err_intr_register(struct roc_ree_vf *vf)
+{
+	uint32_t i, j, ret;
+	uintptr_t base;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
+			plt_err("Invalid REE LF MSI-X offset: 0x%x",
+				vf->lf_msixoff[i]);
+			return -EINVAL;
+		}
+	}
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		ret = roc_ree_lf_err_intr_register(vf, vf->lf_msixoff[i], base);
+		if (ret)
+			goto intr_unregister;
+	}
+
+	vf->err_intr_registered = 1;
+	return 0;
+
+intr_unregister:
+	/* Unregister the ones already registered */
+	for (j = 0; j < i; j++) {
+		base = REE_LF_BAR2(vf, j);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[j], base);
+	}
+	return ret;
+}
+
+int
+roc_ree_iq_enable(struct roc_ree_vf *vf, const struct roc_ree_qp *qp,
+		  uint8_t pri, uint32_t size_div2)
+{
+	union ree_lf_sbuf_addr base;
+	union ree_lf_ena lf_ena;
+
+	/* Set instruction queue size and priority */
+	roc_ree_config_lf(vf, qp->id, pri, size_div2);
+
+	/* Set instruction queue base address */
+	/* Should be written after SBUF_CTL and before LF_ENA */
+
+	base.u = plt_read64(qp->base + REE_LF_SBUF_ADDR);
+	base.s.ptr = qp->iq_dma_addr >> 7;
+	plt_write64(base.u, qp->base + REE_LF_SBUF_ADDR);
+
+	/* Enable instruction queue */
+
+	lf_ena.u = plt_read64(qp->base + REE_LF_ENA);
+	lf_ena.s.ena = 1;
+	plt_write64(lf_ena.u, qp->base + REE_LF_ENA);
+
+	return 0;
+}
+
+void
+roc_ree_iq_disable(struct roc_ree_qp *qp)
+{
+	union ree_lf_ena lf_ena;
+
+	/* Stop instruction execution */
+	lf_ena.u = plt_read64(qp->base + REE_LF_ENA);
+	lf_ena.s.ena = 0x0;
+	plt_write64(lf_ena.u, qp->base + REE_LF_ENA);
+}
+
+int
+roc_ree_dev_init(struct roc_ree_vf *vf)
+{
+	struct plt_pci_device *pci_dev;
+	struct ree *ree;
+	struct dev *dev;
+	uint8_t max_matches = 0;
+	uint16_t nb_queues = 0;
+	int rc;
+
+	if (vf == NULL || vf->pci_dev == NULL)
+		return -EINVAL;
+
+	PLT_STATIC_ASSERT(sizeof(struct ree) <= ROC_REE_MEM_SZ);
+
+	ree = roc_ree_to_ree_priv(vf);
+	memset(ree, 0, sizeof(*ree));
+	vf->dev = &ree->dev;
+
+	pci_dev = vf->pci_dev;
+	dev = vf->dev;
+
+	/* Initialize device  */
+	rc = dev_init(dev, pci_dev);
+	if (rc) {
+		plt_err("Failed to init roc device");
+		goto fail;
+	}
+
+	/* Get REE block address */
+	vf->block_address = ree_get_blkaddr(dev);
+	if (!vf->block_address) {
+		plt_err("Could not determine block PF number");
+		goto fail;
+	}
+
+	/* Get number of queues available on the device */
+	rc = roc_ree_available_queues_get(vf, &nb_queues);
+	if (rc) {
+		plt_err("Could not determine the number of queues available");
+		goto fail;
+	}
+
+	/* Don't exceed the limits set per VF */
+	nb_queues = RTE_MIN(nb_queues, REE_MAX_QUEUES_PER_VF);
+
+	if (nb_queues == 0) {
+		plt_err("No free queues available on the device");
+		goto fail;
+	}
+
+	vf->max_queues = nb_queues;
+
+	plt_ree_dbg("Max queues supported by device: %d", vf->max_queues);
+
+	/* Get number of maximum matches supported on the device */
+	rc = roc_ree_max_matches_get(vf, &max_matches);
+	if (rc) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+	/* Don't exceed the limits set per VF */
+	max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
+	if (max_matches == 0) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+
+	vf->max_matches = max_matches;
+
+	plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+fail:
+	return rc;
+}
+
+int
+roc_ree_dev_fini(struct roc_ree_vf *vf)
+{
+	if (vf == NULL)
+		return -EINVAL;
+
+	vf->max_matches = 0;
+	vf->max_queues = 0;
+
+	return dev_fini(vf->dev, vf->pci_dev);
+}
diff --git a/drivers/common/cnxk/roc_ree.h b/drivers/common/cnxk/roc_ree.h
new file mode 100644
index 0000000000..e138e4de66
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_H_
+#define _ROC_REE_H_
+
+#include "roc_api.h"
+
+#define REE_MAX_LFS	       36
+#define REE_MAX_QUEUES_PER_VF  36
+#define REE_MAX_MATCHES_PER_VF 254
+
+#define REE_MAX_PAYLOAD_SIZE (1 << 14)
+
+#define REE_NON_INC_PROG 0
+#define REE_INC_PROG	 1
+
+#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)
+
+/**
+ * Device vf data
+ */
+struct roc_ree_vf {
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	/**< Base class */
+	uint16_t max_queues;
+	/**< Max queues supported */
+	uint8_t nb_queues;
+	/**< Number of regex queues attached */
+	uint16_t max_matches;
+	/**<  Max matches supported*/
+	uint16_t lf_msixoff[REE_MAX_LFS];
+	/**< MSI-X offsets */
+	uint8_t block_address;
+	/**< REE Block Address */
+	uint8_t err_intr_registered : 1;
+	/**< Are error interrupts registered? */
+
+#define ROC_REE_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_REE_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+struct roc_ree_rid {
+	uintptr_t rid;
+	/** Request id of a ree operation */
+	uint64_t user_id;
+	/* Client data */
+	/**< IOVA address of the pattern to be matched. */
+};
+
+struct roc_ree_pending_queue {
+	uint64_t pending_count;
+	/** Pending requests count */
+	struct roc_ree_rid *rid_queue;
+	/** Array of pending requests */
+	uint16_t enq_tail;
+	/** Tail of queue to be used for enqueue */
+	uint16_t deq_head;
+	/** Head of queue to be used for dequeue */
+};
+
+struct roc_ree_qp {
+	uint32_t id;
+	/**< Queue pair id */
+	uintptr_t base;
+	/**< Base address where BAR is mapped */
+	struct roc_ree_pending_queue pend_q;
+	/**< Pending queue */
+	rte_iova_t iq_dma_addr;
+	/**< Instruction queue address */
+	uint32_t roc_regexdev_jobid;
+	/**< Job ID */
+	uint32_t write_offset;
+	/**< write offset */
+};
+
+union roc_ree_inst {
+	uint64_t u[8];
+	struct {
+		uint64_t doneint : 1;
+		uint64_t reserved_1_3 : 3;
+		uint64_t dg : 1;
+		uint64_t reserved_5_7 : 3;
+		uint64_t ooj : 1;
+		uint64_t reserved_9_15 : 7;
+		uint64_t reserved_16_63 : 48;
+		uint64_t inp_ptr_addr : 64;
+		uint64_t inp_ptr_ctl : 64;
+		uint64_t res_ptr_addr : 64;
+		uint64_t wq_ptr : 64;
+		uint64_t tag : 32;
+		uint64_t tt : 2;
+		uint64_t ggrp : 10;
+		uint64_t reserved_364_383 : 20;
+		uint64_t reserved_384_391 : 8;
+		uint64_t ree_job_id : 24;
+		uint64_t ree_job_ctrl : 16;
+		uint64_t ree_job_length : 15;
+		uint64_t reserved_447_447 : 1;
+		uint64_t ree_job_subset_id_0 : 16;
+		uint64_t ree_job_subset_id_1 : 16;
+		uint64_t ree_job_subset_id_2 : 16;
+		uint64_t ree_job_subset_id_3 : 16;
+	} cn98xx;
+};
+
+int __roc_api roc_ree_dev_init(struct roc_ree_vf *vf);
+int __roc_api roc_ree_dev_fini(struct roc_ree_vf *vf);
+int __roc_api roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues);
+int __roc_api roc_ree_queues_detach(struct roc_ree_vf *vf);
+int __roc_api roc_ree_msix_offsets_get(struct roc_ree_vf *vf);
+int __roc_api roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri,
+				uint32_t size);
+int __roc_api roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg,
+				  uint64_t *val);
+int __roc_api roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg,
+				   uint64_t val);
+int __roc_api roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db,
+				  uint32_t rule_db_len, char *rule_dbi,
+				  uint32_t rule_dbi_len);
+int __roc_api roc_ree_rule_db_len_get(struct roc_ree_vf *vf,
+				      uint32_t *rule_db_len,
+				      uint32_t *rule_dbi_len);
+int __roc_api roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+				   uint32_t rule_db_len, const char *rule_dbi,
+				   uint32_t rule_dbi_len);
+uintptr_t __roc_api roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id);
+void __roc_api roc_ree_err_intr_unregister(struct roc_ree_vf *vf);
+int __roc_api roc_ree_err_intr_register(struct roc_ree_vf *vf);
+int __roc_api roc_ree_iq_enable(struct roc_ree_vf *vf,
+				const struct roc_ree_qp *qp, uint8_t pri,
+				uint32_t size_div128);
+void __roc_api roc_ree_iq_disable(struct roc_ree_qp *qp);
+
+#endif /* _ROC_REE_H_ */
diff --git a/drivers/common/cnxk/roc_ree_priv.h b/drivers/common/cnxk/roc_ree_priv.h
new file mode 100644
index 0000000000..c39f7cf986
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree_priv.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_PRIV_H_
+#define _ROC_REE_PRIV_H_
+
+struct ree {
+	struct dev dev;
+} __plt_cache_aligned;
+
+static inline struct ree *
+roc_ree_to_ree_priv(struct roc_ree_vf *roc_ree)
+{
+	return (struct ree *)&roc_ree->reserved[0];
+}
+
+#endif /* _ROC_REE_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 926d5c2167..e1e96d41d0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_nix;
 	cnxk_logtype_npa;
 	cnxk_logtype_npc;
+	cnxk_logtype_ree;
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
@@ -314,6 +315,21 @@ INTERNAL {
 	roc_tim_lf_enable;
 	roc_tim_lf_free;
 	roc_se_ctx_swap;
-
+	roc_ree_af_reg_read;
+	roc_ree_af_reg_write;
+	roc_ree_config_lf;
+	roc_ree_dev_fini;
+	roc_ree_dev_init;
+	roc_ree_err_intr_register;
+	roc_ree_err_intr_unregister;
+	roc_ree_iq_disable;
+	roc_ree_iq_enable;
+	roc_ree_msix_offsets_get;
+	roc_ree_qp_get_base;
+	roc_ree_queues_attach;
+	roc_ree_queues_detach;
+	roc_ree_rule_db_get;
+	roc_ree_rule_db_len_get;
+	roc_ree_rule_db_prog;
 	local: *;
 };
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [dpdk-dev] [PATCH] common/cnxk: add REE support
  2021-10-03  6:23 [dpdk-dev] [PATCH] common/cnxk: add REE support lironh
@ 2021-10-28  9:30 ` Jerin Jacob
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
  1 sibling, 0 replies; 31+ messages in thread
From: Jerin Jacob @ 2021-10-28  9:30 UTC (permalink / raw)
  To: Liron Himi
  Cc: Jerin Jacob, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
	Satha Koteswara Rao Kottidi, dpdk-dev

On Sun, Oct 3, 2021 at 11:53 AM <lironh@marvell.com> wrote:
>
> From: Liron Himi <lironh@marvell.com>
>
> Adding REE definitions and related ROC code

# Mention the full form of REE in the git commit message.

#Patch looks good to me. Some minor comments below

# Also, Please send a patch for switching drivers/regex/octeontx2/ to
the new RoC driver. We will plan to merge it on RC2.

# Please split this patch a 3 or 4 more logical patches for
device-specific, rules API, etc


>
> Signed-off-by: Liron Himi <lironh@marvell.com>
> ---
>  drivers/common/cnxk/hw/ree.h        | 165 +++++++
>  drivers/common/cnxk/hw/rvu.h        |   5 +
>  drivers/common/cnxk/meson.build     |   1 +
>  drivers/common/cnxk/roc_api.h       |   4 +
>  drivers/common/cnxk/roc_constants.h |   2 +
>  drivers/common/cnxk/roc_mbox.h      | 100 +++++
>  drivers/common/cnxk/roc_platform.c  |   1 +
>  drivers/common/cnxk/roc_platform.h  |   2 +
>  drivers/common/cnxk/roc_priv.h      |   3 +
>  drivers/common/cnxk/roc_ree.c       | 647 ++++++++++++++++++++++++++++
>  drivers/common/cnxk/roc_ree.h       | 137 ++++++
>  drivers/common/cnxk/roc_ree_priv.h  |  18 +
>  drivers/common/cnxk/version.map     |  18 +-
>  13 files changed, 1102 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/common/cnxk/hw/ree.h
>  create mode 100644 drivers/common/cnxk/roc_ree.c
>  create mode 100644 drivers/common/cnxk/roc_ree.h
>  create mode 100644 drivers/common/cnxk/roc_ree_priv.h
>
> diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
> new file mode 100644
> index 0000000000..0766d35e52
> --- /dev/null
> +++ b/drivers/common/cnxk/hw/ree.h
> @@ -0,0 +1,165 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#ifndef __REE_HW_H__
> +#define __REE_HW_H__
> +
> +/* REE instruction queue length */
> +#define REE_IQ_LEN (1 << 13)
> +
> +#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
> +
> +/* Status register bits */
> +#define REE_STATUS_PMI_EOJ_BIT    (1 << 14)
> +#define REE_STATUS_PMI_SOJ_BIT    (1 << 13)
> +#define REE_STATUS_MP_CNT_DET_BIT  (1 << 7)
> +#define REE_STATUS_MM_CNT_DET_BIT  (1 << 6)
> +#define REE_STATUS_ML_CNT_DET_BIT  (1 << 5)
> +#define REE_STATUS_MST_CNT_DET_BIT (1 << 4)
> +#define REE_STATUS_MPT_CNT_DET_BIT (1 << 3)

Use macros in drivers/common/cnxk/roc_bits.h


> +
> +/* Register offsets */
> +/* REE LF registers */
> +#define REE_LF_DONE_INT                0x120ull
> +#define REE_LF_DONE_INT_W1S    0x130ull
> +#define REE_LF_DONE_INT_ENA_W1S 0x138ull
> +#define REE_LF_DONE_INT_ENA_W1C 0x140ull
> +#define REE_LF_MISC_INT                0x300ull
> +#define REE_LF_MISC_INT_W1S    0x310ull
> +#define REE_LF_MISC_INT_ENA_W1S 0x320ull
> +#define REE_LF_MISC_INT_ENA_W1C 0x330ull
> +#define REE_LF_ENA             0x10ull
> +#define REE_LF_SBUF_ADDR       0x20ull
> +#define REE_LF_DONE            0x100ull
> +#define REE_LF_DONE_ACK                0x110ull
> +#define REE_LF_DONE_WAIT       0x148ull
> +#define REE_LF_DOORBELL                0x400ull
> +#define REE_LF_OUTSTAND_JOB    0x410ull
> +
> +/* BAR 0 */
> +#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
> +#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
> +#define REE_PRIV_LF_CFG(a)     (0x41000ull | (uint64_t)(a) << 3)
> +
> +#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
> +
> +#define REE_AF_INT_VEC_RAS     (0x0ull)
> +#define REE_AF_INT_VEC_RVU     (0x1ull)
> +#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
> +#define REE_AF_INT_VEC_AQ      (0x3ull)
> +
> +/* ENUMS */
> +
> +#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
> +#define REE_LF_INT_VEC_MISC    (0x1ull)
> +
> +#define REE_LF_BAR2(vf, q_id)                                                  \
> +       ((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
> +
> +#define REE_QUEUE_HI_PRIO 0x1
> +
> +enum ree_desc_type_e {
> +       REE_TYPE_JOB_DESC = 0x0,
> +       REE_TYPE_RESULT_DESC = 0x1,
> +       REE_TYPE_ENUM_LAST = 0x2
> +};
> +
> +union ree_priv_lf_cfg {
> +       uint64_t u;
> +       struct {
> +               uint64_t slot : 8;
> +               uint64_t pf_func : 16;
> +               uint64_t reserved_24_62 : 39;
> +               uint64_t ena : 1;
> +       } s;
> +};
> +
> +union ree_lf_sbuf_addr {
> +       uint64_t u;
> +       struct {
> +               uint64_t off : 7;
> +               uint64_t ptr : 46;
> +               uint64_t reserved_53_63 : 11;
> +       } s;
> +};
> +
> +union ree_lf_ena {
> +       uint64_t u;
> +       struct {
> +               uint64_t ena : 1;
> +               uint64_t reserved_1_63 : 63;
> +       } s;
> +};
> +
> +union ree_af_reexm_max_match {
> +       uint64_t u;
> +       struct {
> +               uint64_t max : 8;
> +               uint64_t reserved_8_63 : 56;
> +       } s;
> +};
> +
> +union ree_lf_done {
> +       uint64_t u;
> +       struct {
> +               uint64_t done : 20;
> +               uint64_t reserved_20_63 : 44;
> +       } s;
> +};

All the register definitions above use bitfield APIs in
drivers/common/cnxk/roc_bitfield.h

context structure like below OK to use structure scheme like existing
HW blocks in RoC.

> +
> +union ree_res_status {
> +       uint64_t u;
> +       struct {
> +               uint64_t job_type : 3;
> +               uint64_t mpt_cnt_det : 1;
> +               uint64_t mst_cnt_det : 1;
> +               uint64_t ml_cnt_det : 1;
> +               uint64_t mm_cnt_det : 1;
> +               uint64_t mp_cnt_det : 1;
> +               uint64_t mode : 2;
> +               uint64_t reserved_10_11 : 2;
> +               uint64_t reserved_12_12 : 1;
> +               uint64_t pmi_soj : 1;
> +               uint64_t pmi_eoj : 1;
> +               uint64_t reserved_15_15 : 1;
> +               uint64_t reserved_16_63 : 48;
> +       } s;
> +};
> +
> +union ree_res {
> +       uint64_t u[8];
> +       struct ree_res_s_98 {
> +               uint64_t done : 1;
> +               uint64_t hwjid : 7;
> +               uint64_t ree_res_job_id : 24;
> +               uint64_t ree_res_status : 16;
> +               uint64_t ree_res_dmcnt : 8;
> +               uint64_t ree_res_mcnt : 8;
> +               uint64_t ree_meta_ptcnt : 16;
> +               uint64_t ree_meta_icnt : 16;
> +               uint64_t ree_meta_lcnt : 16;
> +               uint64_t ree_pmi_min_byte_ptr : 16;
> +               uint64_t ree_err : 1;
> +               uint64_t reserved_129_190 : 62;
> +               uint64_t doneint : 1;
> +               uint64_t reserved_192_255 : 64;
> +               uint64_t reserved_256_319 : 64;
> +               uint64_t reserved_320_383 : 64;
> +               uint64_t reserved_384_447 : 64;
> +               uint64_t reserved_448_511 : 64;
> +       } s;
> +};
> +
> +union ree_match {
> +       uint64_t u;
> +       struct {
> +               uint64_t ree_rule_id : 32;
> +               uint64_t start_ptr : 14;
> +               uint64_t reserved_46_47 : 2;
> +               uint64_t match_length : 15;
> +               uint64_t reserved_63_6 : 1;
> +       } s;
> +};
> +
> +#endif /* __REE_HW_H__ */
> diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
> index 632d9499ea..daf758f0b5 100644
> --- a/drivers/common/cnxk/hw/rvu.h
> +++ b/drivers/common/cnxk/hw/rvu.h
> @@ -130,6 +130,7 @@
>  #define RVU_BLOCK_TYPE_RAD  (0xdull)
>  #define RVU_BLOCK_TYPE_DFA  (0xeull)
>  #define RVU_BLOCK_TYPE_HNA  (0xfull)
> +#define RVU_BLOCK_TYPE_REE  (0xeull)
>
>  #define RVU_BLOCK_ADDR_RVUM    (0x0ull)
>  #define RVU_BLOCK_ADDR_LMT     (0x1ull)
> @@ -147,6 +148,8 @@
>  #define RVU_BLOCK_ADDR_NDC2    (0xeull)
>  #define RVU_BLOCK_ADDR_R_END   (0x1full)
>  #define RVU_BLOCK_ADDR_R_START (0x14ull)
> +#define RVU_BLOCK_ADDR_REE0    (0x14ull)
> +#define RVU_BLOCK_ADDR_REE1    (0x15ull)
>
>  #define RVU_VF_INT_VEC_MBOX (0x0ull)
>
> @@ -167,6 +170,7 @@
>  #define NPA_AF_BAR2_SEL         (0x9000000ull)
>  #define CPT_AF_BAR2_SEL         (0x9000000ull)
>  #define RVU_AF_BAR2_SEL         (0x9000000ull)
> +#define REE_AF_BAR2_SEL         (0x9000000ull)
>
>  #define AF_BAR2_ALIASX(a, b)                                                   \
>         (0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))
> @@ -177,6 +181,7 @@
>  #define NPA_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(0, b)
>  #define CPT_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
>  #define RVU_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
> +#define REE_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
>
>  /* Structures definitions */
>
> diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
> index 97db5f087b..fa24f385a3 100644
> --- a/drivers/common/cnxk/meson.build
> +++ b/drivers/common/cnxk/meson.build
> @@ -59,6 +59,7 @@ sources = files(
>          'roc_tim.c',
>          'roc_tim_irq.c',
>          'roc_utils.c',
> +        'roc_ree.c',
>  )
>
>  # Security common code
> diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
> index b8f3667c6c..abf72077f8 100644
> --- a/drivers/common/cnxk/roc_api.h
> +++ b/drivers/common/cnxk/roc_api.h
> @@ -36,6 +36,7 @@
>  #include "hw/nix.h"
>  #include "hw/npa.h"
>  #include "hw/npc.h"
> +#include "hw/ree.h"
>  #include "hw/rvu.h"
>  #include "hw/sdp.h"
>  #include "hw/sso.h"
> @@ -86,6 +87,9 @@
>  #include "roc_ie_ot.h"
>  #include "roc_se.h"
>
> +/* REE */
> +#include "roc_ree.h"
> +
>  /* HASH computation */
>  #include "roc_hash.h"
>
> diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
> index 1e6427cf91..e1ffca31d4 100644
> --- a/drivers/common/cnxk/roc_constants.h
> +++ b/drivers/common/cnxk/roc_constants.h
> @@ -37,6 +37,8 @@
>  #define PCI_DEVID_CNXK_BPHY          0xA089
>  #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
>  #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
> +#define PCI_DEVID_CNXK_RVU_REE_PF     0xA0f4
> +#define PCI_DEVID_CNXK_RVU_REE_VF     0xA0f5
>
>  #define PCI_DEVID_CN9K_CGX  0xA059
>  #define PCI_DEVID_CN10K_RPM 0xA060
> diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
> index 75d1ff1ef3..4924620084 100644
> --- a/drivers/common/cnxk/roc_mbox.h
> +++ b/drivers/common/cnxk/roc_mbox.h
> @@ -148,6 +148,16 @@ struct mbox_msghdr {
>         M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)        \
>         M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,            \
>           cpt_eng_grp_rsp)                                                     \
> +       /* REE mbox IDs (range 0xE00 - 0xFFF) */                               \
> +       M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)        \
> +       M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,    \
> +         ree_rd_wr_reg_msg)                                                   \
> +       M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
> +         msg_rsp)                                                             \
> +       M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,        \
> +         ree_rule_db_len_rsp_msg)                                             \
> +       M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,    \
> +         ree_rule_db_get_rsp_msg)                                             \
>         /* SDP mbox IDs (range 0x1000 - 0x11FF) */                             \
>         M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg,     \
>           msg_rsp)                                                             \
> @@ -1394,6 +1404,96 @@ struct cpt_eng_grp_rsp {
>         uint8_t __io eng_grp_num;
>  };
>
> +/* REE mailbox error codes
> + * Range 1001 - 1100.
> + */
> +enum ree_af_status {
> +       REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
> +       REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
> +       REE_AF_ERR_LF_INVALID = -1003,
> +       REE_AF_ERR_ACCESS_DENIED = -1004,
> +       REE_AF_ERR_RULE_DB_PARTIAL = -1005,
> +       REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
> +       REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
> +       REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
> +       REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
> +       REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
> +       REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
> +       REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
> +       REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
> +       REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
> +       REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
> +       REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
> +       REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
> +       REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
> +       REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
> +       REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
> +       REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
> +       REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
> +       REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
> +};
> +
> +/* REE mbox message formats */
> +
> +struct ree_req_msg {
> +       struct mbox_msghdr hdr;
> +       uint32_t __io blkaddr;
> +};
> +
> +struct ree_lf_req_msg {
> +       struct mbox_msghdr hdr;
> +       uint32_t __io blkaddr;
> +       uint32_t __io size;
> +       uint8_t __io lf;
> +       uint8_t __io pri;
> +};
> +
> +struct ree_rule_db_prog_req_msg {
> +       struct mbox_msghdr hdr;
> +#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
> +       uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
> +       uint32_t __io blkaddr;       /* REE0 or REE1 */
> +       uint32_t __io total_len;     /* total len of rule db */
> +       uint32_t __io offset;        /* offset of current rule db block */
> +       uint16_t __io len;           /* length of rule db block */
> +       uint8_t __io is_last;        /* is this the last block */
> +       uint8_t __io is_incremental; /* is incremental flow */
> +       uint8_t __io is_dbi;         /* is rule db incremental */
> +};
> +
> +struct ree_rule_db_get_req_msg {
> +       struct mbox_msghdr hdr;
> +       uint32_t __io blkaddr;
> +       uint32_t __io offset; /* retrieve db from this offset */
> +       uint8_t __io is_dbi;  /* is request for rule db incremental */
> +};
> +
> +struct ree_rd_wr_reg_msg {
> +       struct mbox_msghdr hdr;
> +       uint64_t __io reg_offset;
> +       uint64_t __io *ret_val;
> +       uint64_t __io val;
> +       uint32_t __io blkaddr;
> +       uint8_t __io is_write;
> +};
> +
> +struct ree_rule_db_len_rsp_msg {
> +       struct mbox_msghdr hdr;
> +       uint32_t __io blkaddr;
> +       uint32_t __io len;
> +       uint32_t __io inc_len;
> +};
> +
> +struct ree_rule_db_get_rsp_msg {
> +       struct mbox_msghdr hdr;
> +#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
> +       uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
> +       uint32_t __io total_len; /* total len of rule db */
> +       uint32_t __io offset;    /* offset of current rule db block */
> +       uint16_t __io len;       /* length of rule db block */
> +       uint8_t __io is_last;    /* is this the last block */
> +};
> +
>  /* NPC mbox message structs */
>
>  #define NPC_MCAM_ENTRY_INVALID 0xFFFF
> diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c
> index 74dbdeceb9..ebb6225f4d 100644
> --- a/drivers/common/cnxk/roc_platform.c
> +++ b/drivers/common/cnxk/roc_platform.c
> @@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
>  RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
>  RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
>  RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
> +RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
> diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
> index 241655b334..4f48a8e282 100644
> --- a/drivers/common/cnxk/roc_platform.h
> +++ b/drivers/common/cnxk/roc_platform.h
> @@ -152,6 +152,7 @@ extern int cnxk_logtype_npc;
>  extern int cnxk_logtype_sso;
>  extern int cnxk_logtype_tim;
>  extern int cnxk_logtype_tm;
> +extern int cnxk_logtype_ree;
>
>  #define plt_err(fmt, args...)                                                  \
>         RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
> @@ -176,6 +177,7 @@ extern int cnxk_logtype_tm;
>  #define plt_sso_dbg(fmt, ...)  plt_dbg(sso, fmt, ##__VA_ARGS__)
>  #define plt_tim_dbg(fmt, ...)  plt_dbg(tim, fmt, ##__VA_ARGS__)
>  #define plt_tm_dbg(fmt, ...)   plt_dbg(tm, fmt, ##__VA_ARGS__)
> +#define plt_ree_dbg(fmt, ...)  plt_dbg(ree, fmt, ##__VA_ARGS__)
>
>  /* Datapath logs */
>  #define plt_dp_err(fmt, args...)                                               \
> diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
> index f72bbd568f..b091d519cb 100644
> --- a/drivers/common/cnxk/roc_priv.h
> +++ b/drivers/common/cnxk/roc_priv.h
> @@ -41,4 +41,7 @@
>  /* NIX Inline dev */
>  #include "roc_nix_inl_priv.h"
>
> +/* REE */
> +#include "roc_ree_priv.h"
> +
>  #endif /* _ROC_PRIV_H_ */
> diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
> new file mode 100644
> index 0000000000..35ed9ab3d5
> --- /dev/null
> +++ b/drivers/common/cnxk/roc_ree.c
> @@ -0,0 +1,647 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#include "roc_api.h"
> +#include "roc_priv.h"
> +
> +/* This is temporarily here */

Remove this comment if it not valid.



> +#define REE0_PF 19
> +#define REE1_PF 20
> +
> +static int
> +roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
> +{
> +       struct free_rsrcs_rsp *rsp;
> +       struct dev *dev = vf->dev;
> +       int ret;
> +
> +       mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
> +
> +       ret = mbox_process_msg(dev->mbox, (void *)&rsp);
> +       if (ret)
> +               return -EIO;
> +
> +       if (vf->block_address == RVU_BLOCK_ADDR_REE0)
> +               *nb_queues = rsp->ree0;
> +       else
> +               *nb_queues = rsp->ree1;
> +       return 0;
> +}
> +
> +static int
> +roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
> +{
> +       uint64_t val;
> +       int ret;
> +
> +       ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
> +       if (ret)
> +               return ret;
> +
> +       *max_matches = val;
> +       return 0;
> +}
> +
> +int
> +roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
> +{
> +       struct rsrc_attach_req *req;
> +       struct mbox *mbox;
> +
> +       mbox = vf->dev->mbox;
> +       /* Ask AF to attach required LFs */
> +       req = mbox_alloc_msg_attach_resources(mbox);
> +       if (req == NULL) {
> +               plt_err("Could not allocate mailbox message");
> +               return -EFAULT;
> +       }
> +
> +       /* 1 LF = 1 queue */
> +       req->reelfs = nb_queues;
> +       req->ree_blkaddr = vf->block_address;
> +
> +       if (mbox_process(mbox) < 0)
> +               return -EIO;
> +
> +       /* Update number of attached queues */
> +       vf->nb_queues = nb_queues;
> +
> +       return 0;
> +}
> +
> +int
> +roc_ree_queues_detach(struct roc_ree_vf *vf)
> +{
> +       struct rsrc_detach_req *req;
> +       struct mbox *mbox;
> +
> +       mbox = vf->dev->mbox;
> +       req = mbox_alloc_msg_detach_resources(mbox);
> +       if (req == NULL) {
> +               plt_err("Could not allocate mailbox message");
> +               return -EFAULT;
> +       }
> +       req->reelfs = true;
> +       req->partial = true;
> +       if (mbox_process(mbox) < 0)
> +               return -EIO;
> +
> +       /* Queues have been detached */
> +       vf->nb_queues = 0;
> +
> +       return 0;
> +}
> +
> +int
> +roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
> +{
> +       struct msix_offset_rsp *rsp;
> +       struct mbox *mbox;
> +       uint32_t i, ret;
> +
> +       /* Get REE MSI-X vector offsets */
> +       mbox = vf->dev->mbox;
> +       mbox_alloc_msg_msix_offset(mbox);
> +
> +       ret = mbox_process_msg(mbox, (void *)&rsp);
> +       if (ret)
> +               return ret;
> +
> +       for (i = 0; i < vf->nb_queues; i++) {
> +               if (vf->block_address == RVU_BLOCK_ADDR_REE0)
> +                       vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
> +               else
> +                       vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
> +               plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
> +       }
> +
> +       return 0;
> +}
> +
> +static int
> +ree_send_mbox_msg(struct roc_ree_vf *vf)
> +{
> +       struct mbox *mbox = vf->dev->mbox;
> +       int ret;
> +
> +       mbox_msg_send(mbox, 0);
> +
> +       ret = mbox_wait_for_rsp(mbox, 0);
> +       if (ret < 0) {
> +               plt_err("Could not get mailbox response");
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +int
> +roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t size)
> +{
> +       struct ree_lf_req_msg *req;
> +       struct mbox *mbox;
> +       int ret;
> +
> +       mbox = vf->dev->mbox;
> +       req = mbox_alloc_msg_ree_config_lf(mbox);
> +       if (req == NULL) {
> +               plt_err("Could not allocate mailbox message");
> +               return -EFAULT;
> +       }
> +
> +       req->lf = lf;
> +       req->pri = pri ? 1 : 0;
> +       req->size = size;
> +       req->blkaddr = vf->block_address;
> +
> +       ret = mbox_process(mbox);
> +       if (ret < 0) {
> +               plt_err("Could not get mailbox response");
> +               return ret;
> +       }
> +       return 0;
> +}
> +
> +int
> +roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
> +{
> +       struct ree_rd_wr_reg_msg *msg;
> +       struct mbox_dev *mdev;
> +       struct mbox *mbox;
> +       int ret, off;
> +
> +       mbox = vf->dev->mbox;
> +       mdev = &mbox->dev[0];
> +       msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
> +               mbox, 0, sizeof(*msg), sizeof(*msg));
> +       if (msg == NULL) {
> +               plt_err("Could not allocate mailbox message");
> +               return -EFAULT;
> +       }
> +
> +       msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
> +       msg->hdr.sig = MBOX_REQ_SIG;
> +       msg->hdr.pcifunc = vf->dev->pf_func;
> +       msg->is_write = 0;
> +       msg->reg_offset = reg;
> +       msg->ret_val = val;
> +       msg->blkaddr = vf->block_address;
> +
> +       ret = ree_send_mbox_msg(vf);
> +       if (ret < 0)
> +               return ret;
> +
> +       off = mbox->rx_start +
> +             RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
> +       msg = (struct ree_rd_wr_reg_msg *)((uintptr_t)mdev->mbase + off);
> +
> +       *val = msg->val;
> +
> +       return 0;
> +}
> +
> +int
> +roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg, uint64_t val)
> +{
> +       struct ree_rd_wr_reg_msg *msg;
> +       struct mbox *mbox;
> +
> +       mbox = vf->dev->mbox;
> +       msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
> +               mbox, 0, sizeof(*msg), sizeof(*msg));
> +       if (msg == NULL) {
> +               plt_err("Could not allocate mailbox message");
> +               return -EFAULT;
> +       }
> +
> +       msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
> +       msg->hdr.sig = MBOX_REQ_SIG;
> +       msg->hdr.pcifunc = vf->dev->pf_func;
> +       msg->is_write = 1;
> +       msg->reg_offset = reg;
> +       msg->val = val;
> +       msg->blkaddr = vf->block_address;
> +
> +       return ree_send_mbox_msg(vf);
> +}
> +
> +int
> +roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db, uint32_t rule_db_len,
> +                   char *rule_dbi, uint32_t rule_dbi_len)
> +{
> +       struct ree_rule_db_get_req_msg *req;
> +       struct ree_rule_db_get_rsp_msg *rsp;
> +       char *rule_db_ptr = (char *)rule_db;
> +       struct mbox *mbox;
> +       int ret, last = 0;
> +       uint32_t len = 0;
> +
> +       mbox = vf->dev->mbox;
> +       if (!rule_db) {
> +               plt_err("Couldn't return rule db due to NULL pointer");
> +               return -EFAULT;
> +       }
> +
> +       while (!last) {
> +               req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
> +                       mbox, 0, sizeof(*req), sizeof(*rsp));
> +               if (!req) {
> +                       plt_err("Could not allocate mailbox message");
> +                       return -EFAULT;
> +               }
> +
> +               req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
> +               req->hdr.sig = MBOX_REQ_SIG;
> +               req->hdr.pcifunc = vf->dev->pf_func;
> +               req->blkaddr = vf->block_address;
> +               req->is_dbi = 0;
> +               req->offset = len;
> +               ret = mbox_process_msg(mbox, (void *)&rsp);
> +               if (ret)
> +                       return ret;
> +               if (rule_db_len < len + rsp->len) {
> +                       plt_err("Rule db size is too small");
> +                       return -EFAULT;
> +               }
> +               mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
> +               len += rsp->len;
> +               rule_db_ptr = rule_db_ptr + rsp->len;
> +               last = rsp->is_last;
> +       }
> +
> +       if (rule_dbi) {
> +               req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
> +                       mbox, 0, sizeof(*req), sizeof(*rsp));
> +               if (!req) {
> +                       plt_err("Could not allocate mailbox message");
> +                       return -EFAULT;
> +               }
> +
> +               req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
> +               req->hdr.sig = MBOX_REQ_SIG;
> +               req->hdr.pcifunc = vf->dev->pf_func;
> +               req->blkaddr = vf->block_address;
> +               req->is_dbi = 1;
> +               req->offset = 0;
> +
> +               ret = mbox_process_msg(mbox, (void *)&rsp);
> +               if (ret)
> +                       return ret;
> +               if (rule_dbi_len < rsp->len) {
> +                       plt_err("Rule dbi size is too small");
> +                       return -EFAULT;
> +               }
> +               mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
> +       }
> +       return 0;
> +}
> +
> +int
> +roc_ree_rule_db_len_get(struct roc_ree_vf *vf, uint32_t *rule_db_len,
> +                       uint32_t *rule_dbi_len)
> +{
> +       struct ree_rule_db_len_rsp_msg *rsp;
> +       struct ree_req_msg *req;
> +       struct mbox *mbox;
> +       int ret;
> +
> +       mbox = vf->dev->mbox;
> +       req = (struct ree_req_msg *)mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
> +                                                      sizeof(*rsp));
> +       if (!req) {
> +               plt_err("Could not allocate mailbox message");
> +               return -EFAULT;
> +       }
> +
> +       req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
> +       req->hdr.sig = MBOX_REQ_SIG;
> +       req->hdr.pcifunc = vf->dev->pf_func;
> +       req->blkaddr = vf->block_address;
> +       ret = mbox_process_msg(mbox, (void *)&rsp);
> +       if (ret)
> +               return ret;
> +       if (rule_db_len != NULL)
> +               *rule_db_len = rsp->len;
> +       if (rule_dbi_len != NULL)
> +               *rule_dbi_len = rsp->inc_len;
> +
> +       return 0;
> +}
> +
> +static int
> +ree_db_msg(struct roc_ree_vf *vf, const char *db, uint32_t db_len, int inc,
> +          int dbi)
> +{
> +       uint32_t len_left = db_len, offset = 0;
> +       struct ree_rule_db_prog_req_msg *req;
> +       const char *rule_db_ptr = db;
> +       struct mbox *mbox;
> +       struct msg_rsp *rsp;
> +       int ret;
> +
> +       mbox = vf->dev->mbox;
> +       while (len_left) {
> +               req = (struct ree_rule_db_prog_req_msg *)mbox_alloc_msg_rsp(
> +                       mbox, 0, sizeof(*req), sizeof(*rsp));
> +               if (!req) {
> +                       plt_err("Could not allocate mailbox message");
> +                       return -EFAULT;
> +               }
> +               req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
> +               req->hdr.sig = MBOX_REQ_SIG;
> +               req->hdr.pcifunc = vf->dev->pf_func;
> +               req->offset = offset;
> +               req->total_len = db_len;
> +               req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
> +               req->is_incremental = inc;
> +               req->is_dbi = dbi;
> +               req->blkaddr = vf->block_address;
> +
> +               if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
> +                       req->is_last = true;
> +                       req->len = len_left;
> +               }
> +               mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
> +               ret = mbox_process_msg(mbox, (void *)&rsp);
> +               if (ret) {
> +                       plt_err("Programming mailbox processing failed");
> +                       return ret;
> +               }
> +               len_left -= req->len;
> +               offset += req->len;
> +               rule_db_ptr = rule_db_ptr + req->len;
> +       }
> +       return 0;
> +}
> +
> +int
> +roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
> +                    uint32_t rule_db_len, const char *rule_dbi,
> +                    uint32_t rule_dbi_len)
> +{
> +       int inc, ret;
> +
> +       if (rule_db_len == 0) {
> +               plt_err("Couldn't program empty rule db");
> +               return -EFAULT;
> +       }
> +       inc = (rule_dbi_len != 0);
> +       if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
> +               plt_err("Couldn't program NULL rule db");
> +               return -EFAULT;
> +       }
> +       if (inc) {
> +               ret = ree_db_msg(vf, rule_dbi, rule_dbi_len, inc, 1);
> +               if (ret)
> +                       return ret;
> +       }
> +       return ree_db_msg(vf, rule_db, rule_db_len, inc, 0);
> +}
> +
> +static int
> +ree_get_blkaddr(struct dev *dev)
> +{
> +       int pf;
> +
> +       pf = dev_get_pf(dev->pf_func);
> +       if (pf == REE0_PF)
> +               return RVU_BLOCK_ADDR_REE0;
> +       else if (pf == REE1_PF)
> +               return RVU_BLOCK_ADDR_REE1;
> +       else
> +               return 0;
> +}
> +
> +uintptr_t
> +roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id)
> +{
> +       return REE_LF_BAR2(vf, qp_id);
> +}
> +
> +static void
> +roc_ree_lf_err_intr_handler(void *param)
> +{
> +       uintptr_t base = (uintptr_t)param;
> +       uint8_t lf_id;
> +       uint64_t intr;
> +
> +       lf_id = (base >> 12) & 0xFF;
> +
> +       intr = plt_read64(base + REE_LF_MISC_INT);
> +       if (intr == 0)
> +               return;
> +
> +       plt_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
> +
> +       /* Clear interrupt */
> +       plt_write64(intr, base + REE_LF_MISC_INT);
> +}
> +
> +static void
> +roc_ree_lf_err_intr_unregister(struct roc_ree_vf *vf, uint16_t msix_off,
> +                              uintptr_t base)
> +{
> +       struct rte_pci_device *pci_dev = vf->pci_dev;
> +       struct rte_intr_handle *handle = &pci_dev->intr_handle;
> +
> +       /* Disable error interrupts */
> +       plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
> +
> +       dev_irq_unregister(handle, roc_ree_lf_err_intr_handler, (void *)base,
> +                          msix_off);
> +}
> +
> +void
> +roc_ree_err_intr_unregister(struct roc_ree_vf *vf)
> +{
> +       uintptr_t base;
> +       uint32_t i;
> +
> +       for (i = 0; i < vf->nb_queues; i++) {
> +               base = REE_LF_BAR2(vf, i);
> +               roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base);
> +       }
> +
> +       vf->err_intr_registered = 0;
> +}
> +
> +static int
> +roc_ree_lf_err_intr_register(struct roc_ree_vf *vf, uint16_t msix_off,
> +                            uintptr_t base)
> +{
> +       struct rte_pci_device *pci_dev = vf->pci_dev;
> +       struct rte_intr_handle *handle = &pci_dev->intr_handle;
> +       int ret;
> +
> +       /* Disable error interrupts */
> +       plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
> +
> +       /* Register error interrupt handler */
> +       ret = dev_irq_register(handle, roc_ree_lf_err_intr_handler,
> +                              (void *)base, msix_off);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable error interrupts */
> +       plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1S);
> +
> +       return 0;
> +}
> +
> +int
> +roc_ree_err_intr_register(struct roc_ree_vf *vf)
> +{
> +       uint32_t i, j, ret;
> +       uintptr_t base;
> +
> +       for (i = 0; i < vf->nb_queues; i++) {
> +               if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
> +                       plt_err("Invalid REE LF MSI-X offset: 0x%x",
> +                               vf->lf_msixoff[i]);
> +                       return -EINVAL;
> +               }
> +       }
> +
> +       for (i = 0; i < vf->nb_queues; i++) {
> +               base = REE_LF_BAR2(vf, i);
> +               ret = roc_ree_lf_err_intr_register(vf, vf->lf_msixoff[i], base);
> +               if (ret)
> +                       goto intr_unregister;
> +       }
> +
> +       vf->err_intr_registered = 1;
> +       return 0;
> +
> +intr_unregister:
> +       /* Unregister the ones already registered */
> +       for (j = 0; j < i; j++) {
> +               base = REE_LF_BAR2(vf, j);
> +               roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[j], base);
> +       }
> +       return ret;
> +}
> +
> +int
> +roc_ree_iq_enable(struct roc_ree_vf *vf, const struct roc_ree_qp *qp,
> +                 uint8_t pri, uint32_t size_div2)
> +{
> +       union ree_lf_sbuf_addr base;
> +       union ree_lf_ena lf_ena;
> +
> +       /* Set instruction queue size and priority */
> +       roc_ree_config_lf(vf, qp->id, pri, size_div2);
> +
> +       /* Set instruction queue base address */
> +       /* Should be written after SBUF_CTL and before LF_ENA */
> +
> +       base.u = plt_read64(qp->base + REE_LF_SBUF_ADDR);
> +       base.s.ptr = qp->iq_dma_addr >> 7;
> +       plt_write64(base.u, qp->base + REE_LF_SBUF_ADDR);
> +
> +       /* Enable instruction queue */
> +
> +       lf_ena.u = plt_read64(qp->base + REE_LF_ENA);
> +       lf_ena.s.ena = 1;
> +       plt_write64(lf_ena.u, qp->base + REE_LF_ENA);
> +
> +       return 0;
> +}
> +
> +void
> +roc_ree_iq_disable(struct roc_ree_qp *qp)
> +{
> +       union ree_lf_ena lf_ena;
> +
> +       /* Stop instruction execution */
> +       lf_ena.u = plt_read64(qp->base + REE_LF_ENA);
> +       lf_ena.s.ena = 0x0;
> +       plt_write64(lf_ena.u, qp->base + REE_LF_ENA);
> +}
> +
> +int
> +roc_ree_dev_init(struct roc_ree_vf *vf)
> +{
> +       struct plt_pci_device *pci_dev;
> +       struct ree *ree;
> +       struct dev *dev;
> +       uint8_t max_matches = 0;
> +       uint16_t nb_queues = 0;
> +       int rc;
> +
> +       if (vf == NULL || vf->pci_dev == NULL)
> +               return -EINVAL;
> +
> +       PLT_STATIC_ASSERT(sizeof(struct ree) <= ROC_REE_MEM_SZ);
> +
> +       ree = roc_ree_to_ree_priv(vf);
> +       memset(ree, 0, sizeof(*ree));
> +       vf->dev = &ree->dev;
> +
> +       pci_dev = vf->pci_dev;
> +       dev = vf->dev;
> +
> +       /* Initialize device  */
> +       rc = dev_init(dev, pci_dev);
> +       if (rc) {
> +               plt_err("Failed to init roc device");
> +               goto fail;
> +       }
> +
> +       /* Get REE block address */
> +       vf->block_address = ree_get_blkaddr(dev);
> +       if (!vf->block_address) {
> +               plt_err("Could not determine block PF number");
> +               goto fail;
> +       }
> +
> +       /* Get number of queues available on the device */
> +       rc = roc_ree_available_queues_get(vf, &nb_queues);
> +       if (rc) {
> +               plt_err("Could not determine the number of queues available");
> +               goto fail;
> +       }
> +
> +       /* Don't exceed the limits set per VF */
> +       nb_queues = RTE_MIN(nb_queues, REE_MAX_QUEUES_PER_VF);
> +
> +       if (nb_queues == 0) {
> +               plt_err("No free queues available on the device");
> +               goto fail;
> +       }
> +
> +       vf->max_queues = nb_queues;
> +
> +       plt_ree_dbg("Max queues supported by device: %d", vf->max_queues);
> +
> +       /* Get number of maximum matches supported on the device */
> +       rc = roc_ree_max_matches_get(vf, &max_matches);
> +       if (rc) {
> +               plt_err("Could not determine the maximum matches supported");
> +               goto fail;
> +       }
> +       /* Don't exceed the limits set per VF */
> +       max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
> +       if (max_matches == 0) {
> +               plt_err("Could not determine the maximum matches supported");
> +               goto fail;
> +       }
> +
> +       vf->max_matches = max_matches;
> +
> +       plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
> +fail:
> +       return rc;
> +}
> +
> +int
> +roc_ree_dev_fini(struct roc_ree_vf *vf)
> +{
> +       if (vf == NULL)
> +               return -EINVAL;
> +
> +       vf->max_matches = 0;
> +       vf->max_queues = 0;
> +
> +       return dev_fini(vf->dev, vf->pci_dev);
> +}
> diff --git a/drivers/common/cnxk/roc_ree.h b/drivers/common/cnxk/roc_ree.h
> new file mode 100644
> index 0000000000..e138e4de66
> --- /dev/null
> +++ b/drivers/common/cnxk/roc_ree.h
> @@ -0,0 +1,137 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#ifndef _ROC_REE_H_
> +#define _ROC_REE_H_
> +
> +#include "roc_api.h"
> +
> +#define REE_MAX_LFS           36
> +#define REE_MAX_QUEUES_PER_VF  36
> +#define REE_MAX_MATCHES_PER_VF 254
> +
> +#define REE_MAX_PAYLOAD_SIZE (1 << 14)
> +
> +#define REE_NON_INC_PROG 0
> +#define REE_INC_PROG    1
> +
> +#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)
> +
> +/**
> + * Device vf data
> + */
> +struct roc_ree_vf {
> +       struct plt_pci_device *pci_dev;
> +       struct dev *dev;
> +       /**< Base class */
> +       uint16_t max_queues;
> +       /**< Max queues supported */
> +       uint8_t nb_queues;
> +       /**< Number of regex queues attached */
> +       uint16_t max_matches;
> +       /**<  Max matches supported*/
> +       uint16_t lf_msixoff[REE_MAX_LFS];
> +       /**< MSI-X offsets */
> +       uint8_t block_address;
> +       /**< REE Block Address */
> +       uint8_t err_intr_registered : 1;
> +       /**< Are error interrupts registered? */
> +
> +#define ROC_REE_MEM_SZ (6 * 1024)
> +       uint8_t reserved[ROC_REE_MEM_SZ] __plt_cache_aligned;
> +} __plt_cache_aligned;
> +
> +struct roc_ree_rid {
> +       uintptr_t rid;
> +       /** Request id of a ree operation */
> +       uint64_t user_id;
> +       /* Client data */
> +       /**< IOVA address of the pattern to be matched. */
> +};
> +
> +struct roc_ree_pending_queue {
> +       uint64_t pending_count;
> +       /** Pending requests count */
> +       struct roc_ree_rid *rid_queue;
> +       /** Array of pending requests */
> +       uint16_t enq_tail;
> +       /** Tail of queue to be used for enqueue */
> +       uint16_t deq_head;
> +       /** Head of queue to be used for dequeue */
> +};
> +
> +struct roc_ree_qp {
> +       uint32_t id;
> +       /**< Queue pair id */
> +       uintptr_t base;
> +       /**< Base address where BAR is mapped */
> +       struct roc_ree_pending_queue pend_q;
> +       /**< Pending queue */
> +       rte_iova_t iq_dma_addr;
> +       /**< Instruction queue address */
> +       uint32_t roc_regexdev_jobid;
> +       /**< Job ID */
> +       uint32_t write_offset;
> +       /**< write offset */
> +};
> +
> +union roc_ree_inst {
> +       uint64_t u[8];
> +       struct {
> +               uint64_t doneint : 1;
> +               uint64_t reserved_1_3 : 3;
> +               uint64_t dg : 1;
> +               uint64_t reserved_5_7 : 3;
> +               uint64_t ooj : 1;
> +               uint64_t reserved_9_15 : 7;
> +               uint64_t reserved_16_63 : 48;
> +               uint64_t inp_ptr_addr : 64;
> +               uint64_t inp_ptr_ctl : 64;
> +               uint64_t res_ptr_addr : 64;
> +               uint64_t wq_ptr : 64;
> +               uint64_t tag : 32;
> +               uint64_t tt : 2;
> +               uint64_t ggrp : 10;
> +               uint64_t reserved_364_383 : 20;
> +               uint64_t reserved_384_391 : 8;
> +               uint64_t ree_job_id : 24;
> +               uint64_t ree_job_ctrl : 16;
> +               uint64_t ree_job_length : 15;
> +               uint64_t reserved_447_447 : 1;
> +               uint64_t ree_job_subset_id_0 : 16;
> +               uint64_t ree_job_subset_id_1 : 16;
> +               uint64_t ree_job_subset_id_2 : 16;
> +               uint64_t ree_job_subset_id_3 : 16;
> +       } cn98xx;
> +};
> +
> +int __roc_api roc_ree_dev_init(struct roc_ree_vf *vf);
> +int __roc_api roc_ree_dev_fini(struct roc_ree_vf *vf);
> +int __roc_api roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues);
> +int __roc_api roc_ree_queues_detach(struct roc_ree_vf *vf);
> +int __roc_api roc_ree_msix_offsets_get(struct roc_ree_vf *vf);
> +int __roc_api roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri,
> +                               uint32_t size);
> +int __roc_api roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg,
> +                                 uint64_t *val);
> +int __roc_api roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg,
> +                                  uint64_t val);
> +int __roc_api roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db,
> +                                 uint32_t rule_db_len, char *rule_dbi,
> +                                 uint32_t rule_dbi_len);
> +int __roc_api roc_ree_rule_db_len_get(struct roc_ree_vf *vf,
> +                                     uint32_t *rule_db_len,
> +                                     uint32_t *rule_dbi_len);
> +int __roc_api roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
> +                                  uint32_t rule_db_len, const char *rule_dbi,
> +                                  uint32_t rule_dbi_len);
> +uintptr_t __roc_api roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id);
> +void __roc_api roc_ree_err_intr_unregister(struct roc_ree_vf *vf);
> +int __roc_api roc_ree_err_intr_register(struct roc_ree_vf *vf);
> +int __roc_api roc_ree_iq_enable(struct roc_ree_vf *vf,
> +                               const struct roc_ree_qp *qp, uint8_t pri,
> +                               uint32_t size_div128);
> +void __roc_api roc_ree_iq_disable(struct roc_ree_qp *qp);
> +
> +#endif /* _ROC_REE_H_ */
> diff --git a/drivers/common/cnxk/roc_ree_priv.h b/drivers/common/cnxk/roc_ree_priv.h
> new file mode 100644
> index 0000000000..c39f7cf986
> --- /dev/null
> +++ b/drivers/common/cnxk/roc_ree_priv.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#ifndef _ROC_REE_PRIV_H_
> +#define _ROC_REE_PRIV_H_
> +
> +struct ree {
> +       struct dev dev;
> +} __plt_cache_aligned;
> +
> +static inline struct ree *
> +roc_ree_to_ree_priv(struct roc_ree_vf *roc_ree)
> +{
> +       return (struct ree *)&roc_ree->reserved[0];
> +}
> +
> +#endif /* _ROC_REE_PRIV_H_ */
> diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
> index 926d5c2167..e1e96d41d0 100644
> --- a/drivers/common/cnxk/version.map
> +++ b/drivers/common/cnxk/version.map
> @@ -11,6 +11,7 @@ INTERNAL {
>         cnxk_logtype_nix;
>         cnxk_logtype_npa;
>         cnxk_logtype_npc;
> +       cnxk_logtype_ree;
>         cnxk_logtype_sso;
>         cnxk_logtype_tim;
>         cnxk_logtype_tm;
> @@ -314,6 +315,21 @@ INTERNAL {
>         roc_tim_lf_enable;
>         roc_tim_lf_free;
>         roc_se_ctx_swap;
> -
> +       roc_ree_af_reg_read;
> +       roc_ree_af_reg_write;
> +       roc_ree_config_lf;
> +       roc_ree_dev_fini;
> +       roc_ree_dev_init;
> +       roc_ree_err_intr_register;
> +       roc_ree_err_intr_unregister;
> +       roc_ree_iq_disable;
> +       roc_ree_iq_enable;
> +       roc_ree_msix_offsets_get;
> +       roc_ree_qp_get_base;
> +       roc_ree_queues_attach;
> +       roc_ree_queues_detach;
> +       roc_ree_rule_db_get;
> +       roc_ree_rule_db_len_get;
> +       roc_ree_rule_db_prog;
>         local: *;
>  };
> --
> 2.28.0
>

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure
  2021-10-03  6:23 [dpdk-dev] [PATCH] common/cnxk: add REE support lironh
  2021-10-28  9:30 ` Jerin Jacob
@ 2021-11-23 19:13 ` lironh
  2021-11-23 19:13   ` [PATCH v2 1/5] common/cnxk: add REE HW definitions lironh
                     ` (7 more replies)
  1 sibling, 8 replies; 31+ messages in thread
From: lironh @ 2021-11-23 19:13 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 drivers/common/cnxk/hw/ree.h                  | 126 ++++
 drivers/common/cnxk/hw/rvu.h                  |   5 +
 drivers/common/cnxk/meson.build               |   1 +
 drivers/common/cnxk/roc_api.h                 |   4 +
 drivers/common/cnxk/roc_constants.h           |   2 +
 drivers/common/cnxk/roc_mbox.h                | 100 +++
 drivers/common/cnxk/roc_platform.c            |   1 +
 drivers/common/cnxk/roc_platform.h            |   2 +
 drivers/common/cnxk/roc_priv.h                |   3 +
 drivers/common/cnxk/roc_ree.c                 | 647 ++++++++++++++++++
 drivers/common/cnxk/roc_ree.h                 | 137 ++++
 drivers/common/cnxk/roc_ree_priv.h            |  18 +
 drivers/common/cnxk/version.map               |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +++++------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -----
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 31 files changed, 1331 insertions(+), 1202 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (68%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 1/5] common/cnxk: add REE HW definitions
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
@ 2021-11-23 19:13   ` lironh
  2021-11-23 19:13   ` [PATCH v2 2/5] common/cnxk: add REE mbox definitions lironh
                     ` (6 subsequent siblings)
  7 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-23 19:13 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

adding REE (Regular Expression Engine) HW definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/hw/ree.h | 126 +++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/hw/rvu.h |   5 ++
 2 files changed, 131 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/ree.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 0000000000..30af61d704
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BIT	   BIT_ULL(14)
+#define REE_STATUS_PMI_SOJ_BIT	   BIT_ULL(13)
+#define REE_STATUS_MP_CNT_DET_BIT  BIT_ULL(7)
+#define REE_STATUS_MM_CNT_DET_BIT  BIT_ULL(6)
+#define REE_STATUS_ML_CNT_DET_BIT  BIT_ULL(5)
+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT		0x120ull
+#define REE_LF_DONE_INT_W1S	0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT		0x300ull
+#define REE_LF_MISC_INT_W1S	0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA		0x10ull
+#define REE_LF_SBUF_ADDR	0x20ull
+#define REE_LF_DONE		0x100ull
+#define REE_LF_DONE_ACK		0x110ull
+#define REE_LF_DONE_WAIT	0x148ull
+#define REE_LF_DOORBELL		0x400ull
+#define REE_LF_OUTSTAND_JOB	0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a)     (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS	(0x0ull)
+#define REE_AF_INT_VEC_RVU	(0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ	(0x3ull)
+
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC	(0x1ull)
+
+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
+
+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)
+
+#define REE_LF_BAR2(vf, q_id)                                                  \
+	((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+	REE_TYPE_JOB_DESC = 0x0,
+	REE_TYPE_RESULT_DESC = 0x1,
+	REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_res_status {
+	uint64_t u;
+	struct {
+		uint64_t job_type : 3;
+		uint64_t mpt_cnt_det : 1;
+		uint64_t mst_cnt_det : 1;
+		uint64_t ml_cnt_det : 1;
+		uint64_t mm_cnt_det : 1;
+		uint64_t mp_cnt_det : 1;
+		uint64_t mode : 2;
+		uint64_t reserved_10_11 : 2;
+		uint64_t reserved_12_12 : 1;
+		uint64_t pmi_soj : 1;
+		uint64_t pmi_eoj : 1;
+		uint64_t reserved_15_15 : 1;
+		uint64_t reserved_16_63 : 48;
+	} s;
+};
+
+union ree_res {
+	uint64_t u[8];
+	struct ree_res_s_98 {
+		uint64_t done : 1;
+		uint64_t hwjid : 7;
+		uint64_t ree_res_job_id : 24;
+		uint64_t ree_res_status : 16;
+		uint64_t ree_res_dmcnt : 8;
+		uint64_t ree_res_mcnt : 8;
+		uint64_t ree_meta_ptcnt : 16;
+		uint64_t ree_meta_icnt : 16;
+		uint64_t ree_meta_lcnt : 16;
+		uint64_t ree_pmi_min_byte_ptr : 16;
+		uint64_t ree_err : 1;
+		uint64_t reserved_129_190 : 62;
+		uint64_t doneint : 1;
+		uint64_t reserved_192_255 : 64;
+		uint64_t reserved_256_319 : 64;
+		uint64_t reserved_320_383 : 64;
+		uint64_t reserved_384_447 : 64;
+		uint64_t reserved_448_511 : 64;
+	} s;
+};
+
+union ree_match {
+	uint64_t u;
+	struct {
+		uint64_t ree_rule_id : 32;
+		uint64_t start_ptr : 14;
+		uint64_t reserved_46_47 : 2;
+		uint64_t match_length : 15;
+		uint64_t reserved_63_6 : 1;
+	} s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM    (0x0ull)
 #define RVU_BLOCK_ADDR_LMT     (0x1ull)
@@ -147,6 +148,8 @@
 #define RVU_BLOCK_ADDR_NDC2    (0xeull)
 #define RVU_BLOCK_ADDR_R_END   (0x1full)
 #define RVU_BLOCK_ADDR_R_START (0x14ull)
+#define RVU_BLOCK_ADDR_REE0    (0x14ull)
+#define RVU_BLOCK_ADDR_REE1    (0x15ull)
 
 #define RVU_VF_INT_VEC_MBOX (0x0ull)
 
@@ -167,6 +170,7 @@
 #define NPA_AF_BAR2_SEL	 (0x9000000ull)
 #define CPT_AF_BAR2_SEL	 (0x9000000ull)
 #define RVU_AF_BAR2_SEL	 (0x9000000ull)
+#define REE_AF_BAR2_SEL	 (0x9000000ull)
 
 #define AF_BAR2_ALIASX(a, b)                                                   \
 	(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))
@@ -177,6 +181,7 @@
 #define NPA_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(0, b)
 #define CPT_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 #define RVU_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
+#define REE_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 
 /* Structures definitions */
 
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 2/5] common/cnxk: add REE mbox definitions
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
  2021-11-23 19:13   ` [PATCH v2 1/5] common/cnxk: add REE HW definitions lironh
@ 2021-11-23 19:13   ` lironh
  2021-11-23 19:13   ` [PATCH v2 3/5] common/cnxk: add REE support lironh
                     ` (5 subsequent siblings)
  7 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-23 19:13 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add REE mbox definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 100 +++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..e97d93e261 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -151,6 +151,16 @@ struct mbox_msghdr {
 	M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)        \
 	M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,            \
 	  cpt_eng_grp_rsp)                                                     \
+	/* REE mbox IDs (range 0xE00 - 0xFFF) */                               \
+	M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)        \
+	M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,    \
+	  ree_rd_wr_reg_msg)                                                   \
+	M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+	  msg_rsp)                                                             \
+	M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,        \
+	  ree_rule_db_len_rsp_msg)                                             \
+	M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,    \
+	  ree_rule_db_get_rsp_msg)                                             \
 	/* SDP mbox IDs (range 0x1000 - 0x11FF) */                             \
 	M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg,     \
 	  msg_rsp)                                                             \
@@ -1452,6 +1462,96 @@ struct cpt_eng_grp_rsp {
 	uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+	REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+	REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+	REE_AF_ERR_LF_INVALID = -1003,
+	REE_AF_ERR_ACCESS_DENIED = -1004,
+	REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+	REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+	REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+	REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+	REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+	REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+	REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+	REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+	REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+	REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+	REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+	REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+	REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+	REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+	REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+	REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+	REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+	REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+	REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io size;
+	uint8_t __io lf;
+	uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+	uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+	uint32_t __io blkaddr;	     /* REE0 or REE1 */
+	uint32_t __io total_len;     /* total len of rule db */
+	uint32_t __io offset;	     /* offset of current rule db block */
+	uint16_t __io len;	     /* length of rule db block */
+	uint8_t __io is_last;	     /* is this the last block */
+	uint8_t __io is_incremental; /* is incremental flow */
+	uint8_t __io is_dbi;	     /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io offset; /* retrieve db from this offset */
+	uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+	struct mbox_msghdr hdr;
+	uint64_t __io reg_offset;
+	uint64_t __io *ret_val;
+	uint64_t __io val;
+	uint32_t __io blkaddr;
+	uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io len;
+	uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+	uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+	uint32_t __io total_len; /* total len of rule db */
+	uint32_t __io offset;	 /* offset of current rule db block */
+	uint16_t __io len;	 /* length of rule db block */
+	uint8_t __io is_last;	 /* is this the last block */
+};
+
 /* NPC mbox message structs */
 
 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 3/5] common/cnxk: add REE support
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
  2021-11-23 19:13   ` [PATCH v2 1/5] common/cnxk: add REE HW definitions lironh
  2021-11-23 19:13   ` [PATCH v2 2/5] common/cnxk: add REE mbox definitions lironh
@ 2021-11-23 19:13   ` lironh
  2021-11-23 19:13   ` [PATCH v2 4/5] common/cnxk: link REE support to ROC files lironh
                     ` (4 subsequent siblings)
  7 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-23 19:13 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

extend cnxk infrastructure to support REE

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_ree.c      | 647 +++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ree.h      | 137 ++++++
 drivers/common/cnxk/roc_ree_priv.h |  18 +
 3 files changed, 802 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 0000000000..1eb2ae7272
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+	struct free_rsrcs_rsp *rsp;
+	struct dev *dev = vf->dev;
+	int ret;
+
+	mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+		*nb_queues = rsp->ree0;
+	else
+		*nb_queues = rsp->ree1;
+	return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+	uint64_t val;
+	int ret;
+
+	ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+	if (ret)
+		return ret;
+
+	*max_matches = val;
+	return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+	struct rsrc_attach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	/* Ask AF to attach required LFs */
+	req = mbox_alloc_msg_attach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	/* 1 LF = 1 queue */
+	req->reelfs = nb_queues;
+	req->ree_blkaddr = vf->block_address;
+
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Update number of attached queues */
+	vf->nb_queues = nb_queues;
+
+	return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+	struct rsrc_detach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_detach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+	req->reelfs = true;
+	req->partial = true;
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Queues have been detached */
+	vf->nb_queues = 0;
+
+	return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+	struct msix_offset_rsp *rsp;
+	struct mbox *mbox;
+	uint32_t i, ret;
+
+	/* Get REE MSI-X vector offsets */
+	mbox = vf->dev->mbox;
+	mbox_alloc_msg_msix_offset(mbox);
+
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+		else
+			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+		plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+	}
+
+	return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+	struct mbox *mbox = vf->dev->mbox;
+	int ret;
+
+	mbox_msg_send(mbox, 0);
+
+	ret = mbox_wait_for_rsp(mbox, 0);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+
+	return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t size)
+{
+	struct ree_lf_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_ree_config_lf(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->lf = lf;
+	req->pri = pri ? 1 : 0;
+	req->size = size;
+	req->blkaddr = vf->block_address;
+
+	ret = mbox_process(mbox);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+	return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox_dev *mdev;
+	struct mbox *mbox;
+	int ret, off;
+
+	mbox = vf->dev->mbox;
+	mdev = &mbox->dev[0];
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 0;
+	msg->reg_offset = reg;
+	msg->ret_val = val;
+	msg->blkaddr = vf->block_address;
+
+	ret = ree_send_mbox_msg(vf);
+	if (ret < 0)
+		return ret;
+
+	off = mbox->rx_start +
+	      RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+	msg = (struct ree_rd_wr_reg_msg *)((uintptr_t)mdev->mbase + off);
+
+	*val = msg->val;
+
+	return 0;
+}
+
+int
+roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg, uint64_t val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 1;
+	msg->reg_offset = reg;
+	msg->val = val;
+	msg->blkaddr = vf->block_address;
+
+	return ree_send_mbox_msg(vf);
+}
+
+int
+roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db, uint32_t rule_db_len,
+		    char *rule_dbi, uint32_t rule_dbi_len)
+{
+	struct ree_rule_db_get_req_msg *req;
+	struct ree_rule_db_get_rsp_msg *rsp;
+	char *rule_db_ptr = (char *)rule_db;
+	struct mbox *mbox;
+	int ret, last = 0;
+	uint32_t len = 0;
+
+	mbox = vf->dev->mbox;
+	if (!rule_db) {
+		plt_err("Couldn't return rule db due to NULL pointer");
+		return -EFAULT;
+	}
+
+	while (!last) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 0;
+		req->offset = len;
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_db_len < len + rsp->len) {
+			plt_err("Rule db size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
+		len += rsp->len;
+		rule_db_ptr = rule_db_ptr + rsp->len;
+		last = rsp->is_last;
+	}
+
+	if (rule_dbi) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 1;
+		req->offset = 0;
+
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_dbi_len < rsp->len) {
+			plt_err("Rule dbi size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_len_get(struct roc_ree_vf *vf, uint32_t *rule_db_len,
+			uint32_t *rule_dbi_len)
+{
+	struct ree_rule_db_len_rsp_msg *rsp;
+	struct ree_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = (struct ree_req_msg *)mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
+						       sizeof(*rsp));
+	if (!req) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
+	req->hdr.sig = MBOX_REQ_SIG;
+	req->hdr.pcifunc = vf->dev->pf_func;
+	req->blkaddr = vf->block_address;
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+	if (rule_db_len != NULL)
+		*rule_db_len = rsp->len;
+	if (rule_dbi_len != NULL)
+		*rule_dbi_len = rsp->inc_len;
+
+	return 0;
+}
+
+static int
+ree_db_msg(struct roc_ree_vf *vf, const char *db, uint32_t db_len, int inc,
+	   int dbi)
+{
+	uint32_t len_left = db_len, offset = 0;
+	struct ree_rule_db_prog_req_msg *req;
+	const char *rule_db_ptr = db;
+	struct mbox *mbox;
+	struct msg_rsp *rsp;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	while (len_left) {
+		req = (struct ree_rule_db_prog_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->offset = offset;
+		req->total_len = db_len;
+		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
+		req->is_incremental = inc;
+		req->is_dbi = dbi;
+		req->blkaddr = vf->block_address;
+
+		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
+			req->is_last = true;
+			req->len = len_left;
+		}
+		mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret) {
+			plt_err("Programming mailbox processing failed");
+			return ret;
+		}
+		len_left -= req->len;
+		offset += req->len;
+		rule_db_ptr = rule_db_ptr + req->len;
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+		     uint32_t rule_db_len, const char *rule_dbi,
+		     uint32_t rule_dbi_len)
+{
+	int inc, ret;
+
+	if (rule_db_len == 0) {
+		plt_err("Couldn't program empty rule db");
+		return -EFAULT;
+	}
+	inc = (rule_dbi_len != 0);
+	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
+		plt_err("Couldn't program NULL rule db");
+		return -EFAULT;
+	}
+	if (inc) {
+		ret = ree_db_msg(vf, rule_dbi, rule_dbi_len, inc, 1);
+		if (ret)
+			return ret;
+	}
+	return ree_db_msg(vf, rule_db, rule_db_len, inc, 0);
+}
+
+static int
+ree_get_blkaddr(struct dev *dev)
+{
+	int pf;
+
+	pf = dev_get_pf(dev->pf_func);
+	if (pf == REE0_PF)
+		return RVU_BLOCK_ADDR_REE0;
+	else if (pf == REE1_PF)
+		return RVU_BLOCK_ADDR_REE1;
+	else
+		return 0;
+}
+
+uintptr_t
+roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id)
+{
+	return REE_LF_BAR2(vf, qp_id);
+}
+
+static void
+roc_ree_lf_err_intr_handler(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint8_t lf_id;
+	uint64_t intr;
+
+	lf_id = (base >> 12) & 0xFF;
+
+	intr = plt_read64(base + REE_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
+
+	/* Clear interrupt */
+	plt_write64(intr, base + REE_LF_MISC_INT);
+}
+
+static void
+roc_ree_lf_err_intr_unregister(struct roc_ree_vf *vf, uint16_t msix_off,
+			       uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	dev_irq_unregister(pci_dev->intr_handle,
+			   roc_ree_lf_err_intr_handler, (void *)base, msix_off);
+}
+
+void
+roc_ree_err_intr_unregister(struct roc_ree_vf *vf)
+{
+	uintptr_t base;
+	uint32_t i;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base);
+	}
+
+	vf->err_intr_registered = 0;
+}
+
+static int
+roc_ree_lf_err_intr_register(struct roc_ree_vf *vf, uint16_t msix_off,
+			     uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+	int ret;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	/* Register error interrupt handler */
+	ret = dev_irq_register(pci_dev->intr_handle,
+			       roc_ree_lf_err_intr_handler, (void *)base,
+			       msix_off);
+	if (ret)
+		return ret;
+
+	/* Enable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1S);
+
+	return 0;
+}
+
+int
+roc_ree_err_intr_register(struct roc_ree_vf *vf)
+{
+	uint32_t i, j, ret;
+	uintptr_t base;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
+			plt_err("Invalid REE LF MSI-X offset: 0x%x",
+				vf->lf_msixoff[i]);
+			return -EINVAL;
+		}
+	}
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		ret = roc_ree_lf_err_intr_register(vf, vf->lf_msixoff[i], base);
+		if (ret)
+			goto intr_unregister;
+	}
+
+	vf->err_intr_registered = 1;
+	return 0;
+
+intr_unregister:
+	/* Unregister the ones already registered */
+	for (j = 0; j < i; j++) {
+		base = REE_LF_BAR2(vf, j);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[j], base);
+	}
+	return ret;
+}
+
+int
+roc_ree_iq_enable(struct roc_ree_vf *vf, const struct roc_ree_qp *qp,
+		  uint8_t pri, uint32_t size_div2)
+{
+	uint64_t val;
+
+	/* Set instruction queue size and priority */
+	roc_ree_config_lf(vf, qp->id, pri, size_div2);
+
+	/* Set instruction queue base address */
+	/* Should be written after SBUF_CTL and before LF_ENA */
+
+	val = plt_read64(qp->base + REE_LF_SBUF_ADDR);
+	val &= ~REE_LF_SBUF_ADDR_PTR_MASK;
+	val |= FIELD_PREP(REE_LF_SBUF_ADDR_PTR_MASK, qp->iq_dma_addr >> 7);
+	plt_write64(val, qp->base + REE_LF_SBUF_ADDR);
+
+	/* Enable instruction queue */
+
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 1);
+	plt_write64(val, qp->base + REE_LF_ENA);
+
+	return 0;
+}
+
+void
+roc_ree_iq_disable(struct roc_ree_qp *qp)
+{
+	uint64_t val;
+
+	/* Stop instruction execution */
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 0);
+	plt_write64(val, qp->base + REE_LF_ENA);
+}
+
+int
+roc_ree_dev_init(struct roc_ree_vf *vf)
+{
+	struct plt_pci_device *pci_dev;
+	struct ree *ree;
+	struct dev *dev;
+	uint8_t max_matches = 0;
+	uint16_t nb_queues = 0;
+	int rc;
+
+	if (vf == NULL || vf->pci_dev == NULL)
+		return -EINVAL;
+
+	PLT_STATIC_ASSERT(sizeof(struct ree) <= ROC_REE_MEM_SZ);
+
+	ree = roc_ree_to_ree_priv(vf);
+	memset(ree, 0, sizeof(*ree));
+	vf->dev = &ree->dev;
+
+	pci_dev = vf->pci_dev;
+	dev = vf->dev;
+
+	/* Initialize device  */
+	rc = dev_init(dev, pci_dev);
+	if (rc) {
+		plt_err("Failed to init roc device");
+		goto fail;
+	}
+
+	/* Get REE block address */
+	vf->block_address = ree_get_blkaddr(dev);
+	if (!vf->block_address) {
+		plt_err("Could not determine block PF number");
+		goto fail;
+	}
+
+	/* Get number of queues available on the device */
+	rc = roc_ree_available_queues_get(vf, &nb_queues);
+	if (rc) {
+		plt_err("Could not determine the number of queues available");
+		goto fail;
+	}
+
+	/* Don't exceed the limits set per VF */
+	nb_queues = RTE_MIN(nb_queues, REE_MAX_QUEUES_PER_VF);
+
+	if (nb_queues == 0) {
+		plt_err("No free queues available on the device");
+		goto fail;
+	}
+
+	vf->max_queues = nb_queues;
+
+	plt_ree_dbg("Max queues supported by device: %d", vf->max_queues);
+
+	/* Get number of maximum matches supported on the device */
+	rc = roc_ree_max_matches_get(vf, &max_matches);
+	if (rc) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+	/* Don't exceed the limits set per VF */
+	max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
+	if (max_matches == 0) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+
+	vf->max_matches = max_matches;
+
+	plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+fail:
+	return rc;
+}
+
+int
+roc_ree_dev_fini(struct roc_ree_vf *vf)
+{
+	if (vf == NULL)
+		return -EINVAL;
+
+	vf->max_matches = 0;
+	vf->max_queues = 0;
+
+	return dev_fini(vf->dev, vf->pci_dev);
+}
diff --git a/drivers/common/cnxk/roc_ree.h b/drivers/common/cnxk/roc_ree.h
new file mode 100644
index 0000000000..e138e4de66
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_H_
+#define _ROC_REE_H_
+
+#include "roc_api.h"
+
+#define REE_MAX_LFS	       36
+#define REE_MAX_QUEUES_PER_VF  36
+#define REE_MAX_MATCHES_PER_VF 254
+
+#define REE_MAX_PAYLOAD_SIZE (1 << 14)
+
+#define REE_NON_INC_PROG 0
+#define REE_INC_PROG	 1
+
+#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)
+
+/**
+ * Device vf data
+ */
+struct roc_ree_vf {
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	/**< Base class */
+	uint16_t max_queues;
+	/**< Max queues supported */
+	uint8_t nb_queues;
+	/**< Number of regex queues attached */
+	uint16_t max_matches;
+	/**<  Max matches supported*/
+	uint16_t lf_msixoff[REE_MAX_LFS];
+	/**< MSI-X offsets */
+	uint8_t block_address;
+	/**< REE Block Address */
+	uint8_t err_intr_registered : 1;
+	/**< Are error interrupts registered? */
+
+#define ROC_REE_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_REE_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+struct roc_ree_rid {
+	uintptr_t rid;
+	/** Request id of a ree operation */
+	uint64_t user_id;
+	/* Client data */
+	/**< IOVA address of the pattern to be matched. */
+};
+
+struct roc_ree_pending_queue {
+	uint64_t pending_count;
+	/** Pending requests count */
+	struct roc_ree_rid *rid_queue;
+	/** Array of pending requests */
+	uint16_t enq_tail;
+	/** Tail of queue to be used for enqueue */
+	uint16_t deq_head;
+	/** Head of queue to be used for dequeue */
+};
+
+struct roc_ree_qp {
+	uint32_t id;
+	/**< Queue pair id */
+	uintptr_t base;
+	/**< Base address where BAR is mapped */
+	struct roc_ree_pending_queue pend_q;
+	/**< Pending queue */
+	rte_iova_t iq_dma_addr;
+	/**< Instruction queue address */
+	uint32_t roc_regexdev_jobid;
+	/**< Job ID */
+	uint32_t write_offset;
+	/**< write offset */
+};
+
+union roc_ree_inst {
+	uint64_t u[8];
+	struct {
+		uint64_t doneint : 1;
+		uint64_t reserved_1_3 : 3;
+		uint64_t dg : 1;
+		uint64_t reserved_5_7 : 3;
+		uint64_t ooj : 1;
+		uint64_t reserved_9_15 : 7;
+		uint64_t reserved_16_63 : 48;
+		uint64_t inp_ptr_addr : 64;
+		uint64_t inp_ptr_ctl : 64;
+		uint64_t res_ptr_addr : 64;
+		uint64_t wq_ptr : 64;
+		uint64_t tag : 32;
+		uint64_t tt : 2;
+		uint64_t ggrp : 10;
+		uint64_t reserved_364_383 : 20;
+		uint64_t reserved_384_391 : 8;
+		uint64_t ree_job_id : 24;
+		uint64_t ree_job_ctrl : 16;
+		uint64_t ree_job_length : 15;
+		uint64_t reserved_447_447 : 1;
+		uint64_t ree_job_subset_id_0 : 16;
+		uint64_t ree_job_subset_id_1 : 16;
+		uint64_t ree_job_subset_id_2 : 16;
+		uint64_t ree_job_subset_id_3 : 16;
+	} cn98xx;
+};
+
+int __roc_api roc_ree_dev_init(struct roc_ree_vf *vf);
+int __roc_api roc_ree_dev_fini(struct roc_ree_vf *vf);
+int __roc_api roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues);
+int __roc_api roc_ree_queues_detach(struct roc_ree_vf *vf);
+int __roc_api roc_ree_msix_offsets_get(struct roc_ree_vf *vf);
+int __roc_api roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri,
+				uint32_t size);
+int __roc_api roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg,
+				  uint64_t *val);
+int __roc_api roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg,
+				   uint64_t val);
+int __roc_api roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db,
+				  uint32_t rule_db_len, char *rule_dbi,
+				  uint32_t rule_dbi_len);
+int __roc_api roc_ree_rule_db_len_get(struct roc_ree_vf *vf,
+				      uint32_t *rule_db_len,
+				      uint32_t *rule_dbi_len);
+int __roc_api roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+				   uint32_t rule_db_len, const char *rule_dbi,
+				   uint32_t rule_dbi_len);
+uintptr_t __roc_api roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id);
+void __roc_api roc_ree_err_intr_unregister(struct roc_ree_vf *vf);
+int __roc_api roc_ree_err_intr_register(struct roc_ree_vf *vf);
+int __roc_api roc_ree_iq_enable(struct roc_ree_vf *vf,
+				const struct roc_ree_qp *qp, uint8_t pri,
+				uint32_t size_div128);
+void __roc_api roc_ree_iq_disable(struct roc_ree_qp *qp);
+
+#endif /* _ROC_REE_H_ */
diff --git a/drivers/common/cnxk/roc_ree_priv.h b/drivers/common/cnxk/roc_ree_priv.h
new file mode 100644
index 0000000000..c39f7cf986
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree_priv.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_PRIV_H_
+#define _ROC_REE_PRIV_H_
+
+struct ree {
+	struct dev dev;
+} __plt_cache_aligned;
+
+static inline struct ree *
+roc_ree_to_ree_priv(struct roc_ree_vf *roc_ree)
+{
+	return (struct ree *)&roc_ree->reserved[0];
+}
+
+#endif /* _ROC_REE_PRIV_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 4/5] common/cnxk: link REE support to ROC files
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
                     ` (2 preceding siblings ...)
  2021-11-23 19:13   ` [PATCH v2 3/5] common/cnxk: add REE support lironh
@ 2021-11-23 19:13   ` lironh
  2021-11-23 19:13   ` [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure lironh
                     ` (3 subsequent siblings)
  7 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-23 19:13 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add references to REE files from ROC files

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/meson.build     |  1 +
 drivers/common/cnxk/roc_api.h       |  4 ++++
 drivers/common/cnxk/roc_constants.h |  2 ++
 drivers/common/cnxk/roc_platform.c  |  1 +
 drivers/common/cnxk/roc_platform.h  |  2 ++
 drivers/common/cnxk/roc_priv.h      |  3 +++
 drivers/common/cnxk/version.map     | 18 +++++++++++++++++-
 7 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4928f7e549..7e27b3cc0a 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -61,6 +61,7 @@ sources = files(
         'roc_tim.c',
         'roc_tim_irq.c',
         'roc_utils.c',
+        'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index e7aaa07563..1b46c21f7f 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -37,6 +37,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -90,6 +91,9 @@
 /* DPI */
 #include "roc_dpi.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
index ac7335061c..5f78823642 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY	      0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF     0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF     0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 61d4781209..85aa6dcebc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)                                                  \
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)	plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)	plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)	plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)	plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)                                               \
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 782b90cf8d..122d411fe7 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,4 +44,7 @@
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..5a03b91784 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_nix;
 	cnxk_logtype_npa;
 	cnxk_logtype_npc;
+	cnxk_logtype_ree;
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
@@ -347,6 +348,21 @@ INTERNAL {
 	roc_tim_lf_enable;
 	roc_tim_lf_free;
 	roc_se_ctx_swap;
-
+	roc_ree_af_reg_read;
+	roc_ree_af_reg_write;
+	roc_ree_config_lf;
+	roc_ree_dev_fini;
+	roc_ree_dev_init;
+	roc_ree_err_intr_register;
+	roc_ree_err_intr_unregister;
+	roc_ree_iq_disable;
+	roc_ree_iq_enable;
+	roc_ree_msix_offsets_get;
+	roc_ree_qp_get_base;
+	roc_ree_queues_attach;
+	roc_ree_queues_detach;
+	roc_ree_rule_db_get;
+	roc_ree_rule_db_len_get;
+	roc_ree_rule_db_prog;
 	local: *;
 };
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
                     ` (3 preceding siblings ...)
  2021-11-23 19:13   ` [PATCH v2 4/5] common/cnxk: link REE support to ROC files lironh
@ 2021-11-23 19:13   ` lironh
       [not found]     ` <20211123193835.20601-1-robot@bytheb.org>
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
                     ` (2 subsequent siblings)
  7 siblings, 1 reply; 31+ messages in thread
From: lironh @ 2021-11-23 19:13 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

update driver to use the REE cnxk code.
replace octeontx2/otx2 with cn9k

Signed-off-by: Liron Himi <lironh@marvell.com>
Change-Id: I79c3e1e2850e6274afcf86bb406cd04a2c698402
---
 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 ++++++++----------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 -----
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 --------
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ---------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 --
 18 files changed, 268 insertions(+), 1201 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (68%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..5f45b35c51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst
 RegEx Drivers
 -------------
 
-Marvell OCTEON TX2 regex
+Marvell OCTEON CN9K regex
 M: Liron Himi <lironh@marvell.com>
-F: drivers/regex/octeontx2/
-F: doc/guides/regexdevs/octeontx2.rst
-F: doc/guides/regexdevs/features/octeontx2.ini
+F: drivers/regex/cn9k/
+F: doc/guides/regexdevs/cn9k.rst
+F: doc/guides/regexdevs/features/cn9k.ini
 
 Mellanox mlx5
 M: Ori Kam <orika@nvidia.com>
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 88995cc70c..5213df3ccd 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
 #. **Dmadev Driver**
    See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
 
+#. **Regex Device Driver**
+   See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst
similarity index 68%
rename from doc/guides/regexdevs/octeontx2.rst
rename to doc/guides/regexdevs/cn9k.rst
index b39d457d60..8794a1f115 100644
--- a/doc/guides/regexdevs/octeontx2.rst
+++ b/doc/guides/regexdevs/cn9k.rst
@@ -1,20 +1,20 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
     Copyright(c) 2020 Marvell International Ltd.
 
-OCTEON TX2 REE Regexdev Driver
+CN9K REE Regexdev Driver
 ==============================
 
-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode
-regexdev driver support for the inbuilt regex device found in the **Marvell OCTEON TX2**
+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode
+regexdev driver support for the inbuilt regex device found in the **Marvell CN9K**
 SoC family.
 
-More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+More information about CN9K SoC can be found at `Marvell Official Website
 <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
 
 Features
 --------
 
-Features of the OCTEON TX2 REE PMD are:
+Features of the CN9K REE PMD are:
 
 - 36 queues
 - Up to 254 matches for each regex operation
@@ -22,12 +22,12 @@ Features of the OCTEON TX2 REE PMD are:
 Prerequisites and Compilation procedure
 ---------------------------------------
 
-   See :doc:`../platform/octeontx2` for setup information.
+   See :doc:`../platform/cn9k` for setup information.
 
 Device Setup
 ------------
 
-The OCTEON TX2 REE devices will need to be bound to a user-space IO driver
+The CN9K REE devices will need to be bound to a user-space IO driver
 for use. The script ``dpdk-devbind.py`` script included with DPDK can be
 used to view the state of the devices and to bind them to a suitable
 DPDK-supported kernel driver. When querying the status of the devices,
@@ -38,12 +38,12 @@ those devices alone.
 Debugging Options
 -----------------
 
-.. _table_octeontx2_regex_debug_options:
+.. _table_cn9k_regex_debug_options:
 
-.. table:: OCTEON TX2 regex device debug options
+.. table:: CN9K regex device debug options
 
    +---+------------+-------------------------------------------------------+
    | # | Component  | EAL log command                                       |
    +===+============+=======================================================+
-   | 1 | REE        | --log-level='pmd\.regex\.octeontx2,8'                 |
+   | 1 | REE        | --log-level='pmd\.regex\.cn9k,8'                 |
    +---+------------+-------------------------------------------------------+
diff --git a/doc/guides/regexdevs/features/octeontx2.ini b/doc/guides/regexdevs/features/cn9k.ini
similarity index 80%
rename from doc/guides/regexdevs/features/octeontx2.ini
rename to doc/guides/regexdevs/features/cn9k.ini
index c9b421a16d..b029af8ac2 100644
--- a/doc/guides/regexdevs/features/octeontx2.ini
+++ b/doc/guides/regexdevs/features/cn9k.ini
@@ -1,5 +1,5 @@
 ;
-; Supported features of the 'octeontx2' regex driver.
+; Supported features of the 'cn9k' regex driver.
 ;
 ; Refer to default.ini for the full list of available driver features.
 ;
diff --git a/doc/guides/regexdevs/index.rst b/doc/guides/regexdevs/index.rst
index b1abc826bd..11a33fc09e 100644
--- a/doc/guides/regexdevs/index.rst
+++ b/doc/guides/regexdevs/index.rst
@@ -13,4 +13,4 @@ which can be used from an application through RegEx API.
 
    features_overview
    mlx5
-   octeontx2
+   cn9k
diff --git a/drivers/regex/octeontx2/otx2_regexdev.c b/drivers/regex/cn9k/cn9k_regexdev.c
similarity index 61%
rename from drivers/regex/octeontx2/otx2_regexdev.c
rename to drivers/regex/cn9k/cn9k_regexdev.c
index b6e55853e9..32d20c1be8 100644
--- a/drivers/regex/octeontx2/otx2_regexdev.c
+++ b/drivers/regex/cn9k/cn9k_regexdev.c
@@ -13,12 +13,8 @@
 
 
 /* REE common headers */
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 
 /* HW matches are at offset 0x80 from RES_PTR_ADDR
@@ -35,9 +31,6 @@
 #define REE_MAX_RULES_PER_GROUP 0xFFFF
 #define REE_MAX_GROUPS 0xFFFF
 
-/* This is temporarily here */
-#define REE0_PF	19
-#define REE1_PF	20
 
 #define REE_RULE_DB_VERSION	2
 #define REE_RULE_DB_REVISION	0
@@ -58,32 +51,32 @@ struct ree_rule_db {
 static void
 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
 {
-	snprintf(name, size, "otx2_ree_lf_mem_%u:%u", dev_id, qp_id);
+	snprintf(name, size, "cn9k_ree_lf_mem_%u:%u", dev_id, qp_id);
 }
 
-static struct otx2_ree_qp *
+static struct roc_ree_qp *
 ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
-	struct otx2_ree_vf *vf = &data->vf;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct rte_memzone *lf_mem;
 	uint32_t len, iq_len, size_div2;
 	char name[RTE_MEMZONE_NAMESIZE];
 	uint64_t used_len, iova;
-	struct otx2_ree_qp *qp;
+	struct roc_ree_qp *qp;
 	uint8_t *va;
 	int ret;
 
 	/* Allocate queue pair */
-	qp = rte_zmalloc("OCTEON TX2 Regex PMD Queue Pair", sizeof(*qp),
-				OTX2_ALIGN);
+	qp = rte_zmalloc("CN9K Regex PMD Queue Pair", sizeof(*qp),
+				ROC_ALIGN);
 	if (qp == NULL) {
-		otx2_err("Could not allocate queue pair");
+		cn9k_err("Could not allocate queue pair");
 		return NULL;
 	}
 
-	iq_len = OTX2_REE_IQ_LEN;
+	iq_len = REE_IQ_LEN;
 
 	/*
 	 * Queue size must be in units of 128B 2 * REE_INST_S (which is 64B),
@@ -93,13 +86,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	size_div2 = iq_len >> 1;
 
 	/* For pending queue */
-	len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 
 	/* So that instruction queues start as pg size aligned */
 	len = RTE_ALIGN(len, pg_sz);
 
 	/* For instruction queues */
-	len += OTX2_REE_IQ_LEN * sizeof(union otx2_ree_inst);
+	len += REE_IQ_LEN * sizeof(union roc_ree_inst);
 
 	/* Waste after instruction queues */
 	len = RTE_ALIGN(len, pg_sz);
@@ -107,11 +100,11 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp_id);
 
-	lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
+	lf_mem = rte_memzone_reserve_aligned(name, len, rte_socket_id(),
 			RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
 			RTE_CACHE_LINE_SIZE);
 	if (lf_mem == NULL) {
-		otx2_err("Could not allocate reserved memzone");
+		cn9k_err("Could not allocate reserved memzone");
 		goto qp_free;
 	}
 
@@ -121,24 +114,24 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	memset(va, 0, len);
 
 	/* Initialize pending queue */
-	qp->pend_q.rid_queue = (struct otx2_ree_rid *)va;
+	qp->pend_q.rid_queue = (struct roc_ree_rid *)va;
 	qp->pend_q.enq_tail = 0;
 	qp->pend_q.deq_head = 0;
 	qp->pend_q.pending_count = 0;
 
-	used_len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	used_len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 	used_len = RTE_ALIGN(used_len, pg_sz);
 	iova += used_len;
 
 	qp->iq_dma_addr = iova;
 	qp->id = qp_id;
-	qp->base = OTX2_REE_LF_BAR2(vf, qp_id);
-	qp->otx2_regexdev_jobid = 0;
+	qp->base = roc_ree_qp_get_base(vf, qp_id);
+	qp->roc_regexdev_jobid = 0;
 	qp->write_offset = 0;
 
-	ret = otx2_ree_iq_enable(dev, qp, OTX2_REE_QUEUE_HI_PRIO, size_div2);
+	ret = roc_ree_iq_enable(vf, qp, REE_QUEUE_HI_PRIO, size_div2);
 	if (ret) {
-		otx2_err("Could not enable instruction queue");
+		cn9k_err("Could not enable instruction queue");
 		goto qp_free;
 	}
 
@@ -150,13 +143,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 }
 
 static int
-ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
+ree_qp_destroy(const struct rte_regexdev *dev, struct roc_ree_qp *qp)
 {
 	const struct rte_memzone *lf_mem;
 	char name[RTE_MEMZONE_NAMESIZE];
 	int ret;
 
-	otx2_ree_iq_disable(qp);
+	roc_ree_iq_disable(qp);
 
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp->id);
@@ -175,8 +168,8 @@ ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
 static int
 ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
 	int ret;
 
 	ree_func_trace("Queue=%d", qp_id);
@@ -186,7 +179,7 @@ ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 
 	ret = ree_qp_destroy(dev, qp);
 	if (ret) {
-		otx2_err("Could not destroy queue pair %d", qp_id);
+		cn9k_err("Could not destroy queue pair %d", qp_id);
 		return ret;
 	}
 
@@ -200,12 +193,12 @@ ree_dev_register(const char *name)
 {
 	struct rte_regexdev *dev;
 
-	otx2_ree_dbg("Creating regexdev %s\n", name);
+	cn9k_ree_dbg("Creating regexdev %s\n", name);
 
 	/* allocate device structure */
 	dev = rte_regexdev_register(name);
 	if (dev == NULL) {
-		otx2_err("Failed to allocate regex device for %s", name);
+		cn9k_err("Failed to allocate regex device for %s", name);
 		return NULL;
 	}
 
@@ -213,12 +206,12 @@ ree_dev_register(const char *name)
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		dev->data->dev_private =
 				rte_zmalloc_socket("regexdev device private",
-						sizeof(struct otx2_ree_data),
+						sizeof(struct cn9k_ree_data),
 						RTE_CACHE_LINE_SIZE,
 						rte_socket_id());
 
 		if (dev->data->dev_private == NULL) {
-			otx2_err("Cannot allocate memory for dev %s private data",
+			cn9k_err("Cannot allocate memory for dev %s private data",
 					name);
 
 			rte_regexdev_unregister(dev);
@@ -232,7 +225,7 @@ ree_dev_register(const char *name)
 static int
 ree_dev_unregister(struct rte_regexdev *dev)
 {
-	otx2_ree_dbg("Closing regex device %s", dev->device->name);
+	cn9k_ree_dbg("Closing regex device %s", dev->device->name);
 
 	/* free regex device */
 	rte_regexdev_unregister(dev);
@@ -246,8 +239,8 @@ ree_dev_unregister(struct rte_regexdev *dev)
 static int
 ree_dev_fini(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct rte_pci_device *pci_dev;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	int i, ret;
 
 	ree_func_trace();
@@ -258,9 +251,9 @@ ree_dev_fini(struct rte_regexdev *dev)
 			return ret;
 	}
 
-	ret = otx2_ree_queues_detach(dev);
+	ret = roc_ree_queues_detach(vf);
 	if (ret)
-		otx2_err("Could not detach queues");
+		cn9k_err("Could not detach queues");
 
 	/* TEMP : should be in lib */
 	if (data->queue_pairs)
@@ -268,33 +261,32 @@ ree_dev_fini(struct rte_regexdev *dev)
 	if (data->rules)
 		rte_free(data->rules);
 
-	pci_dev = container_of(dev->device, struct rte_pci_device, device);
-	otx2_dev_fini(pci_dev, &(data->vf.otx2_dev));
+	roc_ree_dev_fini(vf);
 
 	ret = ree_dev_unregister(dev);
 	if (ret)
-		otx2_err("Could not destroy PMD");
+		cn9k_err("Could not destroy PMD");
 
 	return ret;
 }
 
 static inline int
-ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
-		 struct otx2_ree_pending_queue *pend_q)
+ree_enqueue(struct roc_ree_qp *qp, struct rte_regex_ops *op,
+		 struct roc_ree_pending_queue *pend_q)
 {
-	union otx2_ree_inst inst;
-	union otx2_ree_res *res;
+	union roc_ree_inst inst;
+	union ree_res *res;
 	uint32_t offset;
 
-	if (unlikely(pend_q->pending_count >= OTX2_REE_DEFAULT_CMD_QLEN)) {
-		otx2_err("Pending count %" PRIu64 " is greater than Q size %d",
-		pend_q->pending_count, OTX2_REE_DEFAULT_CMD_QLEN);
+	if (unlikely(pend_q->pending_count >= REE_DEFAULT_CMD_QLEN)) {
+		cn9k_err("Pending count %" PRIu64 " is greater than Q size %d",
+		pend_q->pending_count, REE_DEFAULT_CMD_QLEN);
 		return -EAGAIN;
 	}
-	if (unlikely(op->mbuf->data_len > OTX2_REE_MAX_PAYLOAD_SIZE ||
+	if (unlikely(op->mbuf->data_len > REE_MAX_PAYLOAD_SIZE ||
 			op->mbuf->data_len == 0)) {
-		otx2_err("Packet length %d is greater than MAX payload %d",
-				op->mbuf->data_len, OTX2_REE_MAX_PAYLOAD_SIZE);
+		cn9k_err("Packet length %d is greater than MAX payload %d",
+				op->mbuf->data_len, REE_MAX_PAYLOAD_SIZE);
 		return -EAGAIN;
 	}
 
@@ -324,7 +316,7 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 		inst.cn98xx.ree_job_ctrl = (0x1 << 8);
 	else
 		inst.cn98xx.ree_job_ctrl = 0;
-	inst.cn98xx.ree_job_id = qp->otx2_regexdev_jobid;
+	inst.cn98xx.ree_job_id = qp->roc_regexdev_jobid;
 	/* W 7 */
 	inst.cn98xx.ree_job_subset_id_0 = op->group_id0;
 	if (op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F)
@@ -348,33 +340,33 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 	pend_q->rid_queue[pend_q->enq_tail].user_id = op->user_id;
 
 	/* Mark result as not done */
-	res = (union otx2_ree_res *)(op);
+	res = (union ree_res *)(op);
 	res->s.done = 0;
 	res->s.ree_err = 0;
 
 	/* We will use soft queue length here to limit requests */
-	REE_MOD_INC(pend_q->enq_tail, OTX2_REE_DEFAULT_CMD_QLEN);
+	REE_MOD_INC(pend_q->enq_tail, REE_DEFAULT_CMD_QLEN);
 	pend_q->pending_count += 1;
-	REE_MOD_INC(qp->otx2_regexdev_jobid, 0xFFFFFF);
-	REE_MOD_INC(qp->write_offset, OTX2_REE_IQ_LEN);
+	REE_MOD_INC(qp->roc_regexdev_jobid, 0xFFFFFF);
+	REE_MOD_INC(qp->write_offset, REE_IQ_LEN);
 
 	return 0;
 }
 
 static uint16_t
-otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	uint16_t nb_allowed, count = 0;
 	struct rte_regex_ops *op;
 	int ret;
 
 	pend_q = &qp->pend_q;
 
-	nb_allowed = OTX2_REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
+	nb_allowed = REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
 	if (nb_ops > nb_allowed)
 		nb_ops = nb_allowed;
 
@@ -392,7 +384,7 @@ otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 	rte_io_wmb();
 
 	/* Update Doorbell */
-	otx2_write64(count, qp->base + OTX2_REE_LF_DOORBELL);
+	plt_write64(count, qp->base + REE_LF_DOORBELL);
 
 	return count;
 }
@@ -422,15 +414,15 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 	}
 
 	if (unlikely(ree_res_status != REE_TYPE_RESULT_DESC)) {
-		if (ree_res_status & OTX2_REE_STATUS_PMI_SOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_SOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_PMI_EOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_EOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_ML_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_ML_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F;
-		if (ree_res_status & OTX2_REE_STATUS_MM_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MM_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F;
-		if (ree_res_status & OTX2_REE_STATUS_MP_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MP_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F;
 	}
 	if (ops->nb_matches > 0) {
@@ -439,22 +431,22 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 			ops->nb_matches : REE_NUM_MATCHES_ALIGN);
 		match = (uint64_t)ops + REE_MATCH_OFFSET;
 		match += (ops->nb_matches - off) *
-			sizeof(union otx2_ree_match);
+			sizeof(union ree_match);
 		memcpy((void *)ops->matches, (void *)match,
-			off * sizeof(union otx2_ree_match));
+			off * sizeof(union ree_match));
 	}
 }
 
 static uint16_t
-otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	int i, nb_pending, nb_completed = 0;
 	volatile struct ree_res_s_98 *res;
-	struct otx2_ree_rid *rid;
+	struct roc_ree_rid *rid;
 
 	pend_q = &qp->pend_q;
 
@@ -474,7 +466,7 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		ops[i] = (struct rte_regex_ops *)(rid->rid);
 		ops[i]->user_id = rid->user_id;
 
-		REE_MOD_INC(pend_q->deq_head, OTX2_REE_DEFAULT_CMD_QLEN);
+		REE_MOD_INC(pend_q->deq_head, REE_DEFAULT_CMD_QLEN);
 		pend_q->pending_count -= 1;
 	}
 
@@ -487,10 +479,10 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 }
 
 static int
-otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
+cn9k_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 
 	ree_func_trace();
 
@@ -502,7 +494,7 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 
 	info->max_queue_pairs = vf->max_queues;
 	info->max_matches = vf->max_matches;
-	info->max_payload_size = OTX2_REE_MAX_PAYLOAD_SIZE;
+	info->max_payload_size = REE_MAX_PAYLOAD_SIZE;
 	info->max_rules_per_group = data->max_rules_per_group;
 	info->max_groups = data->max_groups;
 	info->regexdev_capa = data->regexdev_capa;
@@ -512,11 +504,11 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 }
 
 static int
-otx2_ree_dev_config(struct rte_regexdev *dev,
+cn9k_ree_dev_config(struct rte_regexdev *dev,
 		    const struct rte_regexdev_config *cfg)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *rule_db;
 	uint32_t rule_db_len;
 	int ret;
@@ -524,29 +516,29 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	ree_func_trace();
 
 	if (cfg->nb_queue_pairs > vf->max_queues) {
-		otx2_err("Invalid number of queue pairs requested");
+		cn9k_err("Invalid number of queue pairs requested");
 		return -EINVAL;
 	}
 
 	if (cfg->nb_max_matches != vf->max_matches) {
-		otx2_err("Invalid number of max matches requested");
+		cn9k_err("Invalid number of max matches requested");
 		return -EINVAL;
 	}
 
 	if (cfg->dev_cfg_flags != 0) {
-		otx2_err("Invalid device configuration flags requested");
+		cn9k_err("Invalid device configuration flags requested");
 		return -EINVAL;
 	}
 
 	/* Unregister error interrupts */
 	if (vf->err_intr_registered)
-		otx2_ree_err_intr_unregister(dev);
+		roc_ree_err_intr_unregister(vf);
 
 	/* Detach queues */
 	if (vf->nb_queues) {
-		ret = otx2_ree_queues_detach(dev);
+		ret = roc_ree_queues_detach(vf);
 		if (ret) {
-			otx2_err("Could not detach REE queues");
+			cn9k_err("Could not detach REE queues");
 			return ret;
 		}
 	}
@@ -559,7 +551,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 
 		if (data->queue_pairs == NULL) {
 			data->nb_queue_pairs = 0;
-			otx2_err("Failed to get memory for qp meta data, nb_queues %u",
+			cn9k_err("Failed to get memory for qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -579,7 +571,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 		qp = rte_realloc(qp, sizeof(qp[0]) * cfg->nb_queue_pairs,
 				RTE_CACHE_LINE_SIZE);
 		if (qp == NULL) {
-			otx2_err("Failed to realloc qp meta data, nb_queues %u",
+			cn9k_err("Failed to realloc qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -594,52 +586,52 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	data->nb_queue_pairs = cfg->nb_queue_pairs;
 
 	/* Attach queues */
-	otx2_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
-	ret = otx2_ree_queues_attach(dev, cfg->nb_queue_pairs);
+	cn9k_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
+	ret = roc_ree_queues_attach(vf, cfg->nb_queue_pairs);
 	if (ret) {
-		otx2_err("Could not attach queues");
+		cn9k_err("Could not attach queues");
 		return -ENODEV;
 	}
 
-	ret = otx2_ree_msix_offsets_get(dev);
+	ret = roc_ree_msix_offsets_get(vf);
 	if (ret) {
-		otx2_err("Could not get MSI-X offsets");
+		cn9k_err("Could not get MSI-X offsets");
 		goto queues_detach;
 	}
 
 	if (cfg->rule_db && cfg->rule_db_len) {
-		otx2_ree_dbg("rule_db length %d", cfg->rule_db_len);
+		cn9k_ree_dbg("rule_db length %d", cfg->rule_db_len);
 		rule_db = (const struct ree_rule_db *)cfg->rule_db;
 		rule_db_len = rule_db->number_of_entries *
 				sizeof(struct ree_rule_db_entry);
-		otx2_ree_dbg("rule_db number of entries %d",
+		cn9k_ree_dbg("rule_db number of entries %d",
 				rule_db->number_of_entries);
 		if (rule_db_len > cfg->rule_db_len) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			ret = -EINVAL;
 			goto queues_detach;
 		}
-		ret = otx2_ree_rule_db_prog(dev, (const char *)rule_db->entries,
-				rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+		ret = roc_ree_rule_db_prog(vf, (const char *)rule_db->entries,
+				rule_db_len, NULL, REE_NON_INC_PROG);
 		if (ret) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			goto queues_detach;
 		}
 	}
 
-	dev->enqueue = otx2_ree_enqueue_burst;
-	dev->dequeue = otx2_ree_dequeue_burst;
+	dev->enqueue = cn9k_ree_enqueue_burst;
+	dev->dequeue = cn9k_ree_dequeue_burst;
 
 	rte_mb();
 	return 0;
 
 queues_detach:
-	otx2_ree_queues_detach(dev);
+	roc_ree_queues_detach(vf);
 	return ret;
 }
 
 static int
-otx2_ree_stop(struct rte_regexdev *dev)
+cn9k_ree_stop(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 
@@ -648,18 +640,20 @@ otx2_ree_stop(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_start(struct rte_regexdev *dev)
+cn9k_ree_start(struct rte_regexdev *dev)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	uint32_t rule_db_len = 0;
 	int ret;
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, NULL);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, NULL);
 	if (ret)
 		return ret;
 	if (rule_db_len == 0) {
-		otx2_err("Rule db not programmed");
+		cn9k_err("Rule db not programmed");
 		return -EFAULT;
 	}
 
@@ -667,56 +661,55 @@ otx2_ree_start(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_close(struct rte_regexdev *dev)
+cn9k_ree_close(struct rte_regexdev *dev)
 {
 	return ree_dev_fini(dev);
 }
 
 static int
-otx2_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
 		const struct rte_regexdev_qp_conf *qp_conf)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp;
 
 	ree_func_trace("Queue=%d", qp_id);
 
 	if (data->queue_pairs[qp_id] != NULL)
 		ree_queue_pair_release(dev, qp_id);
 
-	if (qp_conf->nb_desc > OTX2_REE_DEFAULT_CMD_QLEN) {
-		otx2_err("Could not setup queue pair for %u descriptors",
+	if (qp_conf->nb_desc > REE_DEFAULT_CMD_QLEN) {
+		cn9k_err("Could not setup queue pair for %u descriptors",
 				qp_conf->nb_desc);
 		return -EINVAL;
 	}
 	if (qp_conf->qp_conf_flags != 0) {
-		otx2_err("Could not setup queue pair with configuration flags 0x%x",
+		cn9k_err("Could not setup queue pair with configuration flags 0x%x",
 				qp_conf->qp_conf_flags);
 		return -EINVAL;
 	}
 
 	qp = ree_qp_create(dev, qp_id);
 	if (qp == NULL) {
-		otx2_err("Could not create queue pair %d", qp_id);
+		cn9k_err("Could not create queue pair %d", qp_id);
 		return -ENOMEM;
 	}
-	qp->cb = qp_conf->cb;
 	data->queue_pairs[qp_id] = qp;
 
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_compile_activate(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_activate(struct rte_regexdev *dev)
 {
-	return otx2_ree_rule_db_compile_prog(dev);
+	return cn9k_ree_rule_db_compile_prog(dev);
 }
 
 static int
-otx2_ree_rule_db_update(struct rte_regexdev *dev,
+cn9k_ree_rule_db_update(struct rte_regexdev *dev,
 		const struct rte_regexdev_rule *rules, uint16_t nb_rules)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	struct rte_regexdev_rule *old_ptr;
 	uint32_t i, sum_nb_rules;
 
@@ -770,10 +763,11 @@ otx2_ree_rule_db_update(struct rte_regexdev *dev,
 }
 
 static int
-otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
+cn9k_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 		uint32_t rule_db_len)
 {
-
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *ree_rule_db;
 	uint32_t ree_rule_db_len;
 	int ret;
@@ -784,21 +778,23 @@ otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 	ree_rule_db_len = ree_rule_db->number_of_entries *
 			sizeof(struct ree_rule_db_entry);
 	if (ree_rule_db_len > rule_db_len) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -EINVAL;
 	}
-	ret = otx2_ree_rule_db_prog(dev, (const char *)ree_rule_db->entries,
-			ree_rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+	ret = roc_ree_rule_db_prog(vf, (const char *)ree_rule_db->entries,
+			ree_rule_db_len, NULL, REE_NON_INC_PROG);
 	if (ret) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -ENOSPC;
 	}
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
+cn9k_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	struct ree_rule_db *ree_rule_db;
 	uint32_t rule_dbi_len;
 	uint32_t rule_db_len;
@@ -806,7 +802,7 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret)
 		return ret;
 
@@ -816,10 +812,10 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	}
 
 	ree_rule_db = (struct ree_rule_db *)rule_db;
-	ret = otx2_ree_rule_db_get(dev, (char *)ree_rule_db->entries,
+	ret = roc_ree_rule_db_get(vf, (char *)ree_rule_db->entries,
 			rule_db_len, NULL, 0);
 	if (ret) {
-		otx2_err("Could not export rule db");
+		cn9k_err("Could not export rule db");
 		return -EFAULT;
 	}
 	ree_rule_db->number_of_entries =
@@ -830,55 +826,44 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	return 0;
 }
 
-static int
-ree_get_blkaddr(struct otx2_dev *dev)
-{
-	int pf;
-
-	pf = otx2_get_pf(dev->pf_func);
-	if (pf == REE0_PF)
-		return RVU_BLOCK_ADDR_REE0;
-	else if (pf == REE1_PF)
-		return RVU_BLOCK_ADDR_REE1;
-	else
-		return 0;
-}
-
-static struct rte_regexdev_ops otx2_ree_ops = {
-		.dev_info_get = otx2_ree_dev_info_get,
-		.dev_configure = otx2_ree_dev_config,
-		.dev_qp_setup = otx2_ree_queue_pair_setup,
-		.dev_start = otx2_ree_start,
-		.dev_stop = otx2_ree_stop,
-		.dev_close = otx2_ree_close,
-		.dev_attr_get = NULL,
-		.dev_attr_set = NULL,
-		.dev_rule_db_update = otx2_ree_rule_db_update,
-		.dev_rule_db_compile_activate =
-				otx2_ree_rule_db_compile_activate,
-		.dev_db_import = otx2_ree_rule_db_import,
-		.dev_db_export = otx2_ree_rule_db_export,
-		.dev_xstats_names_get = NULL,
-		.dev_xstats_get = NULL,
-		.dev_xstats_by_name_get = NULL,
-		.dev_xstats_reset = NULL,
-		.dev_selftest = NULL,
-		.dev_dump = NULL,
+static struct rte_regexdev_ops cn9k_ree_ops = {
+	.dev_info_get = cn9k_ree_dev_info_get,
+	.dev_configure = cn9k_ree_dev_config,
+	.dev_qp_setup = cn9k_ree_queue_pair_setup,
+	.dev_start = cn9k_ree_start,
+	.dev_stop = cn9k_ree_stop,
+	.dev_close = cn9k_ree_close,
+	.dev_attr_get = NULL,
+	.dev_attr_set = NULL,
+	.dev_rule_db_update = cn9k_ree_rule_db_update,
+	.dev_rule_db_compile_activate =
+			cn9k_ree_rule_db_compile_activate,
+	.dev_db_import = cn9k_ree_rule_db_import,
+	.dev_db_export = cn9k_ree_rule_db_export,
+	.dev_xstats_names_get = NULL,
+	.dev_xstats_get = NULL,
+	.dev_xstats_by_name_get = NULL,
+	.dev_xstats_reset = NULL,
+	.dev_selftest = NULL,
+	.dev_dump = NULL,
 };
 
 static int
-otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+cn9k_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		   struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
-	struct otx2_ree_data *data;
-	struct otx2_dev *otx2_dev;
+	struct cn9k_ree_data *data;
 	struct rte_regexdev *dev;
-	uint8_t max_matches = 0;
-	struct otx2_ree_vf *vf;
-	uint16_t nb_queues = 0;
+	struct roc_ree_vf *vf;
 	int ret;
 
+	ret = roc_plt_init();
+	if (ret < 0) {
+		plt_err("Failed to initialize platform model");
+		return ret;
+	}
+
 	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
 
 	dev = ree_dev_register(name);
@@ -887,63 +872,19 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		goto exit;
 	}
 
-	dev->dev_ops = &otx2_ree_ops;
+	dev->dev_ops = &cn9k_ree_ops;
 	dev->device = &pci_dev->device;
 
 	/* Get private data space allocated */
 	data = dev->data->dev_private;
 	vf = &data->vf;
-
-	otx2_dev = &vf->otx2_dev;
-
-	/* Initialize the base otx2_dev object */
-	ret = otx2_dev_init(pci_dev, otx2_dev);
+	vf->pci_dev = pci_dev;
+	ret = roc_ree_dev_init(vf);
 	if (ret) {
-		otx2_err("Could not initialize otx2_dev");
+		plt_err("Failed to initialize roc cpt rc=%d", ret);
 		goto dev_unregister;
 	}
-	/* Get REE block address */
-	vf->block_address = ree_get_blkaddr(otx2_dev);
-	if (!vf->block_address) {
-		otx2_err("Could not determine block PF number");
-		goto otx2_dev_fini;
-	}
-
-	/* Get number of queues available on the device */
-	ret = otx2_ree_available_queues_get(dev, &nb_queues);
-	if (ret) {
-		otx2_err("Could not determine the number of queues available");
-		goto otx2_dev_fini;
-	}
-
-	/* Don't exceed the limits set per VF */
-	nb_queues = RTE_MIN(nb_queues, OTX2_REE_MAX_QUEUES_PER_VF);
-
-	if (nb_queues == 0) {
-		otx2_err("No free queues available on the device");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_queues = nb_queues;
-
-	otx2_ree_dbg("Max queues supported by device: %d", vf->max_queues);
-
-	/* Get number of maximum matches supported on the device */
-	ret = otx2_ree_max_matches_get(dev, &max_matches);
-	if (ret) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-	/* Don't exceed the limits set per VF */
-	max_matches = RTE_MIN(max_matches, OTX2_REE_MAX_MATCHES_PER_VF);
-	if (max_matches == 0) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_matches = max_matches;
 
-	otx2_ree_dbg("Max matches supported by device: %d", vf->max_matches);
 	data->rule_flags = RTE_REGEX_PCRE_RULE_ALLOW_EMPTY_F |
 			RTE_REGEX_PCRE_RULE_ANCHORED_F;
 	data->regexdev_capa = 0;
@@ -954,18 +895,16 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	dev->state = RTE_REGEXDEV_READY;
 	return 0;
 
-otx2_dev_fini:
-	otx2_dev_fini(pci_dev, otx2_dev);
 dev_unregister:
 	ree_dev_unregister(dev);
 exit:
-	otx2_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
+	cn9k_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
 		    pci_dev->id.vendor_id, pci_dev->id.device_id);
 	return ret;
 }
 
 static int
-otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
+cn9k_ree_pci_remove(struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
 	struct rte_regexdev *dev = NULL;
@@ -986,20 +925,20 @@ otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
 static struct rte_pci_id pci_id_ree_table[] = {
 	{
 		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-				PCI_DEVID_OCTEONTX2_RVU_REE_PF)
+				PCI_DEVID_CNXK_RVU_REE_PF)
 	},
 	{
 		.vendor_id = 0,
 	}
 };
 
-static struct rte_pci_driver otx2_regexdev_pmd = {
+static struct rte_pci_driver cn9k_regexdev_pmd = {
 	.id_table = pci_id_ree_table,
 	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
-	.probe = otx2_ree_pci_probe,
-	.remove = otx2_ree_pci_remove,
+	.probe = cn9k_ree_pci_probe,
+	.remove = cn9k_ree_pci_remove,
 };
 
 
-RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_OCTEONTX2_PMD, otx2_regexdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_OCTEONTX2_PMD, pci_id_ree_table);
+RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_CN9K_PMD, cn9k_regexdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_CN9K_PMD, pci_id_ree_table);
diff --git a/drivers/regex/cn9k/cn9k_regexdev.h b/drivers/regex/cn9k/cn9k_regexdev.h
new file mode 100644
index 0000000000..c715502167
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_H_
+#define _CN9K_REGEXDEV_H_
+
+#include <rte_common.h>
+#include <rte_regexdev.h>
+
+#include "roc_api.h"
+
+#define cn9k_ree_dbg plt_ree_dbg
+#define cn9k_err plt_err
+
+#define ree_func_trace cn9k_ree_dbg
+
+/* Marvell CN9K Regex PMD device name */
+#define REGEXDEV_NAME_CN9K_PMD	regex_cn9k
+
+/**
+ * Device private data
+ */
+struct cn9k_ree_data {
+	uint32_t regexdev_capa;
+	uint64_t rule_flags;
+	/**< Feature flags exposes HW/SW features for the given device */
+	uint16_t max_rules_per_group;
+	/**< Maximum rules supported per subset by this device */
+	uint16_t max_groups;
+	/**< Maximum subset supported by this device */
+	void **queue_pairs;
+	/**< Array of pointers to queue pairs. */
+	uint16_t nb_queue_pairs;
+	/**< Number of device queue pairs. */
+	struct roc_ree_vf vf;
+	/**< vf data */
+	struct rte_regexdev_rule *rules;
+	/**< rules to be compiled */
+	uint16_t nb_rules;
+	/**< number of rules */
+} __rte_cache_aligned;
+
+#endif /* _CN9K_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.c b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
similarity index 86%
rename from drivers/regex/octeontx2/otx2_regexdev_compiler.c
rename to drivers/regex/cn9k/cn9k_regexdev_compiler.c
index 785459f741..935b8a53b4 100644
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.c
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
@@ -5,9 +5,8 @@
 #include <rte_malloc.h>
 #include <rte_regexdev.h>
 
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 #ifdef REE_COMPILER_SDK
 #include <rxp-compiler.h>
@@ -65,7 +64,7 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 			nb_rules*sizeof(struct rxp_rule_entry), 0);
 
 	if (ruleset.rules == NULL) {
-		otx2_err("Could not allocate memory for rule compilation\n");
+		cn9k_err("Could not allocate memory for rule compilation\n");
 		return -EFAULT;
 	}
 	if (rof_for_incremental_compile)
@@ -126,9 +125,10 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 }
 
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	char compiler_version[] = "20.5.2.eda0fa2";
 	char timestamp[] = "19700101_000001";
 	uint32_t rule_db_len, rule_dbi_len;
@@ -144,25 +144,25 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret != 0) {
-		otx2_err("Could not get rule db length");
+		cn9k_err("Could not get rule db length");
 		return ret;
 	}
 
 	if (rule_db_len > 0) {
-		otx2_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
+		cn9k_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
 				rule_db_len, rule_dbi_len);
 		rule_db = rte_malloc("ree_rule_db", rule_db_len, 0);
 		if (!rule_db) {
-			otx2_err("Could not allocate memory for rule db");
+			cn9k_err("Could not allocate memory for rule db");
 			return -EFAULT;
 		}
 
-		ret = otx2_ree_rule_db_get(dev, rule_db, rule_db_len,
+		ret = roc_ree_rule_db_get(vf, rule_db, rule_db_len,
 				(char *)rule_dbi, rule_dbi_len);
 		if (ret) {
-			otx2_err("Could not read rule db");
+			cn9k_err("Could not read rule db");
 			rte_free(rule_db);
 			return -EFAULT;
 		}
@@ -188,7 +188,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 		ret = ree_rule_db_compile(data->rules, data->nb_rules, &rof,
 				&rofi, &rof_inc, rofi_inc_p);
 		if (rofi->number_of_entries == 0) {
-			otx2_ree_dbg("No change to rule db");
+			cn9k_ree_dbg("No change to rule db");
 			ret = 0;
 			goto free_structs;
 		}
@@ -201,14 +201,14 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 				&rofi, NULL, NULL);
 	}
 	if (ret != 0) {
-		otx2_err("Could not compile rule db");
+		cn9k_err("Could not compile rule db");
 		goto free_structs;
 	}
 	rule_db_len = rof->number_of_entries * sizeof(struct rxp_rof_entry);
-	ret = otx2_ree_rule_db_prog(dev, (char *)rof->rof_entries, rule_db_len,
+	ret = roc_ree_rule_db_prog(vf, (char *)rof->rof_entries, rule_db_len,
 			rofi_rof_entries, rule_dbi_len);
 	if (ret)
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 
 free_structs:
 	rxp_free_structs(NULL, NULL, NULL, NULL, NULL, &rof, NULL, &rofi, NULL,
@@ -221,7 +221,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 }
 #else
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 	return -ENOTSUP;
diff --git a/drivers/regex/cn9k/cn9k_regexdev_compiler.h b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
new file mode 100644
index 0000000000..4c29a69ada
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_COMPILER_H_
+#define _CN9K_REGEXDEV_COMPILER_H_
+
+int
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev);
+
+#endif /* _CN9K_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/meson.build b/drivers/regex/cn9k/meson.build
similarity index 65%
rename from drivers/regex/octeontx2/meson.build
rename to drivers/regex/cn9k/meson.build
index 3f81add5bf..bb0504fba1 100644
--- a/drivers/regex/octeontx2/meson.build
+++ b/drivers/regex/cn9k/meson.build
@@ -16,12 +16,10 @@ if lib.found()
 endif
 
 sources = files(
-        'otx2_regexdev.c',
-        'otx2_regexdev_compiler.c',
-        'otx2_regexdev_hw_access.c',
-        'otx2_regexdev_mbox.c',
+        'cn9k_regexdev.c',
+        'cn9k_regexdev_compiler.c',
 )
 
-deps += ['bus_pci', 'common_octeontx2', 'regexdev']
+deps += ['bus_pci', 'regexdev']
+deps += ['common_cnxk', 'mempool_cnxk']
 
-includes += include_directories('../../common/octeontx2')
diff --git a/drivers/regex/octeontx2/version.map b/drivers/regex/cn9k/version.map
similarity index 100%
rename from drivers/regex/octeontx2/version.map
rename to drivers/regex/cn9k/version.map
diff --git a/drivers/regex/meson.build b/drivers/regex/meson.build
index 94222e55fe..7ad55af8ca 100644
--- a/drivers/regex/meson.build
+++ b/drivers/regex/meson.build
@@ -3,6 +3,6 @@
 
 drivers = [
         'mlx5',
-        'octeontx2',
+        'cn9k',
 ]
 std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc
diff --git a/drivers/regex/octeontx2/otx2_regexdev.h b/drivers/regex/octeontx2/otx2_regexdev.h
deleted file mode 100644
index d710535f5f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_H_
-#define _OTX2_REGEXDEV_H_
-
-#include <rte_common.h>
-#include <rte_regexdev.h>
-
-#include "otx2_dev.h"
-
-#define ree_func_trace otx2_ree_dbg
-
-/* Marvell OCTEON TX2 Regex PMD device name */
-#define REGEXDEV_NAME_OCTEONTX2_PMD	regex_octeontx2
-
-#define OTX2_REE_MAX_LFS		36
-#define OTX2_REE_MAX_QUEUES_PER_VF	36
-#define OTX2_REE_MAX_MATCHES_PER_VF	254
-
-#define OTX2_REE_MAX_PAYLOAD_SIZE	(1 << 14)
-
-#define OTX2_REE_NON_INC_PROG 0
-#define OTX2_REE_INC_PROG 1
-
-#define REE_MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
-
-
-/**
- * Device vf data
- */
-struct otx2_ree_vf {
-	struct otx2_dev otx2_dev;
-	/**< Base class */
-	uint16_t max_queues;
-	/**< Max queues supported */
-	uint8_t nb_queues;
-	/**< Number of regex queues attached */
-	uint16_t max_matches;
-	/**<  Max matches supported*/
-	uint16_t lf_msixoff[OTX2_REE_MAX_LFS];
-	/**< MSI-X offsets */
-	uint8_t block_address;
-	/**< REE Block Address */
-	uint8_t err_intr_registered:1;
-	/**< Are error interrupts registered? */
-};
-
-/**
- * Device private data
- */
-struct otx2_ree_data {
-	uint32_t regexdev_capa;
-	uint64_t rule_flags;
-	/**< Feature flags exposes HW/SW features for the given device */
-	uint16_t max_rules_per_group;
-	/**< Maximum rules supported per subset by this device */
-	uint16_t max_groups;
-	/**< Maximum subset supported by this device */
-	void **queue_pairs;
-	/**< Array of pointers to queue pairs. */
-	uint16_t nb_queue_pairs;
-	/**< Number of device queue pairs. */
-	struct otx2_ree_vf vf;
-	/**< vf data */
-	struct rte_regexdev_rule *rules;
-	/**< rules to be compiled */
-	uint16_t nb_rules;
-	/**< number of rules */
-} __rte_cache_aligned;
-
-struct otx2_ree_rid {
-	uintptr_t rid;
-	/** Request id of a ree operation */
-	uint64_t user_id;
-	/* Client data */
-	/**< IOVA address of the pattern to be matched. */
-};
-
-struct otx2_ree_pending_queue {
-	uint64_t pending_count;
-	/** Pending requests count */
-	struct otx2_ree_rid *rid_queue;
-	/** Array of pending requests */
-	uint16_t enq_tail;
-	/** Tail of queue to be used for enqueue */
-	uint16_t deq_head;
-	/** Head of queue to be used for dequeue */
-};
-
-struct otx2_ree_qp {
-	uint32_t id;
-	/**< Queue pair id */
-	uintptr_t base;
-	/**< Base address where BAR is mapped */
-	struct otx2_ree_pending_queue pend_q;
-	/**< Pending queue */
-	rte_iova_t iq_dma_addr;
-	/**< Instruction queue address */
-	uint32_t otx2_regexdev_jobid;
-	/**< Job ID */
-	uint32_t write_offset;
-	/**< write offset */
-	regexdev_stop_flush_t cb;
-	/**< Callback function called during rte_regex_dev_stop()*/
-};
-
-#endif /* _OTX2_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.h b/drivers/regex/octeontx2/otx2_regexdev_compiler.h
deleted file mode 100644
index 8d2625bf7f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_COMPILER_H_
-#define _OTX2_REGEXDEV_COMPILER_H_
-
-int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev);
-
-#endif /* _OTX2_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c b/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
deleted file mode 100644
index f8031d0f72..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
-
-static void
-ree_lf_err_intr_handler(void *param)
-{
-	uintptr_t base = (uintptr_t)param;
-	uint8_t lf_id;
-	uint64_t intr;
-
-	lf_id = (base >> 12) & 0xFF;
-
-	intr = otx2_read64(base + OTX2_REE_LF_MISC_INT);
-	if (intr == 0)
-		return;
-
-	otx2_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
-
-	/* Clear interrupt */
-	otx2_write64(intr, base + OTX2_REE_LF_MISC_INT);
-}
-
-static void
-ree_lf_err_intr_unregister(const struct rte_regexdev *dev, uint16_t msix_off,
-			   uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	otx2_unregister_irq(handle, ree_lf_err_intr_handler, (void *)base,
-			    msix_off);
-}
-
-void
-otx2_ree_err_intr_unregister(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uintptr_t base;
-	uint32_t i;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
-	}
-
-	vf->err_intr_registered = 0;
-}
-
-static int
-ree_lf_err_intr_register(const struct rte_regexdev *dev, uint16_t msix_off,
-			 uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-	int ret;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	/* Register error interrupt handler */
-	ret = otx2_register_irq(handle, ree_lf_err_intr_handler, (void *)base,
-				msix_off);
-	if (ret)
-		return ret;
-
-	/* Enable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1S);
-
-	return 0;
-}
-
-int
-otx2_ree_err_intr_register(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uint32_t i, j, ret;
-	uintptr_t base;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
-			otx2_err("Invalid REE LF MSI-X offset: 0x%x",
-				    vf->lf_msixoff[i]);
-			return -EINVAL;
-		}
-	}
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ret = ree_lf_err_intr_register(dev, vf->lf_msixoff[i], base);
-		if (ret)
-			goto intr_unregister;
-	}
-
-	vf->err_intr_registered = 1;
-	return 0;
-
-intr_unregister:
-	/* Unregister the ones already registered */
-	for (j = 0; j < i; j++) {
-		base = OTX2_REE_LF_BAR2(vf, j);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
-	}
-	return ret;
-}
-
-int
-otx2_ree_iq_enable(const struct rte_regexdev *dev, const struct otx2_ree_qp *qp,
-		   uint8_t pri, uint32_t size_div2)
-{
-	union otx2_ree_lf_sbuf_addr base;
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Set instruction queue size and priority */
-	otx2_ree_config_lf(dev, qp->id, pri, size_div2);
-
-	/* Set instruction queue base address */
-	/* Should be written after SBUF_CTL and before LF_ENA */
-
-	base.u = otx2_read64(qp->base + OTX2_REE_LF_SBUF_ADDR);
-	base.s.ptr = qp->iq_dma_addr >> 7;
-	otx2_write64(base.u, qp->base + OTX2_REE_LF_SBUF_ADDR);
-
-	/* Enable instruction queue */
-
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 1;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-
-	return 0;
-}
-
-void
-otx2_ree_iq_disable(struct otx2_ree_qp *qp)
-{
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Stop instruction execution */
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 0x0;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-}
-
-int
-otx2_ree_max_matches_get(const struct rte_regexdev *dev, uint8_t *max_matches)
-{
-	union otx2_ree_af_reexm_max_match reexm_max_match;
-	int ret;
-
-	ret = otx2_ree_af_reg_read(dev, REE_AF_REEXM_MAX_MATCH,
-				   &reexm_max_match.u);
-	if (ret)
-		return ret;
-
-	*max_matches = reexm_max_match.s.max;
-	return 0;
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h b/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
deleted file mode 100644
index dedf5f3282..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_HW_ACCESS_H_
-#define _OTX2_REGEXDEV_HW_ACCESS_H_
-
-#include <stdint.h>
-
-#include "otx2_regexdev.h"
-
-/* REE instruction queue length */
-#define OTX2_REE_IQ_LEN			(1 << 13)
-
-#define OTX2_REE_DEFAULT_CMD_QLEN	OTX2_REE_IQ_LEN
-
-/* Status register bits */
-#define OTX2_REE_STATUS_PMI_EOJ_BIT		(1 << 14)
-#define OTX2_REE_STATUS_PMI_SOJ_BIT		(1 << 13)
-#define OTX2_REE_STATUS_MP_CNT_DET_BIT		(1 << 7)
-#define OTX2_REE_STATUS_MM_CNT_DET_BIT		(1 << 6)
-#define OTX2_REE_STATUS_ML_CNT_DET_BIT		(1 << 5)
-#define OTX2_REE_STATUS_MST_CNT_DET_BIT		(1 << 4)
-#define OTX2_REE_STATUS_MPT_CNT_DET_BIT		(1 << 3)
-
-/* Register offsets */
-/* REE LF registers */
-#define OTX2_REE_LF_DONE_INT		0x120ull
-#define OTX2_REE_LF_DONE_INT_W1S	0x130ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1S	0x138ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1C	0x140ull
-#define OTX2_REE_LF_MISC_INT		0x300ull
-#define OTX2_REE_LF_MISC_INT_W1S	0x310ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1S	0x320ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1C	0x330ull
-#define OTX2_REE_LF_ENA			0x10ull
-#define OTX2_REE_LF_SBUF_ADDR		0x20ull
-#define OTX2_REE_LF_DONE		0x100ull
-#define OTX2_REE_LF_DONE_ACK		0x110ull
-#define OTX2_REE_LF_DONE_WAIT		0x148ull
-#define OTX2_REE_LF_DOORBELL		0x400ull
-#define OTX2_REE_LF_OUTSTAND_JOB	0x410ull
-
-/* BAR 0 */
-#define OTX2_REE_AF_QUE_SBUF_CTL(a)	(0x1200ull | (uint64_t)(a) << 3)
-#define OTX2_REE_PRIV_LF_CFG(a)		(0x41000ull | (uint64_t)(a) << 3)
-
-#define OTX2_REE_LF_BAR2(vf, q_id) \
-		((vf)->otx2_dev.bar2 + \
-		 (((vf)->block_address << 20) | ((q_id) << 12)))
-
-
-#define OTX2_REE_QUEUE_HI_PRIO 0x1
-
-enum ree_desc_type_e {
-	REE_TYPE_JOB_DESC    = 0x0,
-	REE_TYPE_RESULT_DESC = 0x1,
-	REE_TYPE_ENUM_LAST   = 0x2
-};
-
-union otx2_ree_priv_lf_cfg {
-	uint64_t u;
-	struct {
-		uint64_t slot                        : 8;
-		uint64_t pf_func                     : 16;
-		uint64_t reserved_24_62              : 39;
-		uint64_t ena                         : 1;
-	} s;
-};
-
-
-union otx2_ree_lf_sbuf_addr {
-	uint64_t u;
-	struct {
-		uint64_t off                         : 7;
-		uint64_t ptr                         : 46;
-		uint64_t reserved_53_63              : 11;
-	} s;
-};
-
-union otx2_ree_lf_ena {
-	uint64_t u;
-	struct {
-		uint64_t ena                         : 1;
-		uint64_t reserved_1_63               : 63;
-	} s;
-};
-
-union otx2_ree_af_reexm_max_match {
-	uint64_t u;
-	struct {
-		uint64_t max                         : 8;
-		uint64_t reserved_8_63               : 56;
-	} s;
-};
-
-union otx2_ree_lf_done {
-	uint64_t u;
-	struct {
-		uint64_t done                        : 20;
-		uint64_t reserved_20_63              : 44;
-	} s;
-};
-
-union otx2_ree_inst {
-	uint64_t u[8];
-	struct  {
-		uint64_t doneint                     :  1;
-		uint64_t reserved_1_3                :  3;
-		uint64_t dg                          :  1;
-		uint64_t reserved_5_7                :  3;
-		uint64_t ooj                         :  1;
-		uint64_t reserved_9_15               :  7;
-		uint64_t reserved_16_63              : 48;
-		uint64_t inp_ptr_addr                : 64;
-		uint64_t inp_ptr_ctl                 : 64;
-		uint64_t res_ptr_addr                : 64;
-		uint64_t wq_ptr                      : 64;
-		uint64_t tag                         : 32;
-		uint64_t tt                          :  2;
-		uint64_t ggrp                        : 10;
-		uint64_t reserved_364_383            : 20;
-		uint64_t reserved_384_391            :  8;
-		uint64_t ree_job_id                  : 24;
-		uint64_t ree_job_ctrl                : 16;
-		uint64_t ree_job_length              : 15;
-		uint64_t reserved_447_447            :  1;
-		uint64_t ree_job_subset_id_0         : 16;
-		uint64_t ree_job_subset_id_1         : 16;
-		uint64_t ree_job_subset_id_2         : 16;
-		uint64_t ree_job_subset_id_3         : 16;
-	} cn98xx;
-};
-
-union otx2_ree_res_status {
-	uint64_t u;
-	struct {
-		uint64_t job_type                    :  3;
-		uint64_t mpt_cnt_det                 :  1;
-		uint64_t mst_cnt_det                 :  1;
-		uint64_t ml_cnt_det                  :  1;
-		uint64_t mm_cnt_det                  :  1;
-		uint64_t mp_cnt_det                  :  1;
-		uint64_t mode                        :  2;
-		uint64_t reserved_10_11              :  2;
-		uint64_t reserved_12_12              :  1;
-		uint64_t pmi_soj                     :  1;
-		uint64_t pmi_eoj                     :  1;
-		uint64_t reserved_15_15              :  1;
-		uint64_t reserved_16_63              : 48;
-	} s;
-};
-
-union otx2_ree_res {
-	uint64_t u[8];
-	struct ree_res_s_98 {
-		uint64_t done			:  1;
-		uint64_t hwjid			:  7;
-		uint64_t ree_res_job_id		: 24;
-		uint64_t ree_res_status		: 16;
-		uint64_t ree_res_dmcnt		:  8;
-		uint64_t ree_res_mcnt		:  8;
-		uint64_t ree_meta_ptcnt		: 16;
-		uint64_t ree_meta_icnt		: 16;
-		uint64_t ree_meta_lcnt		: 16;
-		uint64_t ree_pmi_min_byte_ptr	: 16;
-		uint64_t ree_err		:  1;
-		uint64_t reserved_129_190	: 62;
-		uint64_t doneint		:  1;
-		uint64_t reserved_192_255	: 64;
-		uint64_t reserved_256_319	: 64;
-		uint64_t reserved_320_383	: 64;
-		uint64_t reserved_384_447	: 64;
-		uint64_t reserved_448_511	: 64;
-	} s;
-};
-
-union otx2_ree_match {
-	uint64_t u;
-	struct {
-		uint64_t ree_rule_id                 : 32;
-		uint64_t start_ptr                   : 14;
-		uint64_t reserved_46_47              :  2;
-		uint64_t match_length                : 15;
-		uint64_t reserved_63_63              :  1;
-	} s;
-};
-
-void otx2_ree_err_intr_unregister(const struct rte_regexdev *dev);
-
-int otx2_ree_err_intr_register(const struct rte_regexdev *dev);
-
-int otx2_ree_iq_enable(const struct rte_regexdev *dev,
-		       const struct otx2_ree_qp *qp,
-		       uint8_t pri, uint32_t size_div128);
-
-void otx2_ree_iq_disable(struct otx2_ree_qp *qp);
-
-int otx2_ree_max_matches_get(const struct rte_regexdev *dev,
-			     uint8_t *max_matches);
-
-#endif /* _OTX2_REGEXDEV_HW_ACCESS_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.c b/drivers/regex/octeontx2/otx2_regexdev_mbox.c
deleted file mode 100644
index 6d58d367d4..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_mbox.h"
-#include "otx2_regexdev.h"
-
-int
-otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-			      uint16_t *nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct free_rsrcs_rsp *rsp;
-	struct otx2_dev *otx2_dev;
-	int ret;
-
-	otx2_dev = &vf->otx2_dev;
-	otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);
-
-	ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
-	if (ret)
-		return -EIO;
-
-	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-		*nb_queues = rsp->ree0;
-	else
-		*nb_queues = rsp->ree1;
-	return 0;
-}
-
-int
-otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_attach_req *req;
-	struct otx2_mbox *mbox;
-
-	/* Ask AF to attach required LFs */
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_attach_resources(mbox);
-
-	/* 1 LF = 1 queue */
-	req->reelfs = nb_queues;
-	req->ree_blkaddr = vf->block_address;
-
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Update number of attached queues */
-	vf->nb_queues = nb_queues;
-
-	return 0;
-}
-
-int
-otx2_ree_queues_detach(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_detach_req *req;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_detach_resources(mbox);
-	req->reelfs = true;
-	req->partial = true;
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Queues have been detached */
-	vf->nb_queues = 0;
-
-	return 0;
-}
-
-int
-otx2_ree_msix_offsets_get(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct msix_offset_rsp *rsp;
-	struct otx2_mbox *mbox;
-	uint32_t i, ret;
-
-	/* Get REE MSI-X vector offsets */
-	mbox = vf->otx2_dev.mbox;
-	otx2_mbox_alloc_msg_msix_offset(mbox);
-
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
-		else
-			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
-		otx2_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
-	}
-
-	return 0;
-}
-
-static int
-ree_send_mbox_msg(struct otx2_ree_vf *vf)
-{
-	struct otx2_mbox *mbox = vf->otx2_dev.mbox;
-	int ret;
-
-	otx2_mbox_msg_send(mbox, 0);
-
-	ret = otx2_mbox_wait_for_rsp(mbox, 0);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-
-	return 0;
-}
-
-int
-otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		   uint32_t size)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_lf_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_ree_config_lf(mbox);
-
-	req->lf = lf;
-	req->pri =  pri ? 1 : 0;
-	req->size = size;
-	req->blkaddr = vf->block_address;
-
-	ret = otx2_mbox_process(mbox);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-	return 0;
-}
-
-int
-otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-		     uint64_t *val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox_dev *mdev;
-	struct otx2_mbox *mbox;
-	int ret, off;
-
-	mbox = vf->otx2_dev.mbox;
-	mdev = &mbox->dev[0];
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 0;
-	msg->reg_offset = reg;
-	msg->ret_val = val;
-	msg->blkaddr = vf->block_address;
-
-	ret = ree_send_mbox_msg(vf);
-	if (ret < 0)
-		return ret;
-
-	off = mbox->rx_start +
-			RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
-	msg = (struct ree_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);
-
-	*val = msg->val;
-
-	return 0;
-}
-
-int
-otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-		      uint64_t val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 1;
-	msg->reg_offset = reg;
-	msg->val = val;
-	msg->blkaddr = vf->block_address;
-
-	return ree_send_mbox_msg(vf);
-}
-
-int
-otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_get_req_msg *req;
-	struct ree_rule_db_get_rsp_msg *rsp;
-	char *rule_db_ptr = (char *)rule_db;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct otx2_mbox *mbox;
-	int ret, last = 0;
-	uint32_t len = 0;
-
-	mbox = vf->otx2_dev.mbox;
-	if (!rule_db) {
-		otx2_err("Couldn't return rule db due to NULL pointer");
-		return -EFAULT;
-	}
-
-	while (!last) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 0;
-		req->offset = len;
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_db_len < len + rsp->len) {
-			otx2_err("Rule db size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
-		len += rsp->len;
-		rule_db_ptr = rule_db_ptr + rsp->len;
-		last = rsp->is_last;
-	}
-
-	if (rule_dbi) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 1;
-		req->offset = 0;
-
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_dbi_len < rsp->len) {
-			otx2_err("Rule dbi size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-		uint32_t *rule_db_len,
-		uint32_t *rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_len_rsp_msg *rsp;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = (struct ree_req_msg *)
-		otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), sizeof(*rsp));
-	if (!req) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
-	req->hdr.sig = OTX2_MBOX_REQ_SIG;
-	req->hdr.pcifunc = vf->otx2_dev.pf_func;
-	req->blkaddr = vf->block_address;
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-	if (rule_db_len != NULL)
-		*rule_db_len = rsp->len;
-	if (rule_dbi_len != NULL)
-		*rule_dbi_len = rsp->inc_len;
-
-	return 0;
-}
-
-static int
-ree_db_msg(const struct rte_regexdev *dev, const char *db, uint32_t db_len,
-		int inc, int dbi)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	uint32_t len_left = db_len, offset = 0;
-	struct ree_rule_db_prog_req_msg *req;
-	struct otx2_ree_vf *vf = &data->vf;
-	const char *rule_db_ptr = db;
-	struct otx2_mbox *mbox;
-	struct msg_rsp *rsp;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	while (len_left) {
-		req = (struct ree_rule_db_prog_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->offset = offset;
-		req->total_len = db_len;
-		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
-		req->is_incremental = inc;
-		req->is_dbi = dbi;
-		req->blkaddr = vf->block_address;
-
-		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
-			req->is_last = true;
-			req->len = len_left;
-		}
-		otx2_mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret) {
-			otx2_err("Programming mailbox processing failed");
-			return ret;
-		}
-		len_left -= req->len;
-		offset += req->len;
-		rule_db_ptr = rule_db_ptr + req->len;
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len)
-{
-	int inc, ret;
-
-	if (rule_db_len == 0) {
-		otx2_err("Couldn't program empty rule db");
-		return -EFAULT;
-	}
-	inc = (rule_dbi_len != 0);
-	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
-		otx2_err("Couldn't program NULL rule db");
-		return -EFAULT;
-	}
-	if (inc) {
-		ret = ree_db_msg(dev, rule_dbi, rule_dbi_len, inc, 1);
-		if (ret)
-			return ret;
-	}
-	return ree_db_msg(dev, rule_db, rule_db_len, inc, 0);
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.h b/drivers/regex/octeontx2/otx2_regexdev_mbox.h
deleted file mode 100644
index 953efa6724..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_MBOX_H_
-#define _OTX2_REGEXDEV_MBOX_H_
-
-#include <rte_regexdev.h>
-
-int otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-				  uint16_t *nb_queues);
-
-int otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues);
-
-int otx2_ree_queues_detach(const struct rte_regexdev *dev);
-
-int otx2_ree_msix_offsets_get(const struct rte_regexdev *dev);
-
-int otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		       uint32_t size);
-
-int otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-			 uint64_t *val);
-
-int otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-			  uint64_t val);
-
-int otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		 uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len);
-
-int otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-			     uint32_t *rule_db_len, uint32_t *rule_dbi_len);
-
-int otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len);
-
-#endif /* _OTX2_REGEXDEV_MBOX_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* RE: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure
       [not found]     ` <20211123193835.20601-1-robot@bytheb.org>
@ 2021-11-28 20:17       ` Liron Himi
  2021-11-28 20:37         ` Thomas Monjalon
  0 siblings, 1 reply; 31+ messages in thread
From: Liron Himi @ 2021-11-28 20:17 UTC (permalink / raw)
  To: thomas, David Marchand, Yigit, Ferruh
  Cc: Jerin Jacob Kollanukkaran, dev, Liron Himi

Hi,

I have fixed the error below but got additional errors which I need your advice if to ignore or update it is some way.
This patch also replace the name of the 'regexdevs/octeontx2' folder to 'regexdevs/cn9k'
Note that Jerin is going to remove the current 'octeontx2' references as the new cnxk is replacing it.

What should I do with those errors:
dpdk-next-net-mrvl/doc/guides/platform/octeontx2.rst:158:unknown document: ../regexdevs/octeontx2
dpdk-next-net-mrvl/doc/guides/rel_notes/release_20_11.rst:293:unknown document: ../regexdevs/octeontx2
 

Liron Himi


-----Original Message-----
From: 0-day Robot <robot@bytheb.org> 
Sent: Tuesday, 23 November 2021 21:39
To: test-report@dpdk.org
Cc: Liron Himi <lironh@marvell.com>; robot@bytheb.org
Subject: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure

External Email

----------------------------------------------------------------------
From: robot@bytheb.org

Test-Label: github-robot: build
Test-Status: FAILURE
https://urldefense.proofpoint.com/v2/url?u=http-3A__patchwork.dpdk.org_patch_104631_&d=DwIDAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=M6lEONY3jVnAkBjt0yC6oAsT7Jn2HI7LhNHCQYlnx1Q&m=t5lFxhoB1xIBWU8MMJw2Ye8t3ipEQRRXa1tkPiNY014-j9RG8StvAwgSnKqpi6hn&s=0Bb6lOdxDfbDXDGLguBU0SeNJX8pyNvRPfZm3kkFMwI&e= 

_github build: failed_
Build URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_ovsrobot_dpdk_actions_runs_1496327439&d=DwIDAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=M6lEONY3jVnAkBjt0yC6oAsT7Jn2HI7LhNHCQYlnx1Q&m=t5lFxhoB1xIBWU8MMJw2Ye8t3ipEQRRXa1tkPiNY014-j9RG8StvAwgSnKqpi6hn&s=gFlcioDYnxi99XqRR_n9qBCtQH2axCFaqhL_OFd6NOs&e=
Build Logs:
-----------------------Summary of failed steps----------------------- "ubuntu-18.04-gcc-shared-doc+tests" failed at step Build and test "ubuntu-18.04-clang-shared-doc+tests" failed at step Build and test ----------------------End summary of failed steps--------------------

-------------------------------BEGIN LOGS---------------------------- ####################################################################################
#### [Begin job log] "ubuntu-18.04-gcc-shared-doc+tests" at step Build and test ####################################################################################
[3208/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_mempool_trace_fp.c'.
[3209/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_mbuf.c'.
[3210/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_mbuf_core.c'.
[3211/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_mbuf_ptype.c'.
[3212/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_mbuf_pool_ops.c'.
[3213/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_mbuf_dyn.c'.
[3214/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_ip.c'.
[3215/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_tcp.c'.
[3216/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_udp.c'.
[3217/3617] Generating html_guides with a custom command.
FAILED: doc/guides/html
/usr/bin/python3 ../buildtools/call-sphinx-build.py /usr/bin/sphinx-build 21.11.0-rc3 /home/runner/work/dpdk/dpdk/doc/guides /home/runner/work/dpdk/dpdk/build/doc/guides -W

Warning, treated as error:
/home/runner/work/dpdk/dpdk/doc/guides/regexdevs/cn9k.rst:45:Malformed table.

+---+------------+-------------------------------------------------------+
| # | Component  | EAL log command                                       |
+===+============+======================================================
+=+
| 1 | REE        | --log-level='pmd\.regex\.cn9k,8'                 |
+---+------------+-------------------------------------------------------+
[3218/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_esp.c'.
[3219/3617] Generating 'buildtools/chkincs/fe389a9@@chkincs@exe/rte_sctp.c'.
ninja: build stopped: subcommand failed.
##[error]Process completed with exit code 1.
####################################################################################
#### [End job log] "ubuntu-18.04-gcc-shared-doc+tests" at step Build and test ####################################################################################




####################################################################################
#### [Begin job log] "ubuntu-18.04-clang-shared-doc+tests" at step Build and test ####################################################################################
[3042/3617] Linking target examples/dpdk-kni.
[3043/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd-event@exe/l2fwd-event_l2fwd_common.c.o'.
[3044/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd@exe/l2fwd_main.c.o'.
[3045/3617] Linking target examples/dpdk-l2fwd.
[3046/3617] Linking target examples/dpdk-l2fwd-crypto.
[3047/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd-event@exe/l2fwd-event_l2fwd_event.c.o'.
[3048/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd-event@exe/l2fwd-event_l2fwd_event_internal_port.c.o'.
[3049/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd-event@exe/l2fwd-event_l2fwd_event_generic.c.o'.
[3050/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd-event@exe/l2fwd-event_l2fwd_poll.c.o'.
[3051/3617] Generating html_guides with a custom command.
FAILED: doc/guides/html
/usr/bin/python3 ../buildtools/call-sphinx-build.py /usr/bin/sphinx-build 21.11.0-rc3 /home/runner/work/dpdk/dpdk/doc/guides /home/runner/work/dpdk/dpdk/build/doc/guides -W

Warning, treated as error:
/home/runner/work/dpdk/dpdk/doc/guides/regexdevs/cn9k.rst:45:Malformed table.

+---+------------+-------------------------------------------------------+
| # | Component  | EAL log command                                       |
+===+============+======================================================
+=+
| 1 | REE        | --log-level='pmd\.regex\.cn9k,8'                 |
+---+------------+-------------------------------------------------------+
[3052/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd-jobstats@exe/l2fwd-jobstats_main.c.o'.
[3053/3617] Compiling C object 'examples/c590b3c@@dpdk-l2fwd-keepalive@exe/l2fwd-keepalive_main.c.o'.
ninja: build stopped: subcommand failed.
##[error]Process completed with exit code 1.
####################################################################################
#### [End job log] "ubuntu-18.04-clang-shared-doc+tests" at step Build and test ####################################################################################
--------------------------------END LOGS-----------------------------

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure
  2021-11-28 20:17       ` [EXT] |FAILURE| pw104631 " Liron Himi
@ 2021-11-28 20:37         ` Thomas Monjalon
  2021-11-29  9:55           ` Liron Himi
  0 siblings, 1 reply; 31+ messages in thread
From: Thomas Monjalon @ 2021-11-28 20:37 UTC (permalink / raw)
  To: Liron Himi; +Cc: David Marchand, Yigit, Ferruh, Jerin Jacob Kollanukkaran, dev

28/11/2021 21:17, Liron Himi:
> Hi,
> 
> I have fixed the error below but got additional errors which I need your advice if to ignore or update it is some way.
> This patch also replace the name of the 'regexdevs/octeontx2' folder to 'regexdevs/cn9k'
> Note that Jerin is going to remove the current 'octeontx2' references as the new cnxk is replacing it.
> 
> What should I do with those errors:
> dpdk-next-net-mrvl/doc/guides/platform/octeontx2.rst:158:unknown document: ../regexdevs/octeontx2

This one, you must fix to the next regex doc.

> dpdk-next-net-mrvl/doc/guides/rel_notes/release_20_11.rst:293:unknown document: ../regexdevs/octeontx2

This one, you must replace the link with a normal text.
For instance, this is what was done for another octeontx2 driver:

-  See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.
+  See ``rawdevs/octeontx2_ep`` for more details on this new PMD.




^ permalink raw reply	[flat|nested] 31+ messages in thread

* RE: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure
  2021-11-28 20:37         ` Thomas Monjalon
@ 2021-11-29  9:55           ` Liron Himi
  2021-11-29 10:10             ` Thomas Monjalon
  0 siblings, 1 reply; 31+ messages in thread
From: Liron Himi @ 2021-11-29  9:55 UTC (permalink / raw)
  To: Thomas Monjalon
  Cc: David Marchand, Yigit, Ferruh, Jerin Jacob Kollanukkaran, dev,
	Liron Himi

Hi Thomas,


-----Original Message-----
From: Thomas Monjalon <thomas@monjalon.net> 
Sent: Sunday, 28 November 2021 22:37
To: Liron Himi <lironh@marvell.com>
Cc: David Marchand <david.marchand@redhat.com>; Yigit, Ferruh <ferruh.yigit@intel.com>; Jerin Jacob Kollanukkaran <jerinj@marvell.com>; dev@dpdk.org
Subject: Re: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure

28/11/2021 21:17, Liron Himi:
> Hi,
> 
> I have fixed the error below but got additional errors which I need your advice if to ignore or update it is some way.
> This patch also replace the name of the 'regexdevs/octeontx2' folder to 'regexdevs/cn9k'
> Note that Jerin is going to remove the current 'octeontx2' references as the new cnxk is replacing it.
> 
> What should I do with those errors:
> dpdk-next-net-mrvl/doc/guides/platform/octeontx2.rst:158:unknown document: ../regexdevs/octeontx2

This one, you must fix to the next regex doc.
[L.H.] okay.

> dpdk-next-net-mrvl/doc/guides/rel_notes/release_20_11.rst:293:unknown document: ../regexdevs/octeontx2

This one, you must replace the link with a normal text.
For instance, this is what was done for another octeontx2 driver:

-  See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.
+  See ``rawdevs/octeontx2_ep`` for more details on this new PMD.
[L.H.] but this file represent the release notes of dpdk-20.11, right? so, in this release the driver is still 'regexdevs/octeontx2'.
only in the upcoming release the driver name will be changed to "regexdevs/cn9k".
I also think this is relevant for the example you provided. In dpdk-20.11 the driver was "rawdevs/octeontx2_ep"





^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure
  2021-11-29  9:55           ` Liron Himi
@ 2021-11-29 10:10             ` Thomas Monjalon
  0 siblings, 0 replies; 31+ messages in thread
From: Thomas Monjalon @ 2021-11-29 10:10 UTC (permalink / raw)
  To: Liron Himi; +Cc: David Marchand, Yigit, Ferruh, Jerin Jacob Kollanukkaran, dev

29/11/2021 10:55, Liron Himi:
> From: Thomas Monjalon <thomas@monjalon.net> 
> 28/11/2021 21:17, Liron Himi:
> > Hi,
> > 
> > I have fixed the error below but got additional errors which I need your advice if to ignore or update it is some way.
> > This patch also replace the name of the 'regexdevs/octeontx2' folder to 'regexdevs/cn9k'
> > Note that Jerin is going to remove the current 'octeontx2' references as the new cnxk is replacing it.
> > 
> > What should I do with those errors:
> > dpdk-next-net-mrvl/doc/guides/platform/octeontx2.rst:158:unknown document: ../regexdevs/octeontx2
> 
> This one, you must fix to the next regex doc.
> [L.H.] okay.
> 
> > dpdk-next-net-mrvl/doc/guides/rel_notes/release_20_11.rst:293:unknown document: ../regexdevs/octeontx2
> 
> This one, you must replace the link with a normal text.
> For instance, this is what was done for another octeontx2 driver:
> 
> -  See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.
> +  See ``rawdevs/octeontx2_ep`` for more details on this new PMD.
> [L.H.] but this file represent the release notes of dpdk-20.11, right? so, in this release the driver is still 'regexdevs/octeontx2'.
> only in the upcoming release the driver name will be changed to "regexdevs/cn9k".
> I also think this is relevant for the example you provided. In dpdk-20.11 the driver was "rawdevs/octeontx2_ep"

In new releases, the driver doesn't exist, right?
So the documentation, including old release notes cannot compile
with a reference to a removed page.
That's why we need to transform this link to a removed page.

If you want to see the old documentation, you can go to
	https://doc.dpdk.org/guides-20.11/



^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
                     ` (4 preceding siblings ...)
  2021-11-23 19:13   ` [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure lironh
@ 2021-11-29 19:47   ` lironh
  2021-11-29 19:47     ` [PATCH v3 " lironh
                       ` (5 more replies)
  2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
  2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
  7 siblings, 6 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:47 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 drivers/common/cnxk/hw/ree.h                  | 126 ++++
 drivers/common/cnxk/hw/rvu.h                  |   5 +
 drivers/common/cnxk/meson.build               |   1 +
 drivers/common/cnxk/roc_api.h                 |   4 +
 drivers/common/cnxk/roc_constants.h           |   2 +
 drivers/common/cnxk/roc_mbox.h                | 100 +++
 drivers/common/cnxk/roc_platform.c            |   1 +
 drivers/common/cnxk/roc_platform.h            |   2 +
 drivers/common/cnxk/roc_priv.h                |   3 +
 drivers/common/cnxk/roc_ree.c                 | 647 ++++++++++++++++++
 drivers/common/cnxk/roc_ree.h                 | 137 ++++
 drivers/common/cnxk/roc_ree_priv.h            |  18 +
 drivers/common/cnxk/version.map               |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +++++------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -----
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 31 files changed, 1331 insertions(+), 1202 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (68%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 0/5] regex/cn9k: use cnxk infrastructure
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
@ 2021-11-29 19:47     ` lironh
  2021-11-29 19:47     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
                       ` (4 subsequent siblings)
  5 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:47 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v3:
- fix documentation issues

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 doc/guides/platform/octeontx2.rst             |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 doc/guides/rel_notes/release_20_11.rst        |   2 +-
 drivers/common/cnxk/hw/ree.h                  | 126 ++++
 drivers/common/cnxk/hw/rvu.h                  |   5 +
 drivers/common/cnxk/meson.build               |   1 +
 drivers/common/cnxk/roc_api.h                 |   4 +
 drivers/common/cnxk/roc_constants.h           |   2 +
 drivers/common/cnxk/roc_mbox.h                | 100 +++
 drivers/common/cnxk/roc_platform.c            |   1 +
 drivers/common/cnxk/roc_platform.h            |   2 +
 drivers/common/cnxk/roc_priv.h                |   3 +
 drivers/common/cnxk/roc_ree.c                 | 647 ++++++++++++++++++
 drivers/common/cnxk/roc_ree.h                 | 137 ++++
 drivers/common/cnxk/roc_ree_priv.h            |  18 +
 drivers/common/cnxk/version.map               |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +++++------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -----
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 33 files changed, 1332 insertions(+), 1206 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 1/5] common/cnxk: add REE HW definitions
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
  2021-11-29 19:47     ` [PATCH v3 " lironh
@ 2021-11-29 19:47     ` lironh
  2021-11-29 19:47     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
                       ` (3 subsequent siblings)
  5 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:47 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

adding REE (Regular Expression Engine) HW definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/hw/ree.h | 126 +++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/hw/rvu.h |   5 ++
 2 files changed, 131 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/ree.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 0000000000..30af61d704
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BIT	   BIT_ULL(14)
+#define REE_STATUS_PMI_SOJ_BIT	   BIT_ULL(13)
+#define REE_STATUS_MP_CNT_DET_BIT  BIT_ULL(7)
+#define REE_STATUS_MM_CNT_DET_BIT  BIT_ULL(6)
+#define REE_STATUS_ML_CNT_DET_BIT  BIT_ULL(5)
+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT		0x120ull
+#define REE_LF_DONE_INT_W1S	0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT		0x300ull
+#define REE_LF_MISC_INT_W1S	0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA		0x10ull
+#define REE_LF_SBUF_ADDR	0x20ull
+#define REE_LF_DONE		0x100ull
+#define REE_LF_DONE_ACK		0x110ull
+#define REE_LF_DONE_WAIT	0x148ull
+#define REE_LF_DOORBELL		0x400ull
+#define REE_LF_OUTSTAND_JOB	0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a)     (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS	(0x0ull)
+#define REE_AF_INT_VEC_RVU	(0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ	(0x3ull)
+
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC	(0x1ull)
+
+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
+
+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)
+
+#define REE_LF_BAR2(vf, q_id)                                                  \
+	((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+	REE_TYPE_JOB_DESC = 0x0,
+	REE_TYPE_RESULT_DESC = 0x1,
+	REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_res_status {
+	uint64_t u;
+	struct {
+		uint64_t job_type : 3;
+		uint64_t mpt_cnt_det : 1;
+		uint64_t mst_cnt_det : 1;
+		uint64_t ml_cnt_det : 1;
+		uint64_t mm_cnt_det : 1;
+		uint64_t mp_cnt_det : 1;
+		uint64_t mode : 2;
+		uint64_t reserved_10_11 : 2;
+		uint64_t reserved_12_12 : 1;
+		uint64_t pmi_soj : 1;
+		uint64_t pmi_eoj : 1;
+		uint64_t reserved_15_15 : 1;
+		uint64_t reserved_16_63 : 48;
+	} s;
+};
+
+union ree_res {
+	uint64_t u[8];
+	struct ree_res_s_98 {
+		uint64_t done : 1;
+		uint64_t hwjid : 7;
+		uint64_t ree_res_job_id : 24;
+		uint64_t ree_res_status : 16;
+		uint64_t ree_res_dmcnt : 8;
+		uint64_t ree_res_mcnt : 8;
+		uint64_t ree_meta_ptcnt : 16;
+		uint64_t ree_meta_icnt : 16;
+		uint64_t ree_meta_lcnt : 16;
+		uint64_t ree_pmi_min_byte_ptr : 16;
+		uint64_t ree_err : 1;
+		uint64_t reserved_129_190 : 62;
+		uint64_t doneint : 1;
+		uint64_t reserved_192_255 : 64;
+		uint64_t reserved_256_319 : 64;
+		uint64_t reserved_320_383 : 64;
+		uint64_t reserved_384_447 : 64;
+		uint64_t reserved_448_511 : 64;
+	} s;
+};
+
+union ree_match {
+	uint64_t u;
+	struct {
+		uint64_t ree_rule_id : 32;
+		uint64_t start_ptr : 14;
+		uint64_t reserved_46_47 : 2;
+		uint64_t match_length : 15;
+		uint64_t reserved_63_6 : 1;
+	} s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM    (0x0ull)
 #define RVU_BLOCK_ADDR_LMT     (0x1ull)
@@ -147,6 +148,8 @@
 #define RVU_BLOCK_ADDR_NDC2    (0xeull)
 #define RVU_BLOCK_ADDR_R_END   (0x1full)
 #define RVU_BLOCK_ADDR_R_START (0x14ull)
+#define RVU_BLOCK_ADDR_REE0    (0x14ull)
+#define RVU_BLOCK_ADDR_REE1    (0x15ull)
 
 #define RVU_VF_INT_VEC_MBOX (0x0ull)
 
@@ -167,6 +170,7 @@
 #define NPA_AF_BAR2_SEL	 (0x9000000ull)
 #define CPT_AF_BAR2_SEL	 (0x9000000ull)
 #define RVU_AF_BAR2_SEL	 (0x9000000ull)
+#define REE_AF_BAR2_SEL	 (0x9000000ull)
 
 #define AF_BAR2_ALIASX(a, b)                                                   \
 	(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))
@@ -177,6 +181,7 @@
 #define NPA_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(0, b)
 #define CPT_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 #define RVU_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
+#define REE_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 
 /* Structures definitions */
 
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 2/5] common/cnxk: add REE mbox definitions
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
  2021-11-29 19:47     ` [PATCH v3 " lironh
  2021-11-29 19:47     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
@ 2021-11-29 19:47     ` lironh
  2021-11-29 19:47     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
                       ` (2 subsequent siblings)
  5 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:47 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add REE mbox definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 100 +++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..e97d93e261 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -151,6 +151,16 @@ struct mbox_msghdr {
 	M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)        \
 	M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,            \
 	  cpt_eng_grp_rsp)                                                     \
+	/* REE mbox IDs (range 0xE00 - 0xFFF) */                               \
+	M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)        \
+	M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,    \
+	  ree_rd_wr_reg_msg)                                                   \
+	M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+	  msg_rsp)                                                             \
+	M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,        \
+	  ree_rule_db_len_rsp_msg)                                             \
+	M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,    \
+	  ree_rule_db_get_rsp_msg)                                             \
 	/* SDP mbox IDs (range 0x1000 - 0x11FF) */                             \
 	M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg,     \
 	  msg_rsp)                                                             \
@@ -1452,6 +1462,96 @@ struct cpt_eng_grp_rsp {
 	uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+	REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+	REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+	REE_AF_ERR_LF_INVALID = -1003,
+	REE_AF_ERR_ACCESS_DENIED = -1004,
+	REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+	REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+	REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+	REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+	REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+	REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+	REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+	REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+	REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+	REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+	REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+	REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+	REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+	REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+	REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+	REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+	REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+	REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+	REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io size;
+	uint8_t __io lf;
+	uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+	uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+	uint32_t __io blkaddr;	     /* REE0 or REE1 */
+	uint32_t __io total_len;     /* total len of rule db */
+	uint32_t __io offset;	     /* offset of current rule db block */
+	uint16_t __io len;	     /* length of rule db block */
+	uint8_t __io is_last;	     /* is this the last block */
+	uint8_t __io is_incremental; /* is incremental flow */
+	uint8_t __io is_dbi;	     /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io offset; /* retrieve db from this offset */
+	uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+	struct mbox_msghdr hdr;
+	uint64_t __io reg_offset;
+	uint64_t __io *ret_val;
+	uint64_t __io val;
+	uint32_t __io blkaddr;
+	uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io len;
+	uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+	uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+	uint32_t __io total_len; /* total len of rule db */
+	uint32_t __io offset;	 /* offset of current rule db block */
+	uint16_t __io len;	 /* length of rule db block */
+	uint8_t __io is_last;	 /* is this the last block */
+};
+
 /* NPC mbox message structs */
 
 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 3/5] common/cnxk: add REE support
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
                       ` (2 preceding siblings ...)
  2021-11-29 19:47     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
@ 2021-11-29 19:47     ` lironh
  2021-11-29 19:47     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
  2021-11-29 19:47     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
  5 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:47 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

extend cnxk infrastructure to support REE

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_ree.c      | 647 +++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ree.h      | 137 ++++++
 drivers/common/cnxk/roc_ree_priv.h |  18 +
 3 files changed, 802 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 0000000000..1eb2ae7272
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+	struct free_rsrcs_rsp *rsp;
+	struct dev *dev = vf->dev;
+	int ret;
+
+	mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+		*nb_queues = rsp->ree0;
+	else
+		*nb_queues = rsp->ree1;
+	return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+	uint64_t val;
+	int ret;
+
+	ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+	if (ret)
+		return ret;
+
+	*max_matches = val;
+	return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+	struct rsrc_attach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	/* Ask AF to attach required LFs */
+	req = mbox_alloc_msg_attach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	/* 1 LF = 1 queue */
+	req->reelfs = nb_queues;
+	req->ree_blkaddr = vf->block_address;
+
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Update number of attached queues */
+	vf->nb_queues = nb_queues;
+
+	return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+	struct rsrc_detach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_detach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+	req->reelfs = true;
+	req->partial = true;
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Queues have been detached */
+	vf->nb_queues = 0;
+
+	return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+	struct msix_offset_rsp *rsp;
+	struct mbox *mbox;
+	uint32_t i, ret;
+
+	/* Get REE MSI-X vector offsets */
+	mbox = vf->dev->mbox;
+	mbox_alloc_msg_msix_offset(mbox);
+
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+		else
+			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+		plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+	}
+
+	return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+	struct mbox *mbox = vf->dev->mbox;
+	int ret;
+
+	mbox_msg_send(mbox, 0);
+
+	ret = mbox_wait_for_rsp(mbox, 0);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+
+	return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t size)
+{
+	struct ree_lf_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_ree_config_lf(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->lf = lf;
+	req->pri = pri ? 1 : 0;
+	req->size = size;
+	req->blkaddr = vf->block_address;
+
+	ret = mbox_process(mbox);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+	return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox_dev *mdev;
+	struct mbox *mbox;
+	int ret, off;
+
+	mbox = vf->dev->mbox;
+	mdev = &mbox->dev[0];
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 0;
+	msg->reg_offset = reg;
+	msg->ret_val = val;
+	msg->blkaddr = vf->block_address;
+
+	ret = ree_send_mbox_msg(vf);
+	if (ret < 0)
+		return ret;
+
+	off = mbox->rx_start +
+	      RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+	msg = (struct ree_rd_wr_reg_msg *)((uintptr_t)mdev->mbase + off);
+
+	*val = msg->val;
+
+	return 0;
+}
+
+int
+roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg, uint64_t val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 1;
+	msg->reg_offset = reg;
+	msg->val = val;
+	msg->blkaddr = vf->block_address;
+
+	return ree_send_mbox_msg(vf);
+}
+
+int
+roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db, uint32_t rule_db_len,
+		    char *rule_dbi, uint32_t rule_dbi_len)
+{
+	struct ree_rule_db_get_req_msg *req;
+	struct ree_rule_db_get_rsp_msg *rsp;
+	char *rule_db_ptr = (char *)rule_db;
+	struct mbox *mbox;
+	int ret, last = 0;
+	uint32_t len = 0;
+
+	mbox = vf->dev->mbox;
+	if (!rule_db) {
+		plt_err("Couldn't return rule db due to NULL pointer");
+		return -EFAULT;
+	}
+
+	while (!last) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 0;
+		req->offset = len;
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_db_len < len + rsp->len) {
+			plt_err("Rule db size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
+		len += rsp->len;
+		rule_db_ptr = rule_db_ptr + rsp->len;
+		last = rsp->is_last;
+	}
+
+	if (rule_dbi) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 1;
+		req->offset = 0;
+
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_dbi_len < rsp->len) {
+			plt_err("Rule dbi size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_len_get(struct roc_ree_vf *vf, uint32_t *rule_db_len,
+			uint32_t *rule_dbi_len)
+{
+	struct ree_rule_db_len_rsp_msg *rsp;
+	struct ree_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = (struct ree_req_msg *)mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
+						       sizeof(*rsp));
+	if (!req) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
+	req->hdr.sig = MBOX_REQ_SIG;
+	req->hdr.pcifunc = vf->dev->pf_func;
+	req->blkaddr = vf->block_address;
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+	if (rule_db_len != NULL)
+		*rule_db_len = rsp->len;
+	if (rule_dbi_len != NULL)
+		*rule_dbi_len = rsp->inc_len;
+
+	return 0;
+}
+
+static int
+ree_db_msg(struct roc_ree_vf *vf, const char *db, uint32_t db_len, int inc,
+	   int dbi)
+{
+	uint32_t len_left = db_len, offset = 0;
+	struct ree_rule_db_prog_req_msg *req;
+	const char *rule_db_ptr = db;
+	struct mbox *mbox;
+	struct msg_rsp *rsp;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	while (len_left) {
+		req = (struct ree_rule_db_prog_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->offset = offset;
+		req->total_len = db_len;
+		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
+		req->is_incremental = inc;
+		req->is_dbi = dbi;
+		req->blkaddr = vf->block_address;
+
+		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
+			req->is_last = true;
+			req->len = len_left;
+		}
+		mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret) {
+			plt_err("Programming mailbox processing failed");
+			return ret;
+		}
+		len_left -= req->len;
+		offset += req->len;
+		rule_db_ptr = rule_db_ptr + req->len;
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+		     uint32_t rule_db_len, const char *rule_dbi,
+		     uint32_t rule_dbi_len)
+{
+	int inc, ret;
+
+	if (rule_db_len == 0) {
+		plt_err("Couldn't program empty rule db");
+		return -EFAULT;
+	}
+	inc = (rule_dbi_len != 0);
+	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
+		plt_err("Couldn't program NULL rule db");
+		return -EFAULT;
+	}
+	if (inc) {
+		ret = ree_db_msg(vf, rule_dbi, rule_dbi_len, inc, 1);
+		if (ret)
+			return ret;
+	}
+	return ree_db_msg(vf, rule_db, rule_db_len, inc, 0);
+}
+
+static int
+ree_get_blkaddr(struct dev *dev)
+{
+	int pf;
+
+	pf = dev_get_pf(dev->pf_func);
+	if (pf == REE0_PF)
+		return RVU_BLOCK_ADDR_REE0;
+	else if (pf == REE1_PF)
+		return RVU_BLOCK_ADDR_REE1;
+	else
+		return 0;
+}
+
+uintptr_t
+roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id)
+{
+	return REE_LF_BAR2(vf, qp_id);
+}
+
+static void
+roc_ree_lf_err_intr_handler(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint8_t lf_id;
+	uint64_t intr;
+
+	lf_id = (base >> 12) & 0xFF;
+
+	intr = plt_read64(base + REE_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
+
+	/* Clear interrupt */
+	plt_write64(intr, base + REE_LF_MISC_INT);
+}
+
+static void
+roc_ree_lf_err_intr_unregister(struct roc_ree_vf *vf, uint16_t msix_off,
+			       uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	dev_irq_unregister(pci_dev->intr_handle,
+			   roc_ree_lf_err_intr_handler, (void *)base, msix_off);
+}
+
+void
+roc_ree_err_intr_unregister(struct roc_ree_vf *vf)
+{
+	uintptr_t base;
+	uint32_t i;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base);
+	}
+
+	vf->err_intr_registered = 0;
+}
+
+static int
+roc_ree_lf_err_intr_register(struct roc_ree_vf *vf, uint16_t msix_off,
+			     uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+	int ret;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	/* Register error interrupt handler */
+	ret = dev_irq_register(pci_dev->intr_handle,
+			       roc_ree_lf_err_intr_handler, (void *)base,
+			       msix_off);
+	if (ret)
+		return ret;
+
+	/* Enable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1S);
+
+	return 0;
+}
+
+int
+roc_ree_err_intr_register(struct roc_ree_vf *vf)
+{
+	uint32_t i, j, ret;
+	uintptr_t base;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
+			plt_err("Invalid REE LF MSI-X offset: 0x%x",
+				vf->lf_msixoff[i]);
+			return -EINVAL;
+		}
+	}
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		ret = roc_ree_lf_err_intr_register(vf, vf->lf_msixoff[i], base);
+		if (ret)
+			goto intr_unregister;
+	}
+
+	vf->err_intr_registered = 1;
+	return 0;
+
+intr_unregister:
+	/* Unregister the ones already registered */
+	for (j = 0; j < i; j++) {
+		base = REE_LF_BAR2(vf, j);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[j], base);
+	}
+	return ret;
+}
+
+int
+roc_ree_iq_enable(struct roc_ree_vf *vf, const struct roc_ree_qp *qp,
+		  uint8_t pri, uint32_t size_div2)
+{
+	uint64_t val;
+
+	/* Set instruction queue size and priority */
+	roc_ree_config_lf(vf, qp->id, pri, size_div2);
+
+	/* Set instruction queue base address */
+	/* Should be written after SBUF_CTL and before LF_ENA */
+
+	val = plt_read64(qp->base + REE_LF_SBUF_ADDR);
+	val &= ~REE_LF_SBUF_ADDR_PTR_MASK;
+	val |= FIELD_PREP(REE_LF_SBUF_ADDR_PTR_MASK, qp->iq_dma_addr >> 7);
+	plt_write64(val, qp->base + REE_LF_SBUF_ADDR);
+
+	/* Enable instruction queue */
+
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 1);
+	plt_write64(val, qp->base + REE_LF_ENA);
+
+	return 0;
+}
+
+void
+roc_ree_iq_disable(struct roc_ree_qp *qp)
+{
+	uint64_t val;
+
+	/* Stop instruction execution */
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 0);
+	plt_write64(val, qp->base + REE_LF_ENA);
+}
+
+int
+roc_ree_dev_init(struct roc_ree_vf *vf)
+{
+	struct plt_pci_device *pci_dev;
+	struct ree *ree;
+	struct dev *dev;
+	uint8_t max_matches = 0;
+	uint16_t nb_queues = 0;
+	int rc;
+
+	if (vf == NULL || vf->pci_dev == NULL)
+		return -EINVAL;
+
+	PLT_STATIC_ASSERT(sizeof(struct ree) <= ROC_REE_MEM_SZ);
+
+	ree = roc_ree_to_ree_priv(vf);
+	memset(ree, 0, sizeof(*ree));
+	vf->dev = &ree->dev;
+
+	pci_dev = vf->pci_dev;
+	dev = vf->dev;
+
+	/* Initialize device  */
+	rc = dev_init(dev, pci_dev);
+	if (rc) {
+		plt_err("Failed to init roc device");
+		goto fail;
+	}
+
+	/* Get REE block address */
+	vf->block_address = ree_get_blkaddr(dev);
+	if (!vf->block_address) {
+		plt_err("Could not determine block PF number");
+		goto fail;
+	}
+
+	/* Get number of queues available on the device */
+	rc = roc_ree_available_queues_get(vf, &nb_queues);
+	if (rc) {
+		plt_err("Could not determine the number of queues available");
+		goto fail;
+	}
+
+	/* Don't exceed the limits set per VF */
+	nb_queues = RTE_MIN(nb_queues, REE_MAX_QUEUES_PER_VF);
+
+	if (nb_queues == 0) {
+		plt_err("No free queues available on the device");
+		goto fail;
+	}
+
+	vf->max_queues = nb_queues;
+
+	plt_ree_dbg("Max queues supported by device: %d", vf->max_queues);
+
+	/* Get number of maximum matches supported on the device */
+	rc = roc_ree_max_matches_get(vf, &max_matches);
+	if (rc) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+	/* Don't exceed the limits set per VF */
+	max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
+	if (max_matches == 0) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+
+	vf->max_matches = max_matches;
+
+	plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+fail:
+	return rc;
+}
+
+int
+roc_ree_dev_fini(struct roc_ree_vf *vf)
+{
+	if (vf == NULL)
+		return -EINVAL;
+
+	vf->max_matches = 0;
+	vf->max_queues = 0;
+
+	return dev_fini(vf->dev, vf->pci_dev);
+}
diff --git a/drivers/common/cnxk/roc_ree.h b/drivers/common/cnxk/roc_ree.h
new file mode 100644
index 0000000000..e138e4de66
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_H_
+#define _ROC_REE_H_
+
+#include "roc_api.h"
+
+#define REE_MAX_LFS	       36
+#define REE_MAX_QUEUES_PER_VF  36
+#define REE_MAX_MATCHES_PER_VF 254
+
+#define REE_MAX_PAYLOAD_SIZE (1 << 14)
+
+#define REE_NON_INC_PROG 0
+#define REE_INC_PROG	 1
+
+#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)
+
+/**
+ * Device vf data
+ */
+struct roc_ree_vf {
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	/**< Base class */
+	uint16_t max_queues;
+	/**< Max queues supported */
+	uint8_t nb_queues;
+	/**< Number of regex queues attached */
+	uint16_t max_matches;
+	/**<  Max matches supported*/
+	uint16_t lf_msixoff[REE_MAX_LFS];
+	/**< MSI-X offsets */
+	uint8_t block_address;
+	/**< REE Block Address */
+	uint8_t err_intr_registered : 1;
+	/**< Are error interrupts registered? */
+
+#define ROC_REE_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_REE_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+struct roc_ree_rid {
+	uintptr_t rid;
+	/** Request id of a ree operation */
+	uint64_t user_id;
+	/* Client data */
+	/**< IOVA address of the pattern to be matched. */
+};
+
+struct roc_ree_pending_queue {
+	uint64_t pending_count;
+	/** Pending requests count */
+	struct roc_ree_rid *rid_queue;
+	/** Array of pending requests */
+	uint16_t enq_tail;
+	/** Tail of queue to be used for enqueue */
+	uint16_t deq_head;
+	/** Head of queue to be used for dequeue */
+};
+
+struct roc_ree_qp {
+	uint32_t id;
+	/**< Queue pair id */
+	uintptr_t base;
+	/**< Base address where BAR is mapped */
+	struct roc_ree_pending_queue pend_q;
+	/**< Pending queue */
+	rte_iova_t iq_dma_addr;
+	/**< Instruction queue address */
+	uint32_t roc_regexdev_jobid;
+	/**< Job ID */
+	uint32_t write_offset;
+	/**< write offset */
+};
+
+union roc_ree_inst {
+	uint64_t u[8];
+	struct {
+		uint64_t doneint : 1;
+		uint64_t reserved_1_3 : 3;
+		uint64_t dg : 1;
+		uint64_t reserved_5_7 : 3;
+		uint64_t ooj : 1;
+		uint64_t reserved_9_15 : 7;
+		uint64_t reserved_16_63 : 48;
+		uint64_t inp_ptr_addr : 64;
+		uint64_t inp_ptr_ctl : 64;
+		uint64_t res_ptr_addr : 64;
+		uint64_t wq_ptr : 64;
+		uint64_t tag : 32;
+		uint64_t tt : 2;
+		uint64_t ggrp : 10;
+		uint64_t reserved_364_383 : 20;
+		uint64_t reserved_384_391 : 8;
+		uint64_t ree_job_id : 24;
+		uint64_t ree_job_ctrl : 16;
+		uint64_t ree_job_length : 15;
+		uint64_t reserved_447_447 : 1;
+		uint64_t ree_job_subset_id_0 : 16;
+		uint64_t ree_job_subset_id_1 : 16;
+		uint64_t ree_job_subset_id_2 : 16;
+		uint64_t ree_job_subset_id_3 : 16;
+	} cn98xx;
+};
+
+int __roc_api roc_ree_dev_init(struct roc_ree_vf *vf);
+int __roc_api roc_ree_dev_fini(struct roc_ree_vf *vf);
+int __roc_api roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues);
+int __roc_api roc_ree_queues_detach(struct roc_ree_vf *vf);
+int __roc_api roc_ree_msix_offsets_get(struct roc_ree_vf *vf);
+int __roc_api roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri,
+				uint32_t size);
+int __roc_api roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg,
+				  uint64_t *val);
+int __roc_api roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg,
+				   uint64_t val);
+int __roc_api roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db,
+				  uint32_t rule_db_len, char *rule_dbi,
+				  uint32_t rule_dbi_len);
+int __roc_api roc_ree_rule_db_len_get(struct roc_ree_vf *vf,
+				      uint32_t *rule_db_len,
+				      uint32_t *rule_dbi_len);
+int __roc_api roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+				   uint32_t rule_db_len, const char *rule_dbi,
+				   uint32_t rule_dbi_len);
+uintptr_t __roc_api roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id);
+void __roc_api roc_ree_err_intr_unregister(struct roc_ree_vf *vf);
+int __roc_api roc_ree_err_intr_register(struct roc_ree_vf *vf);
+int __roc_api roc_ree_iq_enable(struct roc_ree_vf *vf,
+				const struct roc_ree_qp *qp, uint8_t pri,
+				uint32_t size_div128);
+void __roc_api roc_ree_iq_disable(struct roc_ree_qp *qp);
+
+#endif /* _ROC_REE_H_ */
diff --git a/drivers/common/cnxk/roc_ree_priv.h b/drivers/common/cnxk/roc_ree_priv.h
new file mode 100644
index 0000000000..c39f7cf986
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree_priv.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_PRIV_H_
+#define _ROC_REE_PRIV_H_
+
+struct ree {
+	struct dev dev;
+} __plt_cache_aligned;
+
+static inline struct ree *
+roc_ree_to_ree_priv(struct roc_ree_vf *roc_ree)
+{
+	return (struct ree *)&roc_ree->reserved[0];
+}
+
+#endif /* _ROC_REE_PRIV_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 4/5] common/cnxk: link REE support to ROC files
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
                       ` (3 preceding siblings ...)
  2021-11-29 19:47     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
@ 2021-11-29 19:47     ` lironh
  2021-11-29 19:47     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
  5 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:47 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add references to REE files from ROC files

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/meson.build     |  1 +
 drivers/common/cnxk/roc_api.h       |  4 ++++
 drivers/common/cnxk/roc_constants.h |  2 ++
 drivers/common/cnxk/roc_platform.c  |  1 +
 drivers/common/cnxk/roc_platform.h  |  2 ++
 drivers/common/cnxk/roc_priv.h      |  3 +++
 drivers/common/cnxk/version.map     | 18 +++++++++++++++++-
 7 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4928f7e549..7e27b3cc0a 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -61,6 +61,7 @@ sources = files(
         'roc_tim.c',
         'roc_tim_irq.c',
         'roc_utils.c',
+        'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index e7aaa07563..1b46c21f7f 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -37,6 +37,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -90,6 +91,9 @@
 /* DPI */
 #include "roc_dpi.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
index ac7335061c..5f78823642 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY	      0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF     0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF     0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 61d4781209..85aa6dcebc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)                                                  \
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)	plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)	plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)	plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)	plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)                                               \
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 782b90cf8d..122d411fe7 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,4 +44,7 @@
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..5a03b91784 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_nix;
 	cnxk_logtype_npa;
 	cnxk_logtype_npc;
+	cnxk_logtype_ree;
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
@@ -347,6 +348,21 @@ INTERNAL {
 	roc_tim_lf_enable;
 	roc_tim_lf_free;
 	roc_se_ctx_swap;
-
+	roc_ree_af_reg_read;
+	roc_ree_af_reg_write;
+	roc_ree_config_lf;
+	roc_ree_dev_fini;
+	roc_ree_dev_init;
+	roc_ree_err_intr_register;
+	roc_ree_err_intr_unregister;
+	roc_ree_iq_disable;
+	roc_ree_iq_enable;
+	roc_ree_msix_offsets_get;
+	roc_ree_qp_get_base;
+	roc_ree_queues_attach;
+	roc_ree_queues_detach;
+	roc_ree_rule_db_get;
+	roc_ree_rule_db_len_get;
+	roc_ree_rule_db_prog;
 	local: *;
 };
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
                       ` (4 preceding siblings ...)
  2021-11-29 19:47     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
@ 2021-11-29 19:47     ` lironh
  5 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:47 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

update driver to use the REE cnxk code
replace octeontx2/otx2 with cn9k

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 doc/guides/platform/octeontx2.rst             |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 doc/guides/rel_notes/release_20_11.rst        |   2 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 ++++++++----------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 -----
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 --------
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ---------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 --
 20 files changed, 269 insertions(+), 1205 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..5f45b35c51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst
 RegEx Drivers
 -------------
 
-Marvell OCTEON TX2 regex
+Marvell OCTEON CN9K regex
 M: Liron Himi <lironh@marvell.com>
-F: drivers/regex/octeontx2/
-F: doc/guides/regexdevs/octeontx2.rst
-F: doc/guides/regexdevs/features/octeontx2.ini
+F: drivers/regex/cn9k/
+F: doc/guides/regexdevs/cn9k.rst
+F: doc/guides/regexdevs/features/cn9k.ini
 
 Mellanox mlx5
 M: Ori Kam <orika@nvidia.com>
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 88995cc70c..5213df3ccd 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
 #. **Dmadev Driver**
    See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
 
+#. **Regex Device Driver**
+   See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 3a3d28571c..5ab43abbdd 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -155,9 +155,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
 #. **Crypto Device Driver**
    See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
-#. **Regex Device Driver**
-   See :doc:`../regexdevs/octeontx2` for REE regex device driver information.
-
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst
similarity index 69%
rename from doc/guides/regexdevs/octeontx2.rst
rename to doc/guides/regexdevs/cn9k.rst
index b39d457d60..c23c295b93 100644
--- a/doc/guides/regexdevs/octeontx2.rst
+++ b/doc/guides/regexdevs/cn9k.rst
@@ -1,20 +1,20 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
     Copyright(c) 2020 Marvell International Ltd.
 
-OCTEON TX2 REE Regexdev Driver
+CN9K REE Regexdev Driver
 ==============================
 
-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode
-regexdev driver support for the inbuilt regex device found in the **Marvell OCTEON TX2**
+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode
+regexdev driver support for the inbuilt regex device found in the **Marvell CN9K**
 SoC family.
 
-More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+More information about CN9K SoC can be found at `Marvell Official Website
 <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
 
 Features
 --------
 
-Features of the OCTEON TX2 REE PMD are:
+Features of the CN9K REE PMD are:
 
 - 36 queues
 - Up to 254 matches for each regex operation
@@ -22,12 +22,12 @@ Features of the OCTEON TX2 REE PMD are:
 Prerequisites and Compilation procedure
 ---------------------------------------
 
-   See :doc:`../platform/octeontx2` for setup information.
+   See :doc:`../platform/cnxk` for setup information.
 
 Device Setup
 ------------
 
-The OCTEON TX2 REE devices will need to be bound to a user-space IO driver
+The CN9K REE devices will need to be bound to a user-space IO driver
 for use. The script ``dpdk-devbind.py`` script included with DPDK can be
 used to view the state of the devices and to bind them to a suitable
 DPDK-supported kernel driver. When querying the status of the devices,
@@ -38,12 +38,12 @@ those devices alone.
 Debugging Options
 -----------------
 
-.. _table_octeontx2_regex_debug_options:
+.. _table_cn9k_regex_debug_options:
 
-.. table:: OCTEON TX2 regex device debug options
+.. table:: CN9K regex device debug options
 
    +---+------------+-------------------------------------------------------+
    | # | Component  | EAL log command                                       |
    +===+============+=======================================================+
-   | 1 | REE        | --log-level='pmd\.regex\.octeontx2,8'                 |
+   | 1 | REE        | --log-level='pmd\.regex\.cn9k,8'                      |
    +---+------------+-------------------------------------------------------+
diff --git a/doc/guides/regexdevs/features/octeontx2.ini b/doc/guides/regexdevs/features/cn9k.ini
similarity index 80%
rename from doc/guides/regexdevs/features/octeontx2.ini
rename to doc/guides/regexdevs/features/cn9k.ini
index c9b421a16d..b029af8ac2 100644
--- a/doc/guides/regexdevs/features/octeontx2.ini
+++ b/doc/guides/regexdevs/features/cn9k.ini
@@ -1,5 +1,5 @@
 ;
-; Supported features of the 'octeontx2' regex driver.
+; Supported features of the 'cn9k' regex driver.
 ;
 ; Refer to default.ini for the full list of available driver features.
 ;
diff --git a/doc/guides/regexdevs/index.rst b/doc/guides/regexdevs/index.rst
index b1abc826bd..11a33fc09e 100644
--- a/doc/guides/regexdevs/index.rst
+++ b/doc/guides/regexdevs/index.rst
@@ -13,4 +13,4 @@ which can be used from an application through RegEx API.
 
    features_overview
    mlx5
-   octeontx2
+   cn9k
diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index 90cc3ed680..d6d40c31df 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -290,7 +290,7 @@ New Features
 
   Added a new PMD driver for the hardware regex offload block for OCTEON TX2 SoC.
 
-  See the :doc:`../regexdevs/octeontx2` for more details.
+  See ``regexdevs/octeontx2`` for more details.
 
 * **Updated Software Eventdev driver.**
 
diff --git a/drivers/regex/octeontx2/otx2_regexdev.c b/drivers/regex/cn9k/cn9k_regexdev.c
similarity index 61%
rename from drivers/regex/octeontx2/otx2_regexdev.c
rename to drivers/regex/cn9k/cn9k_regexdev.c
index b6e55853e9..32d20c1be8 100644
--- a/drivers/regex/octeontx2/otx2_regexdev.c
+++ b/drivers/regex/cn9k/cn9k_regexdev.c
@@ -13,12 +13,8 @@
 
 
 /* REE common headers */
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 
 /* HW matches are at offset 0x80 from RES_PTR_ADDR
@@ -35,9 +31,6 @@
 #define REE_MAX_RULES_PER_GROUP 0xFFFF
 #define REE_MAX_GROUPS 0xFFFF
 
-/* This is temporarily here */
-#define REE0_PF	19
-#define REE1_PF	20
 
 #define REE_RULE_DB_VERSION	2
 #define REE_RULE_DB_REVISION	0
@@ -58,32 +51,32 @@ struct ree_rule_db {
 static void
 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
 {
-	snprintf(name, size, "otx2_ree_lf_mem_%u:%u", dev_id, qp_id);
+	snprintf(name, size, "cn9k_ree_lf_mem_%u:%u", dev_id, qp_id);
 }
 
-static struct otx2_ree_qp *
+static struct roc_ree_qp *
 ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
-	struct otx2_ree_vf *vf = &data->vf;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct rte_memzone *lf_mem;
 	uint32_t len, iq_len, size_div2;
 	char name[RTE_MEMZONE_NAMESIZE];
 	uint64_t used_len, iova;
-	struct otx2_ree_qp *qp;
+	struct roc_ree_qp *qp;
 	uint8_t *va;
 	int ret;
 
 	/* Allocate queue pair */
-	qp = rte_zmalloc("OCTEON TX2 Regex PMD Queue Pair", sizeof(*qp),
-				OTX2_ALIGN);
+	qp = rte_zmalloc("CN9K Regex PMD Queue Pair", sizeof(*qp),
+				ROC_ALIGN);
 	if (qp == NULL) {
-		otx2_err("Could not allocate queue pair");
+		cn9k_err("Could not allocate queue pair");
 		return NULL;
 	}
 
-	iq_len = OTX2_REE_IQ_LEN;
+	iq_len = REE_IQ_LEN;
 
 	/*
 	 * Queue size must be in units of 128B 2 * REE_INST_S (which is 64B),
@@ -93,13 +86,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	size_div2 = iq_len >> 1;
 
 	/* For pending queue */
-	len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 
 	/* So that instruction queues start as pg size aligned */
 	len = RTE_ALIGN(len, pg_sz);
 
 	/* For instruction queues */
-	len += OTX2_REE_IQ_LEN * sizeof(union otx2_ree_inst);
+	len += REE_IQ_LEN * sizeof(union roc_ree_inst);
 
 	/* Waste after instruction queues */
 	len = RTE_ALIGN(len, pg_sz);
@@ -107,11 +100,11 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp_id);
 
-	lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
+	lf_mem = rte_memzone_reserve_aligned(name, len, rte_socket_id(),
 			RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
 			RTE_CACHE_LINE_SIZE);
 	if (lf_mem == NULL) {
-		otx2_err("Could not allocate reserved memzone");
+		cn9k_err("Could not allocate reserved memzone");
 		goto qp_free;
 	}
 
@@ -121,24 +114,24 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	memset(va, 0, len);
 
 	/* Initialize pending queue */
-	qp->pend_q.rid_queue = (struct otx2_ree_rid *)va;
+	qp->pend_q.rid_queue = (struct roc_ree_rid *)va;
 	qp->pend_q.enq_tail = 0;
 	qp->pend_q.deq_head = 0;
 	qp->pend_q.pending_count = 0;
 
-	used_len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	used_len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 	used_len = RTE_ALIGN(used_len, pg_sz);
 	iova += used_len;
 
 	qp->iq_dma_addr = iova;
 	qp->id = qp_id;
-	qp->base = OTX2_REE_LF_BAR2(vf, qp_id);
-	qp->otx2_regexdev_jobid = 0;
+	qp->base = roc_ree_qp_get_base(vf, qp_id);
+	qp->roc_regexdev_jobid = 0;
 	qp->write_offset = 0;
 
-	ret = otx2_ree_iq_enable(dev, qp, OTX2_REE_QUEUE_HI_PRIO, size_div2);
+	ret = roc_ree_iq_enable(vf, qp, REE_QUEUE_HI_PRIO, size_div2);
 	if (ret) {
-		otx2_err("Could not enable instruction queue");
+		cn9k_err("Could not enable instruction queue");
 		goto qp_free;
 	}
 
@@ -150,13 +143,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 }
 
 static int
-ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
+ree_qp_destroy(const struct rte_regexdev *dev, struct roc_ree_qp *qp)
 {
 	const struct rte_memzone *lf_mem;
 	char name[RTE_MEMZONE_NAMESIZE];
 	int ret;
 
-	otx2_ree_iq_disable(qp);
+	roc_ree_iq_disable(qp);
 
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp->id);
@@ -175,8 +168,8 @@ ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
 static int
 ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
 	int ret;
 
 	ree_func_trace("Queue=%d", qp_id);
@@ -186,7 +179,7 @@ ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 
 	ret = ree_qp_destroy(dev, qp);
 	if (ret) {
-		otx2_err("Could not destroy queue pair %d", qp_id);
+		cn9k_err("Could not destroy queue pair %d", qp_id);
 		return ret;
 	}
 
@@ -200,12 +193,12 @@ ree_dev_register(const char *name)
 {
 	struct rte_regexdev *dev;
 
-	otx2_ree_dbg("Creating regexdev %s\n", name);
+	cn9k_ree_dbg("Creating regexdev %s\n", name);
 
 	/* allocate device structure */
 	dev = rte_regexdev_register(name);
 	if (dev == NULL) {
-		otx2_err("Failed to allocate regex device for %s", name);
+		cn9k_err("Failed to allocate regex device for %s", name);
 		return NULL;
 	}
 
@@ -213,12 +206,12 @@ ree_dev_register(const char *name)
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		dev->data->dev_private =
 				rte_zmalloc_socket("regexdev device private",
-						sizeof(struct otx2_ree_data),
+						sizeof(struct cn9k_ree_data),
 						RTE_CACHE_LINE_SIZE,
 						rte_socket_id());
 
 		if (dev->data->dev_private == NULL) {
-			otx2_err("Cannot allocate memory for dev %s private data",
+			cn9k_err("Cannot allocate memory for dev %s private data",
 					name);
 
 			rte_regexdev_unregister(dev);
@@ -232,7 +225,7 @@ ree_dev_register(const char *name)
 static int
 ree_dev_unregister(struct rte_regexdev *dev)
 {
-	otx2_ree_dbg("Closing regex device %s", dev->device->name);
+	cn9k_ree_dbg("Closing regex device %s", dev->device->name);
 
 	/* free regex device */
 	rte_regexdev_unregister(dev);
@@ -246,8 +239,8 @@ ree_dev_unregister(struct rte_regexdev *dev)
 static int
 ree_dev_fini(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct rte_pci_device *pci_dev;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	int i, ret;
 
 	ree_func_trace();
@@ -258,9 +251,9 @@ ree_dev_fini(struct rte_regexdev *dev)
 			return ret;
 	}
 
-	ret = otx2_ree_queues_detach(dev);
+	ret = roc_ree_queues_detach(vf);
 	if (ret)
-		otx2_err("Could not detach queues");
+		cn9k_err("Could not detach queues");
 
 	/* TEMP : should be in lib */
 	if (data->queue_pairs)
@@ -268,33 +261,32 @@ ree_dev_fini(struct rte_regexdev *dev)
 	if (data->rules)
 		rte_free(data->rules);
 
-	pci_dev = container_of(dev->device, struct rte_pci_device, device);
-	otx2_dev_fini(pci_dev, &(data->vf.otx2_dev));
+	roc_ree_dev_fini(vf);
 
 	ret = ree_dev_unregister(dev);
 	if (ret)
-		otx2_err("Could not destroy PMD");
+		cn9k_err("Could not destroy PMD");
 
 	return ret;
 }
 
 static inline int
-ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
-		 struct otx2_ree_pending_queue *pend_q)
+ree_enqueue(struct roc_ree_qp *qp, struct rte_regex_ops *op,
+		 struct roc_ree_pending_queue *pend_q)
 {
-	union otx2_ree_inst inst;
-	union otx2_ree_res *res;
+	union roc_ree_inst inst;
+	union ree_res *res;
 	uint32_t offset;
 
-	if (unlikely(pend_q->pending_count >= OTX2_REE_DEFAULT_CMD_QLEN)) {
-		otx2_err("Pending count %" PRIu64 " is greater than Q size %d",
-		pend_q->pending_count, OTX2_REE_DEFAULT_CMD_QLEN);
+	if (unlikely(pend_q->pending_count >= REE_DEFAULT_CMD_QLEN)) {
+		cn9k_err("Pending count %" PRIu64 " is greater than Q size %d",
+		pend_q->pending_count, REE_DEFAULT_CMD_QLEN);
 		return -EAGAIN;
 	}
-	if (unlikely(op->mbuf->data_len > OTX2_REE_MAX_PAYLOAD_SIZE ||
+	if (unlikely(op->mbuf->data_len > REE_MAX_PAYLOAD_SIZE ||
 			op->mbuf->data_len == 0)) {
-		otx2_err("Packet length %d is greater than MAX payload %d",
-				op->mbuf->data_len, OTX2_REE_MAX_PAYLOAD_SIZE);
+		cn9k_err("Packet length %d is greater than MAX payload %d",
+				op->mbuf->data_len, REE_MAX_PAYLOAD_SIZE);
 		return -EAGAIN;
 	}
 
@@ -324,7 +316,7 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 		inst.cn98xx.ree_job_ctrl = (0x1 << 8);
 	else
 		inst.cn98xx.ree_job_ctrl = 0;
-	inst.cn98xx.ree_job_id = qp->otx2_regexdev_jobid;
+	inst.cn98xx.ree_job_id = qp->roc_regexdev_jobid;
 	/* W 7 */
 	inst.cn98xx.ree_job_subset_id_0 = op->group_id0;
 	if (op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F)
@@ -348,33 +340,33 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 	pend_q->rid_queue[pend_q->enq_tail].user_id = op->user_id;
 
 	/* Mark result as not done */
-	res = (union otx2_ree_res *)(op);
+	res = (union ree_res *)(op);
 	res->s.done = 0;
 	res->s.ree_err = 0;
 
 	/* We will use soft queue length here to limit requests */
-	REE_MOD_INC(pend_q->enq_tail, OTX2_REE_DEFAULT_CMD_QLEN);
+	REE_MOD_INC(pend_q->enq_tail, REE_DEFAULT_CMD_QLEN);
 	pend_q->pending_count += 1;
-	REE_MOD_INC(qp->otx2_regexdev_jobid, 0xFFFFFF);
-	REE_MOD_INC(qp->write_offset, OTX2_REE_IQ_LEN);
+	REE_MOD_INC(qp->roc_regexdev_jobid, 0xFFFFFF);
+	REE_MOD_INC(qp->write_offset, REE_IQ_LEN);
 
 	return 0;
 }
 
 static uint16_t
-otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	uint16_t nb_allowed, count = 0;
 	struct rte_regex_ops *op;
 	int ret;
 
 	pend_q = &qp->pend_q;
 
-	nb_allowed = OTX2_REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
+	nb_allowed = REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
 	if (nb_ops > nb_allowed)
 		nb_ops = nb_allowed;
 
@@ -392,7 +384,7 @@ otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 	rte_io_wmb();
 
 	/* Update Doorbell */
-	otx2_write64(count, qp->base + OTX2_REE_LF_DOORBELL);
+	plt_write64(count, qp->base + REE_LF_DOORBELL);
 
 	return count;
 }
@@ -422,15 +414,15 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 	}
 
 	if (unlikely(ree_res_status != REE_TYPE_RESULT_DESC)) {
-		if (ree_res_status & OTX2_REE_STATUS_PMI_SOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_SOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_PMI_EOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_EOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_ML_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_ML_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F;
-		if (ree_res_status & OTX2_REE_STATUS_MM_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MM_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F;
-		if (ree_res_status & OTX2_REE_STATUS_MP_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MP_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F;
 	}
 	if (ops->nb_matches > 0) {
@@ -439,22 +431,22 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 			ops->nb_matches : REE_NUM_MATCHES_ALIGN);
 		match = (uint64_t)ops + REE_MATCH_OFFSET;
 		match += (ops->nb_matches - off) *
-			sizeof(union otx2_ree_match);
+			sizeof(union ree_match);
 		memcpy((void *)ops->matches, (void *)match,
-			off * sizeof(union otx2_ree_match));
+			off * sizeof(union ree_match));
 	}
 }
 
 static uint16_t
-otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	int i, nb_pending, nb_completed = 0;
 	volatile struct ree_res_s_98 *res;
-	struct otx2_ree_rid *rid;
+	struct roc_ree_rid *rid;
 
 	pend_q = &qp->pend_q;
 
@@ -474,7 +466,7 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		ops[i] = (struct rte_regex_ops *)(rid->rid);
 		ops[i]->user_id = rid->user_id;
 
-		REE_MOD_INC(pend_q->deq_head, OTX2_REE_DEFAULT_CMD_QLEN);
+		REE_MOD_INC(pend_q->deq_head, REE_DEFAULT_CMD_QLEN);
 		pend_q->pending_count -= 1;
 	}
 
@@ -487,10 +479,10 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 }
 
 static int
-otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
+cn9k_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 
 	ree_func_trace();
 
@@ -502,7 +494,7 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 
 	info->max_queue_pairs = vf->max_queues;
 	info->max_matches = vf->max_matches;
-	info->max_payload_size = OTX2_REE_MAX_PAYLOAD_SIZE;
+	info->max_payload_size = REE_MAX_PAYLOAD_SIZE;
 	info->max_rules_per_group = data->max_rules_per_group;
 	info->max_groups = data->max_groups;
 	info->regexdev_capa = data->regexdev_capa;
@@ -512,11 +504,11 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 }
 
 static int
-otx2_ree_dev_config(struct rte_regexdev *dev,
+cn9k_ree_dev_config(struct rte_regexdev *dev,
 		    const struct rte_regexdev_config *cfg)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *rule_db;
 	uint32_t rule_db_len;
 	int ret;
@@ -524,29 +516,29 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	ree_func_trace();
 
 	if (cfg->nb_queue_pairs > vf->max_queues) {
-		otx2_err("Invalid number of queue pairs requested");
+		cn9k_err("Invalid number of queue pairs requested");
 		return -EINVAL;
 	}
 
 	if (cfg->nb_max_matches != vf->max_matches) {
-		otx2_err("Invalid number of max matches requested");
+		cn9k_err("Invalid number of max matches requested");
 		return -EINVAL;
 	}
 
 	if (cfg->dev_cfg_flags != 0) {
-		otx2_err("Invalid device configuration flags requested");
+		cn9k_err("Invalid device configuration flags requested");
 		return -EINVAL;
 	}
 
 	/* Unregister error interrupts */
 	if (vf->err_intr_registered)
-		otx2_ree_err_intr_unregister(dev);
+		roc_ree_err_intr_unregister(vf);
 
 	/* Detach queues */
 	if (vf->nb_queues) {
-		ret = otx2_ree_queues_detach(dev);
+		ret = roc_ree_queues_detach(vf);
 		if (ret) {
-			otx2_err("Could not detach REE queues");
+			cn9k_err("Could not detach REE queues");
 			return ret;
 		}
 	}
@@ -559,7 +551,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 
 		if (data->queue_pairs == NULL) {
 			data->nb_queue_pairs = 0;
-			otx2_err("Failed to get memory for qp meta data, nb_queues %u",
+			cn9k_err("Failed to get memory for qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -579,7 +571,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 		qp = rte_realloc(qp, sizeof(qp[0]) * cfg->nb_queue_pairs,
 				RTE_CACHE_LINE_SIZE);
 		if (qp == NULL) {
-			otx2_err("Failed to realloc qp meta data, nb_queues %u",
+			cn9k_err("Failed to realloc qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -594,52 +586,52 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	data->nb_queue_pairs = cfg->nb_queue_pairs;
 
 	/* Attach queues */
-	otx2_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
-	ret = otx2_ree_queues_attach(dev, cfg->nb_queue_pairs);
+	cn9k_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
+	ret = roc_ree_queues_attach(vf, cfg->nb_queue_pairs);
 	if (ret) {
-		otx2_err("Could not attach queues");
+		cn9k_err("Could not attach queues");
 		return -ENODEV;
 	}
 
-	ret = otx2_ree_msix_offsets_get(dev);
+	ret = roc_ree_msix_offsets_get(vf);
 	if (ret) {
-		otx2_err("Could not get MSI-X offsets");
+		cn9k_err("Could not get MSI-X offsets");
 		goto queues_detach;
 	}
 
 	if (cfg->rule_db && cfg->rule_db_len) {
-		otx2_ree_dbg("rule_db length %d", cfg->rule_db_len);
+		cn9k_ree_dbg("rule_db length %d", cfg->rule_db_len);
 		rule_db = (const struct ree_rule_db *)cfg->rule_db;
 		rule_db_len = rule_db->number_of_entries *
 				sizeof(struct ree_rule_db_entry);
-		otx2_ree_dbg("rule_db number of entries %d",
+		cn9k_ree_dbg("rule_db number of entries %d",
 				rule_db->number_of_entries);
 		if (rule_db_len > cfg->rule_db_len) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			ret = -EINVAL;
 			goto queues_detach;
 		}
-		ret = otx2_ree_rule_db_prog(dev, (const char *)rule_db->entries,
-				rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+		ret = roc_ree_rule_db_prog(vf, (const char *)rule_db->entries,
+				rule_db_len, NULL, REE_NON_INC_PROG);
 		if (ret) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			goto queues_detach;
 		}
 	}
 
-	dev->enqueue = otx2_ree_enqueue_burst;
-	dev->dequeue = otx2_ree_dequeue_burst;
+	dev->enqueue = cn9k_ree_enqueue_burst;
+	dev->dequeue = cn9k_ree_dequeue_burst;
 
 	rte_mb();
 	return 0;
 
 queues_detach:
-	otx2_ree_queues_detach(dev);
+	roc_ree_queues_detach(vf);
 	return ret;
 }
 
 static int
-otx2_ree_stop(struct rte_regexdev *dev)
+cn9k_ree_stop(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 
@@ -648,18 +640,20 @@ otx2_ree_stop(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_start(struct rte_regexdev *dev)
+cn9k_ree_start(struct rte_regexdev *dev)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	uint32_t rule_db_len = 0;
 	int ret;
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, NULL);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, NULL);
 	if (ret)
 		return ret;
 	if (rule_db_len == 0) {
-		otx2_err("Rule db not programmed");
+		cn9k_err("Rule db not programmed");
 		return -EFAULT;
 	}
 
@@ -667,56 +661,55 @@ otx2_ree_start(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_close(struct rte_regexdev *dev)
+cn9k_ree_close(struct rte_regexdev *dev)
 {
 	return ree_dev_fini(dev);
 }
 
 static int
-otx2_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
 		const struct rte_regexdev_qp_conf *qp_conf)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp;
 
 	ree_func_trace("Queue=%d", qp_id);
 
 	if (data->queue_pairs[qp_id] != NULL)
 		ree_queue_pair_release(dev, qp_id);
 
-	if (qp_conf->nb_desc > OTX2_REE_DEFAULT_CMD_QLEN) {
-		otx2_err("Could not setup queue pair for %u descriptors",
+	if (qp_conf->nb_desc > REE_DEFAULT_CMD_QLEN) {
+		cn9k_err("Could not setup queue pair for %u descriptors",
 				qp_conf->nb_desc);
 		return -EINVAL;
 	}
 	if (qp_conf->qp_conf_flags != 0) {
-		otx2_err("Could not setup queue pair with configuration flags 0x%x",
+		cn9k_err("Could not setup queue pair with configuration flags 0x%x",
 				qp_conf->qp_conf_flags);
 		return -EINVAL;
 	}
 
 	qp = ree_qp_create(dev, qp_id);
 	if (qp == NULL) {
-		otx2_err("Could not create queue pair %d", qp_id);
+		cn9k_err("Could not create queue pair %d", qp_id);
 		return -ENOMEM;
 	}
-	qp->cb = qp_conf->cb;
 	data->queue_pairs[qp_id] = qp;
 
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_compile_activate(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_activate(struct rte_regexdev *dev)
 {
-	return otx2_ree_rule_db_compile_prog(dev);
+	return cn9k_ree_rule_db_compile_prog(dev);
 }
 
 static int
-otx2_ree_rule_db_update(struct rte_regexdev *dev,
+cn9k_ree_rule_db_update(struct rte_regexdev *dev,
 		const struct rte_regexdev_rule *rules, uint16_t nb_rules)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	struct rte_regexdev_rule *old_ptr;
 	uint32_t i, sum_nb_rules;
 
@@ -770,10 +763,11 @@ otx2_ree_rule_db_update(struct rte_regexdev *dev,
 }
 
 static int
-otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
+cn9k_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 		uint32_t rule_db_len)
 {
-
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *ree_rule_db;
 	uint32_t ree_rule_db_len;
 	int ret;
@@ -784,21 +778,23 @@ otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 	ree_rule_db_len = ree_rule_db->number_of_entries *
 			sizeof(struct ree_rule_db_entry);
 	if (ree_rule_db_len > rule_db_len) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -EINVAL;
 	}
-	ret = otx2_ree_rule_db_prog(dev, (const char *)ree_rule_db->entries,
-			ree_rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+	ret = roc_ree_rule_db_prog(vf, (const char *)ree_rule_db->entries,
+			ree_rule_db_len, NULL, REE_NON_INC_PROG);
 	if (ret) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -ENOSPC;
 	}
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
+cn9k_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	struct ree_rule_db *ree_rule_db;
 	uint32_t rule_dbi_len;
 	uint32_t rule_db_len;
@@ -806,7 +802,7 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret)
 		return ret;
 
@@ -816,10 +812,10 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	}
 
 	ree_rule_db = (struct ree_rule_db *)rule_db;
-	ret = otx2_ree_rule_db_get(dev, (char *)ree_rule_db->entries,
+	ret = roc_ree_rule_db_get(vf, (char *)ree_rule_db->entries,
 			rule_db_len, NULL, 0);
 	if (ret) {
-		otx2_err("Could not export rule db");
+		cn9k_err("Could not export rule db");
 		return -EFAULT;
 	}
 	ree_rule_db->number_of_entries =
@@ -830,55 +826,44 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	return 0;
 }
 
-static int
-ree_get_blkaddr(struct otx2_dev *dev)
-{
-	int pf;
-
-	pf = otx2_get_pf(dev->pf_func);
-	if (pf == REE0_PF)
-		return RVU_BLOCK_ADDR_REE0;
-	else if (pf == REE1_PF)
-		return RVU_BLOCK_ADDR_REE1;
-	else
-		return 0;
-}
-
-static struct rte_regexdev_ops otx2_ree_ops = {
-		.dev_info_get = otx2_ree_dev_info_get,
-		.dev_configure = otx2_ree_dev_config,
-		.dev_qp_setup = otx2_ree_queue_pair_setup,
-		.dev_start = otx2_ree_start,
-		.dev_stop = otx2_ree_stop,
-		.dev_close = otx2_ree_close,
-		.dev_attr_get = NULL,
-		.dev_attr_set = NULL,
-		.dev_rule_db_update = otx2_ree_rule_db_update,
-		.dev_rule_db_compile_activate =
-				otx2_ree_rule_db_compile_activate,
-		.dev_db_import = otx2_ree_rule_db_import,
-		.dev_db_export = otx2_ree_rule_db_export,
-		.dev_xstats_names_get = NULL,
-		.dev_xstats_get = NULL,
-		.dev_xstats_by_name_get = NULL,
-		.dev_xstats_reset = NULL,
-		.dev_selftest = NULL,
-		.dev_dump = NULL,
+static struct rte_regexdev_ops cn9k_ree_ops = {
+	.dev_info_get = cn9k_ree_dev_info_get,
+	.dev_configure = cn9k_ree_dev_config,
+	.dev_qp_setup = cn9k_ree_queue_pair_setup,
+	.dev_start = cn9k_ree_start,
+	.dev_stop = cn9k_ree_stop,
+	.dev_close = cn9k_ree_close,
+	.dev_attr_get = NULL,
+	.dev_attr_set = NULL,
+	.dev_rule_db_update = cn9k_ree_rule_db_update,
+	.dev_rule_db_compile_activate =
+			cn9k_ree_rule_db_compile_activate,
+	.dev_db_import = cn9k_ree_rule_db_import,
+	.dev_db_export = cn9k_ree_rule_db_export,
+	.dev_xstats_names_get = NULL,
+	.dev_xstats_get = NULL,
+	.dev_xstats_by_name_get = NULL,
+	.dev_xstats_reset = NULL,
+	.dev_selftest = NULL,
+	.dev_dump = NULL,
 };
 
 static int
-otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+cn9k_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		   struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
-	struct otx2_ree_data *data;
-	struct otx2_dev *otx2_dev;
+	struct cn9k_ree_data *data;
 	struct rte_regexdev *dev;
-	uint8_t max_matches = 0;
-	struct otx2_ree_vf *vf;
-	uint16_t nb_queues = 0;
+	struct roc_ree_vf *vf;
 	int ret;
 
+	ret = roc_plt_init();
+	if (ret < 0) {
+		plt_err("Failed to initialize platform model");
+		return ret;
+	}
+
 	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
 
 	dev = ree_dev_register(name);
@@ -887,63 +872,19 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		goto exit;
 	}
 
-	dev->dev_ops = &otx2_ree_ops;
+	dev->dev_ops = &cn9k_ree_ops;
 	dev->device = &pci_dev->device;
 
 	/* Get private data space allocated */
 	data = dev->data->dev_private;
 	vf = &data->vf;
-
-	otx2_dev = &vf->otx2_dev;
-
-	/* Initialize the base otx2_dev object */
-	ret = otx2_dev_init(pci_dev, otx2_dev);
+	vf->pci_dev = pci_dev;
+	ret = roc_ree_dev_init(vf);
 	if (ret) {
-		otx2_err("Could not initialize otx2_dev");
+		plt_err("Failed to initialize roc cpt rc=%d", ret);
 		goto dev_unregister;
 	}
-	/* Get REE block address */
-	vf->block_address = ree_get_blkaddr(otx2_dev);
-	if (!vf->block_address) {
-		otx2_err("Could not determine block PF number");
-		goto otx2_dev_fini;
-	}
-
-	/* Get number of queues available on the device */
-	ret = otx2_ree_available_queues_get(dev, &nb_queues);
-	if (ret) {
-		otx2_err("Could not determine the number of queues available");
-		goto otx2_dev_fini;
-	}
-
-	/* Don't exceed the limits set per VF */
-	nb_queues = RTE_MIN(nb_queues, OTX2_REE_MAX_QUEUES_PER_VF);
-
-	if (nb_queues == 0) {
-		otx2_err("No free queues available on the device");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_queues = nb_queues;
-
-	otx2_ree_dbg("Max queues supported by device: %d", vf->max_queues);
-
-	/* Get number of maximum matches supported on the device */
-	ret = otx2_ree_max_matches_get(dev, &max_matches);
-	if (ret) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-	/* Don't exceed the limits set per VF */
-	max_matches = RTE_MIN(max_matches, OTX2_REE_MAX_MATCHES_PER_VF);
-	if (max_matches == 0) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_matches = max_matches;
 
-	otx2_ree_dbg("Max matches supported by device: %d", vf->max_matches);
 	data->rule_flags = RTE_REGEX_PCRE_RULE_ALLOW_EMPTY_F |
 			RTE_REGEX_PCRE_RULE_ANCHORED_F;
 	data->regexdev_capa = 0;
@@ -954,18 +895,16 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	dev->state = RTE_REGEXDEV_READY;
 	return 0;
 
-otx2_dev_fini:
-	otx2_dev_fini(pci_dev, otx2_dev);
 dev_unregister:
 	ree_dev_unregister(dev);
 exit:
-	otx2_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
+	cn9k_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
 		    pci_dev->id.vendor_id, pci_dev->id.device_id);
 	return ret;
 }
 
 static int
-otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
+cn9k_ree_pci_remove(struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
 	struct rte_regexdev *dev = NULL;
@@ -986,20 +925,20 @@ otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
 static struct rte_pci_id pci_id_ree_table[] = {
 	{
 		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-				PCI_DEVID_OCTEONTX2_RVU_REE_PF)
+				PCI_DEVID_CNXK_RVU_REE_PF)
 	},
 	{
 		.vendor_id = 0,
 	}
 };
 
-static struct rte_pci_driver otx2_regexdev_pmd = {
+static struct rte_pci_driver cn9k_regexdev_pmd = {
 	.id_table = pci_id_ree_table,
 	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
-	.probe = otx2_ree_pci_probe,
-	.remove = otx2_ree_pci_remove,
+	.probe = cn9k_ree_pci_probe,
+	.remove = cn9k_ree_pci_remove,
 };
 
 
-RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_OCTEONTX2_PMD, otx2_regexdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_OCTEONTX2_PMD, pci_id_ree_table);
+RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_CN9K_PMD, cn9k_regexdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_CN9K_PMD, pci_id_ree_table);
diff --git a/drivers/regex/cn9k/cn9k_regexdev.h b/drivers/regex/cn9k/cn9k_regexdev.h
new file mode 100644
index 0000000000..c715502167
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_H_
+#define _CN9K_REGEXDEV_H_
+
+#include <rte_common.h>
+#include <rte_regexdev.h>
+
+#include "roc_api.h"
+
+#define cn9k_ree_dbg plt_ree_dbg
+#define cn9k_err plt_err
+
+#define ree_func_trace cn9k_ree_dbg
+
+/* Marvell CN9K Regex PMD device name */
+#define REGEXDEV_NAME_CN9K_PMD	regex_cn9k
+
+/**
+ * Device private data
+ */
+struct cn9k_ree_data {
+	uint32_t regexdev_capa;
+	uint64_t rule_flags;
+	/**< Feature flags exposes HW/SW features for the given device */
+	uint16_t max_rules_per_group;
+	/**< Maximum rules supported per subset by this device */
+	uint16_t max_groups;
+	/**< Maximum subset supported by this device */
+	void **queue_pairs;
+	/**< Array of pointers to queue pairs. */
+	uint16_t nb_queue_pairs;
+	/**< Number of device queue pairs. */
+	struct roc_ree_vf vf;
+	/**< vf data */
+	struct rte_regexdev_rule *rules;
+	/**< rules to be compiled */
+	uint16_t nb_rules;
+	/**< number of rules */
+} __rte_cache_aligned;
+
+#endif /* _CN9K_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.c b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
similarity index 86%
rename from drivers/regex/octeontx2/otx2_regexdev_compiler.c
rename to drivers/regex/cn9k/cn9k_regexdev_compiler.c
index 785459f741..935b8a53b4 100644
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.c
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
@@ -5,9 +5,8 @@
 #include <rte_malloc.h>
 #include <rte_regexdev.h>
 
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 #ifdef REE_COMPILER_SDK
 #include <rxp-compiler.h>
@@ -65,7 +64,7 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 			nb_rules*sizeof(struct rxp_rule_entry), 0);
 
 	if (ruleset.rules == NULL) {
-		otx2_err("Could not allocate memory for rule compilation\n");
+		cn9k_err("Could not allocate memory for rule compilation\n");
 		return -EFAULT;
 	}
 	if (rof_for_incremental_compile)
@@ -126,9 +125,10 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 }
 
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	char compiler_version[] = "20.5.2.eda0fa2";
 	char timestamp[] = "19700101_000001";
 	uint32_t rule_db_len, rule_dbi_len;
@@ -144,25 +144,25 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret != 0) {
-		otx2_err("Could not get rule db length");
+		cn9k_err("Could not get rule db length");
 		return ret;
 	}
 
 	if (rule_db_len > 0) {
-		otx2_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
+		cn9k_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
 				rule_db_len, rule_dbi_len);
 		rule_db = rte_malloc("ree_rule_db", rule_db_len, 0);
 		if (!rule_db) {
-			otx2_err("Could not allocate memory for rule db");
+			cn9k_err("Could not allocate memory for rule db");
 			return -EFAULT;
 		}
 
-		ret = otx2_ree_rule_db_get(dev, rule_db, rule_db_len,
+		ret = roc_ree_rule_db_get(vf, rule_db, rule_db_len,
 				(char *)rule_dbi, rule_dbi_len);
 		if (ret) {
-			otx2_err("Could not read rule db");
+			cn9k_err("Could not read rule db");
 			rte_free(rule_db);
 			return -EFAULT;
 		}
@@ -188,7 +188,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 		ret = ree_rule_db_compile(data->rules, data->nb_rules, &rof,
 				&rofi, &rof_inc, rofi_inc_p);
 		if (rofi->number_of_entries == 0) {
-			otx2_ree_dbg("No change to rule db");
+			cn9k_ree_dbg("No change to rule db");
 			ret = 0;
 			goto free_structs;
 		}
@@ -201,14 +201,14 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 				&rofi, NULL, NULL);
 	}
 	if (ret != 0) {
-		otx2_err("Could not compile rule db");
+		cn9k_err("Could not compile rule db");
 		goto free_structs;
 	}
 	rule_db_len = rof->number_of_entries * sizeof(struct rxp_rof_entry);
-	ret = otx2_ree_rule_db_prog(dev, (char *)rof->rof_entries, rule_db_len,
+	ret = roc_ree_rule_db_prog(vf, (char *)rof->rof_entries, rule_db_len,
 			rofi_rof_entries, rule_dbi_len);
 	if (ret)
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 
 free_structs:
 	rxp_free_structs(NULL, NULL, NULL, NULL, NULL, &rof, NULL, &rofi, NULL,
@@ -221,7 +221,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 }
 #else
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 	return -ENOTSUP;
diff --git a/drivers/regex/cn9k/cn9k_regexdev_compiler.h b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
new file mode 100644
index 0000000000..4c29a69ada
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_COMPILER_H_
+#define _CN9K_REGEXDEV_COMPILER_H_
+
+int
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev);
+
+#endif /* _CN9K_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/meson.build b/drivers/regex/cn9k/meson.build
similarity index 65%
rename from drivers/regex/octeontx2/meson.build
rename to drivers/regex/cn9k/meson.build
index 3f81add5bf..bb0504fba1 100644
--- a/drivers/regex/octeontx2/meson.build
+++ b/drivers/regex/cn9k/meson.build
@@ -16,12 +16,10 @@ if lib.found()
 endif
 
 sources = files(
-        'otx2_regexdev.c',
-        'otx2_regexdev_compiler.c',
-        'otx2_regexdev_hw_access.c',
-        'otx2_regexdev_mbox.c',
+        'cn9k_regexdev.c',
+        'cn9k_regexdev_compiler.c',
 )
 
-deps += ['bus_pci', 'common_octeontx2', 'regexdev']
+deps += ['bus_pci', 'regexdev']
+deps += ['common_cnxk', 'mempool_cnxk']
 
-includes += include_directories('../../common/octeontx2')
diff --git a/drivers/regex/octeontx2/version.map b/drivers/regex/cn9k/version.map
similarity index 100%
rename from drivers/regex/octeontx2/version.map
rename to drivers/regex/cn9k/version.map
diff --git a/drivers/regex/meson.build b/drivers/regex/meson.build
index 94222e55fe..7ad55af8ca 100644
--- a/drivers/regex/meson.build
+++ b/drivers/regex/meson.build
@@ -3,6 +3,6 @@
 
 drivers = [
         'mlx5',
-        'octeontx2',
+        'cn9k',
 ]
 std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc
diff --git a/drivers/regex/octeontx2/otx2_regexdev.h b/drivers/regex/octeontx2/otx2_regexdev.h
deleted file mode 100644
index d710535f5f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_H_
-#define _OTX2_REGEXDEV_H_
-
-#include <rte_common.h>
-#include <rte_regexdev.h>
-
-#include "otx2_dev.h"
-
-#define ree_func_trace otx2_ree_dbg
-
-/* Marvell OCTEON TX2 Regex PMD device name */
-#define REGEXDEV_NAME_OCTEONTX2_PMD	regex_octeontx2
-
-#define OTX2_REE_MAX_LFS		36
-#define OTX2_REE_MAX_QUEUES_PER_VF	36
-#define OTX2_REE_MAX_MATCHES_PER_VF	254
-
-#define OTX2_REE_MAX_PAYLOAD_SIZE	(1 << 14)
-
-#define OTX2_REE_NON_INC_PROG 0
-#define OTX2_REE_INC_PROG 1
-
-#define REE_MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
-
-
-/**
- * Device vf data
- */
-struct otx2_ree_vf {
-	struct otx2_dev otx2_dev;
-	/**< Base class */
-	uint16_t max_queues;
-	/**< Max queues supported */
-	uint8_t nb_queues;
-	/**< Number of regex queues attached */
-	uint16_t max_matches;
-	/**<  Max matches supported*/
-	uint16_t lf_msixoff[OTX2_REE_MAX_LFS];
-	/**< MSI-X offsets */
-	uint8_t block_address;
-	/**< REE Block Address */
-	uint8_t err_intr_registered:1;
-	/**< Are error interrupts registered? */
-};
-
-/**
- * Device private data
- */
-struct otx2_ree_data {
-	uint32_t regexdev_capa;
-	uint64_t rule_flags;
-	/**< Feature flags exposes HW/SW features for the given device */
-	uint16_t max_rules_per_group;
-	/**< Maximum rules supported per subset by this device */
-	uint16_t max_groups;
-	/**< Maximum subset supported by this device */
-	void **queue_pairs;
-	/**< Array of pointers to queue pairs. */
-	uint16_t nb_queue_pairs;
-	/**< Number of device queue pairs. */
-	struct otx2_ree_vf vf;
-	/**< vf data */
-	struct rte_regexdev_rule *rules;
-	/**< rules to be compiled */
-	uint16_t nb_rules;
-	/**< number of rules */
-} __rte_cache_aligned;
-
-struct otx2_ree_rid {
-	uintptr_t rid;
-	/** Request id of a ree operation */
-	uint64_t user_id;
-	/* Client data */
-	/**< IOVA address of the pattern to be matched. */
-};
-
-struct otx2_ree_pending_queue {
-	uint64_t pending_count;
-	/** Pending requests count */
-	struct otx2_ree_rid *rid_queue;
-	/** Array of pending requests */
-	uint16_t enq_tail;
-	/** Tail of queue to be used for enqueue */
-	uint16_t deq_head;
-	/** Head of queue to be used for dequeue */
-};
-
-struct otx2_ree_qp {
-	uint32_t id;
-	/**< Queue pair id */
-	uintptr_t base;
-	/**< Base address where BAR is mapped */
-	struct otx2_ree_pending_queue pend_q;
-	/**< Pending queue */
-	rte_iova_t iq_dma_addr;
-	/**< Instruction queue address */
-	uint32_t otx2_regexdev_jobid;
-	/**< Job ID */
-	uint32_t write_offset;
-	/**< write offset */
-	regexdev_stop_flush_t cb;
-	/**< Callback function called during rte_regex_dev_stop()*/
-};
-
-#endif /* _OTX2_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.h b/drivers/regex/octeontx2/otx2_regexdev_compiler.h
deleted file mode 100644
index 8d2625bf7f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_COMPILER_H_
-#define _OTX2_REGEXDEV_COMPILER_H_
-
-int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev);
-
-#endif /* _OTX2_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c b/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
deleted file mode 100644
index f8031d0f72..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
-
-static void
-ree_lf_err_intr_handler(void *param)
-{
-	uintptr_t base = (uintptr_t)param;
-	uint8_t lf_id;
-	uint64_t intr;
-
-	lf_id = (base >> 12) & 0xFF;
-
-	intr = otx2_read64(base + OTX2_REE_LF_MISC_INT);
-	if (intr == 0)
-		return;
-
-	otx2_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
-
-	/* Clear interrupt */
-	otx2_write64(intr, base + OTX2_REE_LF_MISC_INT);
-}
-
-static void
-ree_lf_err_intr_unregister(const struct rte_regexdev *dev, uint16_t msix_off,
-			   uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	otx2_unregister_irq(handle, ree_lf_err_intr_handler, (void *)base,
-			    msix_off);
-}
-
-void
-otx2_ree_err_intr_unregister(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uintptr_t base;
-	uint32_t i;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
-	}
-
-	vf->err_intr_registered = 0;
-}
-
-static int
-ree_lf_err_intr_register(const struct rte_regexdev *dev, uint16_t msix_off,
-			 uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-	int ret;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	/* Register error interrupt handler */
-	ret = otx2_register_irq(handle, ree_lf_err_intr_handler, (void *)base,
-				msix_off);
-	if (ret)
-		return ret;
-
-	/* Enable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1S);
-
-	return 0;
-}
-
-int
-otx2_ree_err_intr_register(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uint32_t i, j, ret;
-	uintptr_t base;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
-			otx2_err("Invalid REE LF MSI-X offset: 0x%x",
-				    vf->lf_msixoff[i]);
-			return -EINVAL;
-		}
-	}
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ret = ree_lf_err_intr_register(dev, vf->lf_msixoff[i], base);
-		if (ret)
-			goto intr_unregister;
-	}
-
-	vf->err_intr_registered = 1;
-	return 0;
-
-intr_unregister:
-	/* Unregister the ones already registered */
-	for (j = 0; j < i; j++) {
-		base = OTX2_REE_LF_BAR2(vf, j);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
-	}
-	return ret;
-}
-
-int
-otx2_ree_iq_enable(const struct rte_regexdev *dev, const struct otx2_ree_qp *qp,
-		   uint8_t pri, uint32_t size_div2)
-{
-	union otx2_ree_lf_sbuf_addr base;
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Set instruction queue size and priority */
-	otx2_ree_config_lf(dev, qp->id, pri, size_div2);
-
-	/* Set instruction queue base address */
-	/* Should be written after SBUF_CTL and before LF_ENA */
-
-	base.u = otx2_read64(qp->base + OTX2_REE_LF_SBUF_ADDR);
-	base.s.ptr = qp->iq_dma_addr >> 7;
-	otx2_write64(base.u, qp->base + OTX2_REE_LF_SBUF_ADDR);
-
-	/* Enable instruction queue */
-
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 1;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-
-	return 0;
-}
-
-void
-otx2_ree_iq_disable(struct otx2_ree_qp *qp)
-{
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Stop instruction execution */
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 0x0;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-}
-
-int
-otx2_ree_max_matches_get(const struct rte_regexdev *dev, uint8_t *max_matches)
-{
-	union otx2_ree_af_reexm_max_match reexm_max_match;
-	int ret;
-
-	ret = otx2_ree_af_reg_read(dev, REE_AF_REEXM_MAX_MATCH,
-				   &reexm_max_match.u);
-	if (ret)
-		return ret;
-
-	*max_matches = reexm_max_match.s.max;
-	return 0;
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h b/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
deleted file mode 100644
index dedf5f3282..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_HW_ACCESS_H_
-#define _OTX2_REGEXDEV_HW_ACCESS_H_
-
-#include <stdint.h>
-
-#include "otx2_regexdev.h"
-
-/* REE instruction queue length */
-#define OTX2_REE_IQ_LEN			(1 << 13)
-
-#define OTX2_REE_DEFAULT_CMD_QLEN	OTX2_REE_IQ_LEN
-
-/* Status register bits */
-#define OTX2_REE_STATUS_PMI_EOJ_BIT		(1 << 14)
-#define OTX2_REE_STATUS_PMI_SOJ_BIT		(1 << 13)
-#define OTX2_REE_STATUS_MP_CNT_DET_BIT		(1 << 7)
-#define OTX2_REE_STATUS_MM_CNT_DET_BIT		(1 << 6)
-#define OTX2_REE_STATUS_ML_CNT_DET_BIT		(1 << 5)
-#define OTX2_REE_STATUS_MST_CNT_DET_BIT		(1 << 4)
-#define OTX2_REE_STATUS_MPT_CNT_DET_BIT		(1 << 3)
-
-/* Register offsets */
-/* REE LF registers */
-#define OTX2_REE_LF_DONE_INT		0x120ull
-#define OTX2_REE_LF_DONE_INT_W1S	0x130ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1S	0x138ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1C	0x140ull
-#define OTX2_REE_LF_MISC_INT		0x300ull
-#define OTX2_REE_LF_MISC_INT_W1S	0x310ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1S	0x320ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1C	0x330ull
-#define OTX2_REE_LF_ENA			0x10ull
-#define OTX2_REE_LF_SBUF_ADDR		0x20ull
-#define OTX2_REE_LF_DONE		0x100ull
-#define OTX2_REE_LF_DONE_ACK		0x110ull
-#define OTX2_REE_LF_DONE_WAIT		0x148ull
-#define OTX2_REE_LF_DOORBELL		0x400ull
-#define OTX2_REE_LF_OUTSTAND_JOB	0x410ull
-
-/* BAR 0 */
-#define OTX2_REE_AF_QUE_SBUF_CTL(a)	(0x1200ull | (uint64_t)(a) << 3)
-#define OTX2_REE_PRIV_LF_CFG(a)		(0x41000ull | (uint64_t)(a) << 3)
-
-#define OTX2_REE_LF_BAR2(vf, q_id) \
-		((vf)->otx2_dev.bar2 + \
-		 (((vf)->block_address << 20) | ((q_id) << 12)))
-
-
-#define OTX2_REE_QUEUE_HI_PRIO 0x1
-
-enum ree_desc_type_e {
-	REE_TYPE_JOB_DESC    = 0x0,
-	REE_TYPE_RESULT_DESC = 0x1,
-	REE_TYPE_ENUM_LAST   = 0x2
-};
-
-union otx2_ree_priv_lf_cfg {
-	uint64_t u;
-	struct {
-		uint64_t slot                        : 8;
-		uint64_t pf_func                     : 16;
-		uint64_t reserved_24_62              : 39;
-		uint64_t ena                         : 1;
-	} s;
-};
-
-
-union otx2_ree_lf_sbuf_addr {
-	uint64_t u;
-	struct {
-		uint64_t off                         : 7;
-		uint64_t ptr                         : 46;
-		uint64_t reserved_53_63              : 11;
-	} s;
-};
-
-union otx2_ree_lf_ena {
-	uint64_t u;
-	struct {
-		uint64_t ena                         : 1;
-		uint64_t reserved_1_63               : 63;
-	} s;
-};
-
-union otx2_ree_af_reexm_max_match {
-	uint64_t u;
-	struct {
-		uint64_t max                         : 8;
-		uint64_t reserved_8_63               : 56;
-	} s;
-};
-
-union otx2_ree_lf_done {
-	uint64_t u;
-	struct {
-		uint64_t done                        : 20;
-		uint64_t reserved_20_63              : 44;
-	} s;
-};
-
-union otx2_ree_inst {
-	uint64_t u[8];
-	struct  {
-		uint64_t doneint                     :  1;
-		uint64_t reserved_1_3                :  3;
-		uint64_t dg                          :  1;
-		uint64_t reserved_5_7                :  3;
-		uint64_t ooj                         :  1;
-		uint64_t reserved_9_15               :  7;
-		uint64_t reserved_16_63              : 48;
-		uint64_t inp_ptr_addr                : 64;
-		uint64_t inp_ptr_ctl                 : 64;
-		uint64_t res_ptr_addr                : 64;
-		uint64_t wq_ptr                      : 64;
-		uint64_t tag                         : 32;
-		uint64_t tt                          :  2;
-		uint64_t ggrp                        : 10;
-		uint64_t reserved_364_383            : 20;
-		uint64_t reserved_384_391            :  8;
-		uint64_t ree_job_id                  : 24;
-		uint64_t ree_job_ctrl                : 16;
-		uint64_t ree_job_length              : 15;
-		uint64_t reserved_447_447            :  1;
-		uint64_t ree_job_subset_id_0         : 16;
-		uint64_t ree_job_subset_id_1         : 16;
-		uint64_t ree_job_subset_id_2         : 16;
-		uint64_t ree_job_subset_id_3         : 16;
-	} cn98xx;
-};
-
-union otx2_ree_res_status {
-	uint64_t u;
-	struct {
-		uint64_t job_type                    :  3;
-		uint64_t mpt_cnt_det                 :  1;
-		uint64_t mst_cnt_det                 :  1;
-		uint64_t ml_cnt_det                  :  1;
-		uint64_t mm_cnt_det                  :  1;
-		uint64_t mp_cnt_det                  :  1;
-		uint64_t mode                        :  2;
-		uint64_t reserved_10_11              :  2;
-		uint64_t reserved_12_12              :  1;
-		uint64_t pmi_soj                     :  1;
-		uint64_t pmi_eoj                     :  1;
-		uint64_t reserved_15_15              :  1;
-		uint64_t reserved_16_63              : 48;
-	} s;
-};
-
-union otx2_ree_res {
-	uint64_t u[8];
-	struct ree_res_s_98 {
-		uint64_t done			:  1;
-		uint64_t hwjid			:  7;
-		uint64_t ree_res_job_id		: 24;
-		uint64_t ree_res_status		: 16;
-		uint64_t ree_res_dmcnt		:  8;
-		uint64_t ree_res_mcnt		:  8;
-		uint64_t ree_meta_ptcnt		: 16;
-		uint64_t ree_meta_icnt		: 16;
-		uint64_t ree_meta_lcnt		: 16;
-		uint64_t ree_pmi_min_byte_ptr	: 16;
-		uint64_t ree_err		:  1;
-		uint64_t reserved_129_190	: 62;
-		uint64_t doneint		:  1;
-		uint64_t reserved_192_255	: 64;
-		uint64_t reserved_256_319	: 64;
-		uint64_t reserved_320_383	: 64;
-		uint64_t reserved_384_447	: 64;
-		uint64_t reserved_448_511	: 64;
-	} s;
-};
-
-union otx2_ree_match {
-	uint64_t u;
-	struct {
-		uint64_t ree_rule_id                 : 32;
-		uint64_t start_ptr                   : 14;
-		uint64_t reserved_46_47              :  2;
-		uint64_t match_length                : 15;
-		uint64_t reserved_63_63              :  1;
-	} s;
-};
-
-void otx2_ree_err_intr_unregister(const struct rte_regexdev *dev);
-
-int otx2_ree_err_intr_register(const struct rte_regexdev *dev);
-
-int otx2_ree_iq_enable(const struct rte_regexdev *dev,
-		       const struct otx2_ree_qp *qp,
-		       uint8_t pri, uint32_t size_div128);
-
-void otx2_ree_iq_disable(struct otx2_ree_qp *qp);
-
-int otx2_ree_max_matches_get(const struct rte_regexdev *dev,
-			     uint8_t *max_matches);
-
-#endif /* _OTX2_REGEXDEV_HW_ACCESS_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.c b/drivers/regex/octeontx2/otx2_regexdev_mbox.c
deleted file mode 100644
index 6d58d367d4..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_mbox.h"
-#include "otx2_regexdev.h"
-
-int
-otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-			      uint16_t *nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct free_rsrcs_rsp *rsp;
-	struct otx2_dev *otx2_dev;
-	int ret;
-
-	otx2_dev = &vf->otx2_dev;
-	otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);
-
-	ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
-	if (ret)
-		return -EIO;
-
-	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-		*nb_queues = rsp->ree0;
-	else
-		*nb_queues = rsp->ree1;
-	return 0;
-}
-
-int
-otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_attach_req *req;
-	struct otx2_mbox *mbox;
-
-	/* Ask AF to attach required LFs */
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_attach_resources(mbox);
-
-	/* 1 LF = 1 queue */
-	req->reelfs = nb_queues;
-	req->ree_blkaddr = vf->block_address;
-
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Update number of attached queues */
-	vf->nb_queues = nb_queues;
-
-	return 0;
-}
-
-int
-otx2_ree_queues_detach(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_detach_req *req;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_detach_resources(mbox);
-	req->reelfs = true;
-	req->partial = true;
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Queues have been detached */
-	vf->nb_queues = 0;
-
-	return 0;
-}
-
-int
-otx2_ree_msix_offsets_get(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct msix_offset_rsp *rsp;
-	struct otx2_mbox *mbox;
-	uint32_t i, ret;
-
-	/* Get REE MSI-X vector offsets */
-	mbox = vf->otx2_dev.mbox;
-	otx2_mbox_alloc_msg_msix_offset(mbox);
-
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
-		else
-			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
-		otx2_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
-	}
-
-	return 0;
-}
-
-static int
-ree_send_mbox_msg(struct otx2_ree_vf *vf)
-{
-	struct otx2_mbox *mbox = vf->otx2_dev.mbox;
-	int ret;
-
-	otx2_mbox_msg_send(mbox, 0);
-
-	ret = otx2_mbox_wait_for_rsp(mbox, 0);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-
-	return 0;
-}
-
-int
-otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		   uint32_t size)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_lf_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_ree_config_lf(mbox);
-
-	req->lf = lf;
-	req->pri =  pri ? 1 : 0;
-	req->size = size;
-	req->blkaddr = vf->block_address;
-
-	ret = otx2_mbox_process(mbox);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-	return 0;
-}
-
-int
-otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-		     uint64_t *val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox_dev *mdev;
-	struct otx2_mbox *mbox;
-	int ret, off;
-
-	mbox = vf->otx2_dev.mbox;
-	mdev = &mbox->dev[0];
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 0;
-	msg->reg_offset = reg;
-	msg->ret_val = val;
-	msg->blkaddr = vf->block_address;
-
-	ret = ree_send_mbox_msg(vf);
-	if (ret < 0)
-		return ret;
-
-	off = mbox->rx_start +
-			RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
-	msg = (struct ree_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);
-
-	*val = msg->val;
-
-	return 0;
-}
-
-int
-otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-		      uint64_t val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 1;
-	msg->reg_offset = reg;
-	msg->val = val;
-	msg->blkaddr = vf->block_address;
-
-	return ree_send_mbox_msg(vf);
-}
-
-int
-otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_get_req_msg *req;
-	struct ree_rule_db_get_rsp_msg *rsp;
-	char *rule_db_ptr = (char *)rule_db;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct otx2_mbox *mbox;
-	int ret, last = 0;
-	uint32_t len = 0;
-
-	mbox = vf->otx2_dev.mbox;
-	if (!rule_db) {
-		otx2_err("Couldn't return rule db due to NULL pointer");
-		return -EFAULT;
-	}
-
-	while (!last) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 0;
-		req->offset = len;
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_db_len < len + rsp->len) {
-			otx2_err("Rule db size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
-		len += rsp->len;
-		rule_db_ptr = rule_db_ptr + rsp->len;
-		last = rsp->is_last;
-	}
-
-	if (rule_dbi) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 1;
-		req->offset = 0;
-
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_dbi_len < rsp->len) {
-			otx2_err("Rule dbi size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-		uint32_t *rule_db_len,
-		uint32_t *rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_len_rsp_msg *rsp;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = (struct ree_req_msg *)
-		otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), sizeof(*rsp));
-	if (!req) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
-	req->hdr.sig = OTX2_MBOX_REQ_SIG;
-	req->hdr.pcifunc = vf->otx2_dev.pf_func;
-	req->blkaddr = vf->block_address;
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-	if (rule_db_len != NULL)
-		*rule_db_len = rsp->len;
-	if (rule_dbi_len != NULL)
-		*rule_dbi_len = rsp->inc_len;
-
-	return 0;
-}
-
-static int
-ree_db_msg(const struct rte_regexdev *dev, const char *db, uint32_t db_len,
-		int inc, int dbi)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	uint32_t len_left = db_len, offset = 0;
-	struct ree_rule_db_prog_req_msg *req;
-	struct otx2_ree_vf *vf = &data->vf;
-	const char *rule_db_ptr = db;
-	struct otx2_mbox *mbox;
-	struct msg_rsp *rsp;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	while (len_left) {
-		req = (struct ree_rule_db_prog_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->offset = offset;
-		req->total_len = db_len;
-		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
-		req->is_incremental = inc;
-		req->is_dbi = dbi;
-		req->blkaddr = vf->block_address;
-
-		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
-			req->is_last = true;
-			req->len = len_left;
-		}
-		otx2_mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret) {
-			otx2_err("Programming mailbox processing failed");
-			return ret;
-		}
-		len_left -= req->len;
-		offset += req->len;
-		rule_db_ptr = rule_db_ptr + req->len;
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len)
-{
-	int inc, ret;
-
-	if (rule_db_len == 0) {
-		otx2_err("Couldn't program empty rule db");
-		return -EFAULT;
-	}
-	inc = (rule_dbi_len != 0);
-	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
-		otx2_err("Couldn't program NULL rule db");
-		return -EFAULT;
-	}
-	if (inc) {
-		ret = ree_db_msg(dev, rule_dbi, rule_dbi_len, inc, 1);
-		if (ret)
-			return ret;
-	}
-	return ree_db_msg(dev, rule_db, rule_db_len, inc, 0);
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.h b/drivers/regex/octeontx2/otx2_regexdev_mbox.h
deleted file mode 100644
index 953efa6724..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_MBOX_H_
-#define _OTX2_REGEXDEV_MBOX_H_
-
-#include <rte_regexdev.h>
-
-int otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-				  uint16_t *nb_queues);
-
-int otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues);
-
-int otx2_ree_queues_detach(const struct rte_regexdev *dev);
-
-int otx2_ree_msix_offsets_get(const struct rte_regexdev *dev);
-
-int otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		       uint32_t size);
-
-int otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-			 uint64_t *val);
-
-int otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-			  uint64_t val);
-
-int otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		 uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len);
-
-int otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-			     uint32_t *rule_db_len, uint32_t *rule_dbi_len);
-
-int otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len);
-
-#endif /* _OTX2_REGEXDEV_MBOX_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 0/5] regex/cn9k: use cnxk infrastructure
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
                     ` (5 preceding siblings ...)
  2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
@ 2021-11-29 19:49   ` lironh
  2021-11-29 19:49     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
                       ` (4 more replies)
  2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
  7 siblings, 5 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:49 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v3:
- fix documentation issues

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 doc/guides/platform/octeontx2.rst             |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 doc/guides/rel_notes/release_20_11.rst        |   2 +-
 drivers/common/cnxk/hw/ree.h                  | 126 ++++
 drivers/common/cnxk/hw/rvu.h                  |   5 +
 drivers/common/cnxk/meson.build               |   1 +
 drivers/common/cnxk/roc_api.h                 |   4 +
 drivers/common/cnxk/roc_constants.h           |   2 +
 drivers/common/cnxk/roc_mbox.h                | 100 +++
 drivers/common/cnxk/roc_platform.c            |   1 +
 drivers/common/cnxk/roc_platform.h            |   2 +
 drivers/common/cnxk/roc_priv.h                |   3 +
 drivers/common/cnxk/roc_ree.c                 | 647 ++++++++++++++++++
 drivers/common/cnxk/roc_ree.h                 | 137 ++++
 drivers/common/cnxk/roc_ree_priv.h            |  18 +
 drivers/common/cnxk/version.map               |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +++++------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -----
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 33 files changed, 1332 insertions(+), 1206 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 1/5] common/cnxk: add REE HW definitions
  2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
@ 2021-11-29 19:49     ` lironh
  2021-11-29 19:49     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
                       ` (3 subsequent siblings)
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:49 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

adding REE (Regular Expression Engine) HW definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/hw/ree.h | 126 +++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/hw/rvu.h |   5 ++
 2 files changed, 131 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/ree.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 0000000000..30af61d704
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BIT	   BIT_ULL(14)
+#define REE_STATUS_PMI_SOJ_BIT	   BIT_ULL(13)
+#define REE_STATUS_MP_CNT_DET_BIT  BIT_ULL(7)
+#define REE_STATUS_MM_CNT_DET_BIT  BIT_ULL(6)
+#define REE_STATUS_ML_CNT_DET_BIT  BIT_ULL(5)
+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT		0x120ull
+#define REE_LF_DONE_INT_W1S	0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT		0x300ull
+#define REE_LF_MISC_INT_W1S	0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA		0x10ull
+#define REE_LF_SBUF_ADDR	0x20ull
+#define REE_LF_DONE		0x100ull
+#define REE_LF_DONE_ACK		0x110ull
+#define REE_LF_DONE_WAIT	0x148ull
+#define REE_LF_DOORBELL		0x400ull
+#define REE_LF_OUTSTAND_JOB	0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a)     (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS	(0x0ull)
+#define REE_AF_INT_VEC_RVU	(0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ	(0x3ull)
+
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC	(0x1ull)
+
+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
+
+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)
+
+#define REE_LF_BAR2(vf, q_id)                                                  \
+	((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+	REE_TYPE_JOB_DESC = 0x0,
+	REE_TYPE_RESULT_DESC = 0x1,
+	REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_res_status {
+	uint64_t u;
+	struct {
+		uint64_t job_type : 3;
+		uint64_t mpt_cnt_det : 1;
+		uint64_t mst_cnt_det : 1;
+		uint64_t ml_cnt_det : 1;
+		uint64_t mm_cnt_det : 1;
+		uint64_t mp_cnt_det : 1;
+		uint64_t mode : 2;
+		uint64_t reserved_10_11 : 2;
+		uint64_t reserved_12_12 : 1;
+		uint64_t pmi_soj : 1;
+		uint64_t pmi_eoj : 1;
+		uint64_t reserved_15_15 : 1;
+		uint64_t reserved_16_63 : 48;
+	} s;
+};
+
+union ree_res {
+	uint64_t u[8];
+	struct ree_res_s_98 {
+		uint64_t done : 1;
+		uint64_t hwjid : 7;
+		uint64_t ree_res_job_id : 24;
+		uint64_t ree_res_status : 16;
+		uint64_t ree_res_dmcnt : 8;
+		uint64_t ree_res_mcnt : 8;
+		uint64_t ree_meta_ptcnt : 16;
+		uint64_t ree_meta_icnt : 16;
+		uint64_t ree_meta_lcnt : 16;
+		uint64_t ree_pmi_min_byte_ptr : 16;
+		uint64_t ree_err : 1;
+		uint64_t reserved_129_190 : 62;
+		uint64_t doneint : 1;
+		uint64_t reserved_192_255 : 64;
+		uint64_t reserved_256_319 : 64;
+		uint64_t reserved_320_383 : 64;
+		uint64_t reserved_384_447 : 64;
+		uint64_t reserved_448_511 : 64;
+	} s;
+};
+
+union ree_match {
+	uint64_t u;
+	struct {
+		uint64_t ree_rule_id : 32;
+		uint64_t start_ptr : 14;
+		uint64_t reserved_46_47 : 2;
+		uint64_t match_length : 15;
+		uint64_t reserved_63_6 : 1;
+	} s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM    (0x0ull)
 #define RVU_BLOCK_ADDR_LMT     (0x1ull)
@@ -147,6 +148,8 @@
 #define RVU_BLOCK_ADDR_NDC2    (0xeull)
 #define RVU_BLOCK_ADDR_R_END   (0x1full)
 #define RVU_BLOCK_ADDR_R_START (0x14ull)
+#define RVU_BLOCK_ADDR_REE0    (0x14ull)
+#define RVU_BLOCK_ADDR_REE1    (0x15ull)
 
 #define RVU_VF_INT_VEC_MBOX (0x0ull)
 
@@ -167,6 +170,7 @@
 #define NPA_AF_BAR2_SEL	 (0x9000000ull)
 #define CPT_AF_BAR2_SEL	 (0x9000000ull)
 #define RVU_AF_BAR2_SEL	 (0x9000000ull)
+#define REE_AF_BAR2_SEL	 (0x9000000ull)
 
 #define AF_BAR2_ALIASX(a, b)                                                   \
 	(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))
@@ -177,6 +181,7 @@
 #define NPA_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(0, b)
 #define CPT_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 #define RVU_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
+#define REE_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 
 /* Structures definitions */
 
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 2/5] common/cnxk: add REE mbox definitions
  2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
  2021-11-29 19:49     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
@ 2021-11-29 19:49     ` lironh
  2021-11-29 19:49     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
                       ` (2 subsequent siblings)
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:49 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add REE mbox definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 100 +++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..e97d93e261 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -151,6 +151,16 @@ struct mbox_msghdr {
 	M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)        \
 	M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,            \
 	  cpt_eng_grp_rsp)                                                     \
+	/* REE mbox IDs (range 0xE00 - 0xFFF) */                               \
+	M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)        \
+	M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,    \
+	  ree_rd_wr_reg_msg)                                                   \
+	M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+	  msg_rsp)                                                             \
+	M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,        \
+	  ree_rule_db_len_rsp_msg)                                             \
+	M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,    \
+	  ree_rule_db_get_rsp_msg)                                             \
 	/* SDP mbox IDs (range 0x1000 - 0x11FF) */                             \
 	M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg,     \
 	  msg_rsp)                                                             \
@@ -1452,6 +1462,96 @@ struct cpt_eng_grp_rsp {
 	uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+	REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+	REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+	REE_AF_ERR_LF_INVALID = -1003,
+	REE_AF_ERR_ACCESS_DENIED = -1004,
+	REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+	REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+	REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+	REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+	REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+	REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+	REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+	REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+	REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+	REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+	REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+	REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+	REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+	REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+	REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+	REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+	REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+	REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+	REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io size;
+	uint8_t __io lf;
+	uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+	uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+	uint32_t __io blkaddr;	     /* REE0 or REE1 */
+	uint32_t __io total_len;     /* total len of rule db */
+	uint32_t __io offset;	     /* offset of current rule db block */
+	uint16_t __io len;	     /* length of rule db block */
+	uint8_t __io is_last;	     /* is this the last block */
+	uint8_t __io is_incremental; /* is incremental flow */
+	uint8_t __io is_dbi;	     /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io offset; /* retrieve db from this offset */
+	uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+	struct mbox_msghdr hdr;
+	uint64_t __io reg_offset;
+	uint64_t __io *ret_val;
+	uint64_t __io val;
+	uint32_t __io blkaddr;
+	uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io len;
+	uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+	uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+	uint32_t __io total_len; /* total len of rule db */
+	uint32_t __io offset;	 /* offset of current rule db block */
+	uint16_t __io len;	 /* length of rule db block */
+	uint8_t __io is_last;	 /* is this the last block */
+};
+
 /* NPC mbox message structs */
 
 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 3/5] common/cnxk: add REE support
  2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
  2021-11-29 19:49     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
  2021-11-29 19:49     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
@ 2021-11-29 19:49     ` lironh
  2021-11-29 19:49     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
  2021-11-29 19:49     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:49 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

extend cnxk infrastructure to support REE

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_ree.c      | 647 +++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ree.h      | 137 ++++++
 drivers/common/cnxk/roc_ree_priv.h |  18 +
 3 files changed, 802 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 0000000000..1eb2ae7272
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+	struct free_rsrcs_rsp *rsp;
+	struct dev *dev = vf->dev;
+	int ret;
+
+	mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+		*nb_queues = rsp->ree0;
+	else
+		*nb_queues = rsp->ree1;
+	return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+	uint64_t val;
+	int ret;
+
+	ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+	if (ret)
+		return ret;
+
+	*max_matches = val;
+	return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+	struct rsrc_attach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	/* Ask AF to attach required LFs */
+	req = mbox_alloc_msg_attach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	/* 1 LF = 1 queue */
+	req->reelfs = nb_queues;
+	req->ree_blkaddr = vf->block_address;
+
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Update number of attached queues */
+	vf->nb_queues = nb_queues;
+
+	return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+	struct rsrc_detach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_detach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+	req->reelfs = true;
+	req->partial = true;
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Queues have been detached */
+	vf->nb_queues = 0;
+
+	return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+	struct msix_offset_rsp *rsp;
+	struct mbox *mbox;
+	uint32_t i, ret;
+
+	/* Get REE MSI-X vector offsets */
+	mbox = vf->dev->mbox;
+	mbox_alloc_msg_msix_offset(mbox);
+
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+		else
+			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+		plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+	}
+
+	return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+	struct mbox *mbox = vf->dev->mbox;
+	int ret;
+
+	mbox_msg_send(mbox, 0);
+
+	ret = mbox_wait_for_rsp(mbox, 0);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+
+	return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t size)
+{
+	struct ree_lf_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_ree_config_lf(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->lf = lf;
+	req->pri = pri ? 1 : 0;
+	req->size = size;
+	req->blkaddr = vf->block_address;
+
+	ret = mbox_process(mbox);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+	return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox_dev *mdev;
+	struct mbox *mbox;
+	int ret, off;
+
+	mbox = vf->dev->mbox;
+	mdev = &mbox->dev[0];
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 0;
+	msg->reg_offset = reg;
+	msg->ret_val = val;
+	msg->blkaddr = vf->block_address;
+
+	ret = ree_send_mbox_msg(vf);
+	if (ret < 0)
+		return ret;
+
+	off = mbox->rx_start +
+	      RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+	msg = (struct ree_rd_wr_reg_msg *)((uintptr_t)mdev->mbase + off);
+
+	*val = msg->val;
+
+	return 0;
+}
+
+int
+roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg, uint64_t val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 1;
+	msg->reg_offset = reg;
+	msg->val = val;
+	msg->blkaddr = vf->block_address;
+
+	return ree_send_mbox_msg(vf);
+}
+
+int
+roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db, uint32_t rule_db_len,
+		    char *rule_dbi, uint32_t rule_dbi_len)
+{
+	struct ree_rule_db_get_req_msg *req;
+	struct ree_rule_db_get_rsp_msg *rsp;
+	char *rule_db_ptr = (char *)rule_db;
+	struct mbox *mbox;
+	int ret, last = 0;
+	uint32_t len = 0;
+
+	mbox = vf->dev->mbox;
+	if (!rule_db) {
+		plt_err("Couldn't return rule db due to NULL pointer");
+		return -EFAULT;
+	}
+
+	while (!last) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 0;
+		req->offset = len;
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_db_len < len + rsp->len) {
+			plt_err("Rule db size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
+		len += rsp->len;
+		rule_db_ptr = rule_db_ptr + rsp->len;
+		last = rsp->is_last;
+	}
+
+	if (rule_dbi) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 1;
+		req->offset = 0;
+
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_dbi_len < rsp->len) {
+			plt_err("Rule dbi size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_len_get(struct roc_ree_vf *vf, uint32_t *rule_db_len,
+			uint32_t *rule_dbi_len)
+{
+	struct ree_rule_db_len_rsp_msg *rsp;
+	struct ree_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = (struct ree_req_msg *)mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
+						       sizeof(*rsp));
+	if (!req) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
+	req->hdr.sig = MBOX_REQ_SIG;
+	req->hdr.pcifunc = vf->dev->pf_func;
+	req->blkaddr = vf->block_address;
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+	if (rule_db_len != NULL)
+		*rule_db_len = rsp->len;
+	if (rule_dbi_len != NULL)
+		*rule_dbi_len = rsp->inc_len;
+
+	return 0;
+}
+
+static int
+ree_db_msg(struct roc_ree_vf *vf, const char *db, uint32_t db_len, int inc,
+	   int dbi)
+{
+	uint32_t len_left = db_len, offset = 0;
+	struct ree_rule_db_prog_req_msg *req;
+	const char *rule_db_ptr = db;
+	struct mbox *mbox;
+	struct msg_rsp *rsp;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	while (len_left) {
+		req = (struct ree_rule_db_prog_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->offset = offset;
+		req->total_len = db_len;
+		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
+		req->is_incremental = inc;
+		req->is_dbi = dbi;
+		req->blkaddr = vf->block_address;
+
+		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
+			req->is_last = true;
+			req->len = len_left;
+		}
+		mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret) {
+			plt_err("Programming mailbox processing failed");
+			return ret;
+		}
+		len_left -= req->len;
+		offset += req->len;
+		rule_db_ptr = rule_db_ptr + req->len;
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+		     uint32_t rule_db_len, const char *rule_dbi,
+		     uint32_t rule_dbi_len)
+{
+	int inc, ret;
+
+	if (rule_db_len == 0) {
+		plt_err("Couldn't program empty rule db");
+		return -EFAULT;
+	}
+	inc = (rule_dbi_len != 0);
+	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
+		plt_err("Couldn't program NULL rule db");
+		return -EFAULT;
+	}
+	if (inc) {
+		ret = ree_db_msg(vf, rule_dbi, rule_dbi_len, inc, 1);
+		if (ret)
+			return ret;
+	}
+	return ree_db_msg(vf, rule_db, rule_db_len, inc, 0);
+}
+
+static int
+ree_get_blkaddr(struct dev *dev)
+{
+	int pf;
+
+	pf = dev_get_pf(dev->pf_func);
+	if (pf == REE0_PF)
+		return RVU_BLOCK_ADDR_REE0;
+	else if (pf == REE1_PF)
+		return RVU_BLOCK_ADDR_REE1;
+	else
+		return 0;
+}
+
+uintptr_t
+roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id)
+{
+	return REE_LF_BAR2(vf, qp_id);
+}
+
+static void
+roc_ree_lf_err_intr_handler(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint8_t lf_id;
+	uint64_t intr;
+
+	lf_id = (base >> 12) & 0xFF;
+
+	intr = plt_read64(base + REE_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
+
+	/* Clear interrupt */
+	plt_write64(intr, base + REE_LF_MISC_INT);
+}
+
+static void
+roc_ree_lf_err_intr_unregister(struct roc_ree_vf *vf, uint16_t msix_off,
+			       uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	dev_irq_unregister(pci_dev->intr_handle,
+			   roc_ree_lf_err_intr_handler, (void *)base, msix_off);
+}
+
+void
+roc_ree_err_intr_unregister(struct roc_ree_vf *vf)
+{
+	uintptr_t base;
+	uint32_t i;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base);
+	}
+
+	vf->err_intr_registered = 0;
+}
+
+static int
+roc_ree_lf_err_intr_register(struct roc_ree_vf *vf, uint16_t msix_off,
+			     uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+	int ret;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	/* Register error interrupt handler */
+	ret = dev_irq_register(pci_dev->intr_handle,
+			       roc_ree_lf_err_intr_handler, (void *)base,
+			       msix_off);
+	if (ret)
+		return ret;
+
+	/* Enable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1S);
+
+	return 0;
+}
+
+int
+roc_ree_err_intr_register(struct roc_ree_vf *vf)
+{
+	uint32_t i, j, ret;
+	uintptr_t base;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
+			plt_err("Invalid REE LF MSI-X offset: 0x%x",
+				vf->lf_msixoff[i]);
+			return -EINVAL;
+		}
+	}
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		ret = roc_ree_lf_err_intr_register(vf, vf->lf_msixoff[i], base);
+		if (ret)
+			goto intr_unregister;
+	}
+
+	vf->err_intr_registered = 1;
+	return 0;
+
+intr_unregister:
+	/* Unregister the ones already registered */
+	for (j = 0; j < i; j++) {
+		base = REE_LF_BAR2(vf, j);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[j], base);
+	}
+	return ret;
+}
+
+int
+roc_ree_iq_enable(struct roc_ree_vf *vf, const struct roc_ree_qp *qp,
+		  uint8_t pri, uint32_t size_div2)
+{
+	uint64_t val;
+
+	/* Set instruction queue size and priority */
+	roc_ree_config_lf(vf, qp->id, pri, size_div2);
+
+	/* Set instruction queue base address */
+	/* Should be written after SBUF_CTL and before LF_ENA */
+
+	val = plt_read64(qp->base + REE_LF_SBUF_ADDR);
+	val &= ~REE_LF_SBUF_ADDR_PTR_MASK;
+	val |= FIELD_PREP(REE_LF_SBUF_ADDR_PTR_MASK, qp->iq_dma_addr >> 7);
+	plt_write64(val, qp->base + REE_LF_SBUF_ADDR);
+
+	/* Enable instruction queue */
+
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 1);
+	plt_write64(val, qp->base + REE_LF_ENA);
+
+	return 0;
+}
+
+void
+roc_ree_iq_disable(struct roc_ree_qp *qp)
+{
+	uint64_t val;
+
+	/* Stop instruction execution */
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 0);
+	plt_write64(val, qp->base + REE_LF_ENA);
+}
+
+int
+roc_ree_dev_init(struct roc_ree_vf *vf)
+{
+	struct plt_pci_device *pci_dev;
+	struct ree *ree;
+	struct dev *dev;
+	uint8_t max_matches = 0;
+	uint16_t nb_queues = 0;
+	int rc;
+
+	if (vf == NULL || vf->pci_dev == NULL)
+		return -EINVAL;
+
+	PLT_STATIC_ASSERT(sizeof(struct ree) <= ROC_REE_MEM_SZ);
+
+	ree = roc_ree_to_ree_priv(vf);
+	memset(ree, 0, sizeof(*ree));
+	vf->dev = &ree->dev;
+
+	pci_dev = vf->pci_dev;
+	dev = vf->dev;
+
+	/* Initialize device  */
+	rc = dev_init(dev, pci_dev);
+	if (rc) {
+		plt_err("Failed to init roc device");
+		goto fail;
+	}
+
+	/* Get REE block address */
+	vf->block_address = ree_get_blkaddr(dev);
+	if (!vf->block_address) {
+		plt_err("Could not determine block PF number");
+		goto fail;
+	}
+
+	/* Get number of queues available on the device */
+	rc = roc_ree_available_queues_get(vf, &nb_queues);
+	if (rc) {
+		plt_err("Could not determine the number of queues available");
+		goto fail;
+	}
+
+	/* Don't exceed the limits set per VF */
+	nb_queues = RTE_MIN(nb_queues, REE_MAX_QUEUES_PER_VF);
+
+	if (nb_queues == 0) {
+		plt_err("No free queues available on the device");
+		goto fail;
+	}
+
+	vf->max_queues = nb_queues;
+
+	plt_ree_dbg("Max queues supported by device: %d", vf->max_queues);
+
+	/* Get number of maximum matches supported on the device */
+	rc = roc_ree_max_matches_get(vf, &max_matches);
+	if (rc) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+	/* Don't exceed the limits set per VF */
+	max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
+	if (max_matches == 0) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+
+	vf->max_matches = max_matches;
+
+	plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+fail:
+	return rc;
+}
+
+int
+roc_ree_dev_fini(struct roc_ree_vf *vf)
+{
+	if (vf == NULL)
+		return -EINVAL;
+
+	vf->max_matches = 0;
+	vf->max_queues = 0;
+
+	return dev_fini(vf->dev, vf->pci_dev);
+}
diff --git a/drivers/common/cnxk/roc_ree.h b/drivers/common/cnxk/roc_ree.h
new file mode 100644
index 0000000000..e138e4de66
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_H_
+#define _ROC_REE_H_
+
+#include "roc_api.h"
+
+#define REE_MAX_LFS	       36
+#define REE_MAX_QUEUES_PER_VF  36
+#define REE_MAX_MATCHES_PER_VF 254
+
+#define REE_MAX_PAYLOAD_SIZE (1 << 14)
+
+#define REE_NON_INC_PROG 0
+#define REE_INC_PROG	 1
+
+#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)
+
+/**
+ * Device vf data
+ */
+struct roc_ree_vf {
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	/**< Base class */
+	uint16_t max_queues;
+	/**< Max queues supported */
+	uint8_t nb_queues;
+	/**< Number of regex queues attached */
+	uint16_t max_matches;
+	/**<  Max matches supported*/
+	uint16_t lf_msixoff[REE_MAX_LFS];
+	/**< MSI-X offsets */
+	uint8_t block_address;
+	/**< REE Block Address */
+	uint8_t err_intr_registered : 1;
+	/**< Are error interrupts registered? */
+
+#define ROC_REE_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_REE_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+struct roc_ree_rid {
+	uintptr_t rid;
+	/** Request id of a ree operation */
+	uint64_t user_id;
+	/* Client data */
+	/**< IOVA address of the pattern to be matched. */
+};
+
+struct roc_ree_pending_queue {
+	uint64_t pending_count;
+	/** Pending requests count */
+	struct roc_ree_rid *rid_queue;
+	/** Array of pending requests */
+	uint16_t enq_tail;
+	/** Tail of queue to be used for enqueue */
+	uint16_t deq_head;
+	/** Head of queue to be used for dequeue */
+};
+
+struct roc_ree_qp {
+	uint32_t id;
+	/**< Queue pair id */
+	uintptr_t base;
+	/**< Base address where BAR is mapped */
+	struct roc_ree_pending_queue pend_q;
+	/**< Pending queue */
+	rte_iova_t iq_dma_addr;
+	/**< Instruction queue address */
+	uint32_t roc_regexdev_jobid;
+	/**< Job ID */
+	uint32_t write_offset;
+	/**< write offset */
+};
+
+union roc_ree_inst {
+	uint64_t u[8];
+	struct {
+		uint64_t doneint : 1;
+		uint64_t reserved_1_3 : 3;
+		uint64_t dg : 1;
+		uint64_t reserved_5_7 : 3;
+		uint64_t ooj : 1;
+		uint64_t reserved_9_15 : 7;
+		uint64_t reserved_16_63 : 48;
+		uint64_t inp_ptr_addr : 64;
+		uint64_t inp_ptr_ctl : 64;
+		uint64_t res_ptr_addr : 64;
+		uint64_t wq_ptr : 64;
+		uint64_t tag : 32;
+		uint64_t tt : 2;
+		uint64_t ggrp : 10;
+		uint64_t reserved_364_383 : 20;
+		uint64_t reserved_384_391 : 8;
+		uint64_t ree_job_id : 24;
+		uint64_t ree_job_ctrl : 16;
+		uint64_t ree_job_length : 15;
+		uint64_t reserved_447_447 : 1;
+		uint64_t ree_job_subset_id_0 : 16;
+		uint64_t ree_job_subset_id_1 : 16;
+		uint64_t ree_job_subset_id_2 : 16;
+		uint64_t ree_job_subset_id_3 : 16;
+	} cn98xx;
+};
+
+int __roc_api roc_ree_dev_init(struct roc_ree_vf *vf);
+int __roc_api roc_ree_dev_fini(struct roc_ree_vf *vf);
+int __roc_api roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues);
+int __roc_api roc_ree_queues_detach(struct roc_ree_vf *vf);
+int __roc_api roc_ree_msix_offsets_get(struct roc_ree_vf *vf);
+int __roc_api roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri,
+				uint32_t size);
+int __roc_api roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg,
+				  uint64_t *val);
+int __roc_api roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg,
+				   uint64_t val);
+int __roc_api roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db,
+				  uint32_t rule_db_len, char *rule_dbi,
+				  uint32_t rule_dbi_len);
+int __roc_api roc_ree_rule_db_len_get(struct roc_ree_vf *vf,
+				      uint32_t *rule_db_len,
+				      uint32_t *rule_dbi_len);
+int __roc_api roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+				   uint32_t rule_db_len, const char *rule_dbi,
+				   uint32_t rule_dbi_len);
+uintptr_t __roc_api roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id);
+void __roc_api roc_ree_err_intr_unregister(struct roc_ree_vf *vf);
+int __roc_api roc_ree_err_intr_register(struct roc_ree_vf *vf);
+int __roc_api roc_ree_iq_enable(struct roc_ree_vf *vf,
+				const struct roc_ree_qp *qp, uint8_t pri,
+				uint32_t size_div128);
+void __roc_api roc_ree_iq_disable(struct roc_ree_qp *qp);
+
+#endif /* _ROC_REE_H_ */
diff --git a/drivers/common/cnxk/roc_ree_priv.h b/drivers/common/cnxk/roc_ree_priv.h
new file mode 100644
index 0000000000..c39f7cf986
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree_priv.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_PRIV_H_
+#define _ROC_REE_PRIV_H_
+
+struct ree {
+	struct dev dev;
+} __plt_cache_aligned;
+
+static inline struct ree *
+roc_ree_to_ree_priv(struct roc_ree_vf *roc_ree)
+{
+	return (struct ree *)&roc_ree->reserved[0];
+}
+
+#endif /* _ROC_REE_PRIV_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 4/5] common/cnxk: link REE support to ROC files
  2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
                       ` (2 preceding siblings ...)
  2021-11-29 19:49     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
@ 2021-11-29 19:49     ` lironh
  2021-11-29 19:49     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:49 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add references to REE files from ROC files

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/meson.build     |  1 +
 drivers/common/cnxk/roc_api.h       |  4 ++++
 drivers/common/cnxk/roc_constants.h |  2 ++
 drivers/common/cnxk/roc_platform.c  |  1 +
 drivers/common/cnxk/roc_platform.h  |  2 ++
 drivers/common/cnxk/roc_priv.h      |  3 +++
 drivers/common/cnxk/version.map     | 18 +++++++++++++++++-
 7 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4928f7e549..7e27b3cc0a 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -61,6 +61,7 @@ sources = files(
         'roc_tim.c',
         'roc_tim_irq.c',
         'roc_utils.c',
+        'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index e7aaa07563..1b46c21f7f 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -37,6 +37,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -90,6 +91,9 @@
 /* DPI */
 #include "roc_dpi.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
index ac7335061c..5f78823642 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY	      0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF     0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF     0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 61d4781209..85aa6dcebc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)                                                  \
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)	plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)	plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)	plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)	plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)                                               \
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 782b90cf8d..122d411fe7 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,4 +44,7 @@
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..5a03b91784 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_nix;
 	cnxk_logtype_npa;
 	cnxk_logtype_npc;
+	cnxk_logtype_ree;
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
@@ -347,6 +348,21 @@ INTERNAL {
 	roc_tim_lf_enable;
 	roc_tim_lf_free;
 	roc_se_ctx_swap;
-
+	roc_ree_af_reg_read;
+	roc_ree_af_reg_write;
+	roc_ree_config_lf;
+	roc_ree_dev_fini;
+	roc_ree_dev_init;
+	roc_ree_err_intr_register;
+	roc_ree_err_intr_unregister;
+	roc_ree_iq_disable;
+	roc_ree_iq_enable;
+	roc_ree_msix_offsets_get;
+	roc_ree_qp_get_base;
+	roc_ree_queues_attach;
+	roc_ree_queues_detach;
+	roc_ree_rule_db_get;
+	roc_ree_rule_db_len_get;
+	roc_ree_rule_db_prog;
 	local: *;
 };
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure
  2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
                       ` (3 preceding siblings ...)
  2021-11-29 19:49     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
@ 2021-11-29 19:49     ` lironh
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:49 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

update driver to use the REE cnxk code
replace octeontx2/otx2 with cn9k

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 doc/guides/platform/octeontx2.rst             |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 doc/guides/rel_notes/release_20_11.rst        |   2 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 ++++++++----------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 -----
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 --------
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ---------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 --
 20 files changed, 269 insertions(+), 1205 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..5f45b35c51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst
 RegEx Drivers
 -------------
 
-Marvell OCTEON TX2 regex
+Marvell OCTEON CN9K regex
 M: Liron Himi <lironh@marvell.com>
-F: drivers/regex/octeontx2/
-F: doc/guides/regexdevs/octeontx2.rst
-F: doc/guides/regexdevs/features/octeontx2.ini
+F: drivers/regex/cn9k/
+F: doc/guides/regexdevs/cn9k.rst
+F: doc/guides/regexdevs/features/cn9k.ini
 
 Mellanox mlx5
 M: Ori Kam <orika@nvidia.com>
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 88995cc70c..5213df3ccd 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
 #. **Dmadev Driver**
    See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
 
+#. **Regex Device Driver**
+   See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 3a3d28571c..5ab43abbdd 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -155,9 +155,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
 #. **Crypto Device Driver**
    See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
-#. **Regex Device Driver**
-   See :doc:`../regexdevs/octeontx2` for REE regex device driver information.
-
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst
similarity index 69%
rename from doc/guides/regexdevs/octeontx2.rst
rename to doc/guides/regexdevs/cn9k.rst
index b39d457d60..c23c295b93 100644
--- a/doc/guides/regexdevs/octeontx2.rst
+++ b/doc/guides/regexdevs/cn9k.rst
@@ -1,20 +1,20 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
     Copyright(c) 2020 Marvell International Ltd.
 
-OCTEON TX2 REE Regexdev Driver
+CN9K REE Regexdev Driver
 ==============================
 
-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode
-regexdev driver support for the inbuilt regex device found in the **Marvell OCTEON TX2**
+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode
+regexdev driver support for the inbuilt regex device found in the **Marvell CN9K**
 SoC family.
 
-More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+More information about CN9K SoC can be found at `Marvell Official Website
 <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
 
 Features
 --------
 
-Features of the OCTEON TX2 REE PMD are:
+Features of the CN9K REE PMD are:
 
 - 36 queues
 - Up to 254 matches for each regex operation
@@ -22,12 +22,12 @@ Features of the OCTEON TX2 REE PMD are:
 Prerequisites and Compilation procedure
 ---------------------------------------
 
-   See :doc:`../platform/octeontx2` for setup information.
+   See :doc:`../platform/cnxk` for setup information.
 
 Device Setup
 ------------
 
-The OCTEON TX2 REE devices will need to be bound to a user-space IO driver
+The CN9K REE devices will need to be bound to a user-space IO driver
 for use. The script ``dpdk-devbind.py`` script included with DPDK can be
 used to view the state of the devices and to bind them to a suitable
 DPDK-supported kernel driver. When querying the status of the devices,
@@ -38,12 +38,12 @@ those devices alone.
 Debugging Options
 -----------------
 
-.. _table_octeontx2_regex_debug_options:
+.. _table_cn9k_regex_debug_options:
 
-.. table:: OCTEON TX2 regex device debug options
+.. table:: CN9K regex device debug options
 
    +---+------------+-------------------------------------------------------+
    | # | Component  | EAL log command                                       |
    +===+============+=======================================================+
-   | 1 | REE        | --log-level='pmd\.regex\.octeontx2,8'                 |
+   | 1 | REE        | --log-level='pmd\.regex\.cn9k,8'                      |
    +---+------------+-------------------------------------------------------+
diff --git a/doc/guides/regexdevs/features/octeontx2.ini b/doc/guides/regexdevs/features/cn9k.ini
similarity index 80%
rename from doc/guides/regexdevs/features/octeontx2.ini
rename to doc/guides/regexdevs/features/cn9k.ini
index c9b421a16d..b029af8ac2 100644
--- a/doc/guides/regexdevs/features/octeontx2.ini
+++ b/doc/guides/regexdevs/features/cn9k.ini
@@ -1,5 +1,5 @@
 ;
-; Supported features of the 'octeontx2' regex driver.
+; Supported features of the 'cn9k' regex driver.
 ;
 ; Refer to default.ini for the full list of available driver features.
 ;
diff --git a/doc/guides/regexdevs/index.rst b/doc/guides/regexdevs/index.rst
index b1abc826bd..11a33fc09e 100644
--- a/doc/guides/regexdevs/index.rst
+++ b/doc/guides/regexdevs/index.rst
@@ -13,4 +13,4 @@ which can be used from an application through RegEx API.
 
    features_overview
    mlx5
-   octeontx2
+   cn9k
diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index 90cc3ed680..d6d40c31df 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -290,7 +290,7 @@ New Features
 
   Added a new PMD driver for the hardware regex offload block for OCTEON TX2 SoC.
 
-  See the :doc:`../regexdevs/octeontx2` for more details.
+  See ``regexdevs/octeontx2`` for more details.
 
 * **Updated Software Eventdev driver.**
 
diff --git a/drivers/regex/octeontx2/otx2_regexdev.c b/drivers/regex/cn9k/cn9k_regexdev.c
similarity index 61%
rename from drivers/regex/octeontx2/otx2_regexdev.c
rename to drivers/regex/cn9k/cn9k_regexdev.c
index b6e55853e9..32d20c1be8 100644
--- a/drivers/regex/octeontx2/otx2_regexdev.c
+++ b/drivers/regex/cn9k/cn9k_regexdev.c
@@ -13,12 +13,8 @@
 
 
 /* REE common headers */
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 
 /* HW matches are at offset 0x80 from RES_PTR_ADDR
@@ -35,9 +31,6 @@
 #define REE_MAX_RULES_PER_GROUP 0xFFFF
 #define REE_MAX_GROUPS 0xFFFF
 
-/* This is temporarily here */
-#define REE0_PF	19
-#define REE1_PF	20
 
 #define REE_RULE_DB_VERSION	2
 #define REE_RULE_DB_REVISION	0
@@ -58,32 +51,32 @@ struct ree_rule_db {
 static void
 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
 {
-	snprintf(name, size, "otx2_ree_lf_mem_%u:%u", dev_id, qp_id);
+	snprintf(name, size, "cn9k_ree_lf_mem_%u:%u", dev_id, qp_id);
 }
 
-static struct otx2_ree_qp *
+static struct roc_ree_qp *
 ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
-	struct otx2_ree_vf *vf = &data->vf;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct rte_memzone *lf_mem;
 	uint32_t len, iq_len, size_div2;
 	char name[RTE_MEMZONE_NAMESIZE];
 	uint64_t used_len, iova;
-	struct otx2_ree_qp *qp;
+	struct roc_ree_qp *qp;
 	uint8_t *va;
 	int ret;
 
 	/* Allocate queue pair */
-	qp = rte_zmalloc("OCTEON TX2 Regex PMD Queue Pair", sizeof(*qp),
-				OTX2_ALIGN);
+	qp = rte_zmalloc("CN9K Regex PMD Queue Pair", sizeof(*qp),
+				ROC_ALIGN);
 	if (qp == NULL) {
-		otx2_err("Could not allocate queue pair");
+		cn9k_err("Could not allocate queue pair");
 		return NULL;
 	}
 
-	iq_len = OTX2_REE_IQ_LEN;
+	iq_len = REE_IQ_LEN;
 
 	/*
 	 * Queue size must be in units of 128B 2 * REE_INST_S (which is 64B),
@@ -93,13 +86,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	size_div2 = iq_len >> 1;
 
 	/* For pending queue */
-	len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 
 	/* So that instruction queues start as pg size aligned */
 	len = RTE_ALIGN(len, pg_sz);
 
 	/* For instruction queues */
-	len += OTX2_REE_IQ_LEN * sizeof(union otx2_ree_inst);
+	len += REE_IQ_LEN * sizeof(union roc_ree_inst);
 
 	/* Waste after instruction queues */
 	len = RTE_ALIGN(len, pg_sz);
@@ -107,11 +100,11 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp_id);
 
-	lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
+	lf_mem = rte_memzone_reserve_aligned(name, len, rte_socket_id(),
 			RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
 			RTE_CACHE_LINE_SIZE);
 	if (lf_mem == NULL) {
-		otx2_err("Could not allocate reserved memzone");
+		cn9k_err("Could not allocate reserved memzone");
 		goto qp_free;
 	}
 
@@ -121,24 +114,24 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	memset(va, 0, len);
 
 	/* Initialize pending queue */
-	qp->pend_q.rid_queue = (struct otx2_ree_rid *)va;
+	qp->pend_q.rid_queue = (struct roc_ree_rid *)va;
 	qp->pend_q.enq_tail = 0;
 	qp->pend_q.deq_head = 0;
 	qp->pend_q.pending_count = 0;
 
-	used_len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	used_len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 	used_len = RTE_ALIGN(used_len, pg_sz);
 	iova += used_len;
 
 	qp->iq_dma_addr = iova;
 	qp->id = qp_id;
-	qp->base = OTX2_REE_LF_BAR2(vf, qp_id);
-	qp->otx2_regexdev_jobid = 0;
+	qp->base = roc_ree_qp_get_base(vf, qp_id);
+	qp->roc_regexdev_jobid = 0;
 	qp->write_offset = 0;
 
-	ret = otx2_ree_iq_enable(dev, qp, OTX2_REE_QUEUE_HI_PRIO, size_div2);
+	ret = roc_ree_iq_enable(vf, qp, REE_QUEUE_HI_PRIO, size_div2);
 	if (ret) {
-		otx2_err("Could not enable instruction queue");
+		cn9k_err("Could not enable instruction queue");
 		goto qp_free;
 	}
 
@@ -150,13 +143,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 }
 
 static int
-ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
+ree_qp_destroy(const struct rte_regexdev *dev, struct roc_ree_qp *qp)
 {
 	const struct rte_memzone *lf_mem;
 	char name[RTE_MEMZONE_NAMESIZE];
 	int ret;
 
-	otx2_ree_iq_disable(qp);
+	roc_ree_iq_disable(qp);
 
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp->id);
@@ -175,8 +168,8 @@ ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
 static int
 ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
 	int ret;
 
 	ree_func_trace("Queue=%d", qp_id);
@@ -186,7 +179,7 @@ ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 
 	ret = ree_qp_destroy(dev, qp);
 	if (ret) {
-		otx2_err("Could not destroy queue pair %d", qp_id);
+		cn9k_err("Could not destroy queue pair %d", qp_id);
 		return ret;
 	}
 
@@ -200,12 +193,12 @@ ree_dev_register(const char *name)
 {
 	struct rte_regexdev *dev;
 
-	otx2_ree_dbg("Creating regexdev %s\n", name);
+	cn9k_ree_dbg("Creating regexdev %s\n", name);
 
 	/* allocate device structure */
 	dev = rte_regexdev_register(name);
 	if (dev == NULL) {
-		otx2_err("Failed to allocate regex device for %s", name);
+		cn9k_err("Failed to allocate regex device for %s", name);
 		return NULL;
 	}
 
@@ -213,12 +206,12 @@ ree_dev_register(const char *name)
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		dev->data->dev_private =
 				rte_zmalloc_socket("regexdev device private",
-						sizeof(struct otx2_ree_data),
+						sizeof(struct cn9k_ree_data),
 						RTE_CACHE_LINE_SIZE,
 						rte_socket_id());
 
 		if (dev->data->dev_private == NULL) {
-			otx2_err("Cannot allocate memory for dev %s private data",
+			cn9k_err("Cannot allocate memory for dev %s private data",
 					name);
 
 			rte_regexdev_unregister(dev);
@@ -232,7 +225,7 @@ ree_dev_register(const char *name)
 static int
 ree_dev_unregister(struct rte_regexdev *dev)
 {
-	otx2_ree_dbg("Closing regex device %s", dev->device->name);
+	cn9k_ree_dbg("Closing regex device %s", dev->device->name);
 
 	/* free regex device */
 	rte_regexdev_unregister(dev);
@@ -246,8 +239,8 @@ ree_dev_unregister(struct rte_regexdev *dev)
 static int
 ree_dev_fini(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct rte_pci_device *pci_dev;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	int i, ret;
 
 	ree_func_trace();
@@ -258,9 +251,9 @@ ree_dev_fini(struct rte_regexdev *dev)
 			return ret;
 	}
 
-	ret = otx2_ree_queues_detach(dev);
+	ret = roc_ree_queues_detach(vf);
 	if (ret)
-		otx2_err("Could not detach queues");
+		cn9k_err("Could not detach queues");
 
 	/* TEMP : should be in lib */
 	if (data->queue_pairs)
@@ -268,33 +261,32 @@ ree_dev_fini(struct rte_regexdev *dev)
 	if (data->rules)
 		rte_free(data->rules);
 
-	pci_dev = container_of(dev->device, struct rte_pci_device, device);
-	otx2_dev_fini(pci_dev, &(data->vf.otx2_dev));
+	roc_ree_dev_fini(vf);
 
 	ret = ree_dev_unregister(dev);
 	if (ret)
-		otx2_err("Could not destroy PMD");
+		cn9k_err("Could not destroy PMD");
 
 	return ret;
 }
 
 static inline int
-ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
-		 struct otx2_ree_pending_queue *pend_q)
+ree_enqueue(struct roc_ree_qp *qp, struct rte_regex_ops *op,
+		 struct roc_ree_pending_queue *pend_q)
 {
-	union otx2_ree_inst inst;
-	union otx2_ree_res *res;
+	union roc_ree_inst inst;
+	union ree_res *res;
 	uint32_t offset;
 
-	if (unlikely(pend_q->pending_count >= OTX2_REE_DEFAULT_CMD_QLEN)) {
-		otx2_err("Pending count %" PRIu64 " is greater than Q size %d",
-		pend_q->pending_count, OTX2_REE_DEFAULT_CMD_QLEN);
+	if (unlikely(pend_q->pending_count >= REE_DEFAULT_CMD_QLEN)) {
+		cn9k_err("Pending count %" PRIu64 " is greater than Q size %d",
+		pend_q->pending_count, REE_DEFAULT_CMD_QLEN);
 		return -EAGAIN;
 	}
-	if (unlikely(op->mbuf->data_len > OTX2_REE_MAX_PAYLOAD_SIZE ||
+	if (unlikely(op->mbuf->data_len > REE_MAX_PAYLOAD_SIZE ||
 			op->mbuf->data_len == 0)) {
-		otx2_err("Packet length %d is greater than MAX payload %d",
-				op->mbuf->data_len, OTX2_REE_MAX_PAYLOAD_SIZE);
+		cn9k_err("Packet length %d is greater than MAX payload %d",
+				op->mbuf->data_len, REE_MAX_PAYLOAD_SIZE);
 		return -EAGAIN;
 	}
 
@@ -324,7 +316,7 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 		inst.cn98xx.ree_job_ctrl = (0x1 << 8);
 	else
 		inst.cn98xx.ree_job_ctrl = 0;
-	inst.cn98xx.ree_job_id = qp->otx2_regexdev_jobid;
+	inst.cn98xx.ree_job_id = qp->roc_regexdev_jobid;
 	/* W 7 */
 	inst.cn98xx.ree_job_subset_id_0 = op->group_id0;
 	if (op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F)
@@ -348,33 +340,33 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 	pend_q->rid_queue[pend_q->enq_tail].user_id = op->user_id;
 
 	/* Mark result as not done */
-	res = (union otx2_ree_res *)(op);
+	res = (union ree_res *)(op);
 	res->s.done = 0;
 	res->s.ree_err = 0;
 
 	/* We will use soft queue length here to limit requests */
-	REE_MOD_INC(pend_q->enq_tail, OTX2_REE_DEFAULT_CMD_QLEN);
+	REE_MOD_INC(pend_q->enq_tail, REE_DEFAULT_CMD_QLEN);
 	pend_q->pending_count += 1;
-	REE_MOD_INC(qp->otx2_regexdev_jobid, 0xFFFFFF);
-	REE_MOD_INC(qp->write_offset, OTX2_REE_IQ_LEN);
+	REE_MOD_INC(qp->roc_regexdev_jobid, 0xFFFFFF);
+	REE_MOD_INC(qp->write_offset, REE_IQ_LEN);
 
 	return 0;
 }
 
 static uint16_t
-otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	uint16_t nb_allowed, count = 0;
 	struct rte_regex_ops *op;
 	int ret;
 
 	pend_q = &qp->pend_q;
 
-	nb_allowed = OTX2_REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
+	nb_allowed = REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
 	if (nb_ops > nb_allowed)
 		nb_ops = nb_allowed;
 
@@ -392,7 +384,7 @@ otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 	rte_io_wmb();
 
 	/* Update Doorbell */
-	otx2_write64(count, qp->base + OTX2_REE_LF_DOORBELL);
+	plt_write64(count, qp->base + REE_LF_DOORBELL);
 
 	return count;
 }
@@ -422,15 +414,15 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 	}
 
 	if (unlikely(ree_res_status != REE_TYPE_RESULT_DESC)) {
-		if (ree_res_status & OTX2_REE_STATUS_PMI_SOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_SOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_PMI_EOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_EOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_ML_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_ML_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F;
-		if (ree_res_status & OTX2_REE_STATUS_MM_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MM_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F;
-		if (ree_res_status & OTX2_REE_STATUS_MP_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MP_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F;
 	}
 	if (ops->nb_matches > 0) {
@@ -439,22 +431,22 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 			ops->nb_matches : REE_NUM_MATCHES_ALIGN);
 		match = (uint64_t)ops + REE_MATCH_OFFSET;
 		match += (ops->nb_matches - off) *
-			sizeof(union otx2_ree_match);
+			sizeof(union ree_match);
 		memcpy((void *)ops->matches, (void *)match,
-			off * sizeof(union otx2_ree_match));
+			off * sizeof(union ree_match));
 	}
 }
 
 static uint16_t
-otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	int i, nb_pending, nb_completed = 0;
 	volatile struct ree_res_s_98 *res;
-	struct otx2_ree_rid *rid;
+	struct roc_ree_rid *rid;
 
 	pend_q = &qp->pend_q;
 
@@ -474,7 +466,7 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		ops[i] = (struct rte_regex_ops *)(rid->rid);
 		ops[i]->user_id = rid->user_id;
 
-		REE_MOD_INC(pend_q->deq_head, OTX2_REE_DEFAULT_CMD_QLEN);
+		REE_MOD_INC(pend_q->deq_head, REE_DEFAULT_CMD_QLEN);
 		pend_q->pending_count -= 1;
 	}
 
@@ -487,10 +479,10 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 }
 
 static int
-otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
+cn9k_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 
 	ree_func_trace();
 
@@ -502,7 +494,7 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 
 	info->max_queue_pairs = vf->max_queues;
 	info->max_matches = vf->max_matches;
-	info->max_payload_size = OTX2_REE_MAX_PAYLOAD_SIZE;
+	info->max_payload_size = REE_MAX_PAYLOAD_SIZE;
 	info->max_rules_per_group = data->max_rules_per_group;
 	info->max_groups = data->max_groups;
 	info->regexdev_capa = data->regexdev_capa;
@@ -512,11 +504,11 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 }
 
 static int
-otx2_ree_dev_config(struct rte_regexdev *dev,
+cn9k_ree_dev_config(struct rte_regexdev *dev,
 		    const struct rte_regexdev_config *cfg)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *rule_db;
 	uint32_t rule_db_len;
 	int ret;
@@ -524,29 +516,29 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	ree_func_trace();
 
 	if (cfg->nb_queue_pairs > vf->max_queues) {
-		otx2_err("Invalid number of queue pairs requested");
+		cn9k_err("Invalid number of queue pairs requested");
 		return -EINVAL;
 	}
 
 	if (cfg->nb_max_matches != vf->max_matches) {
-		otx2_err("Invalid number of max matches requested");
+		cn9k_err("Invalid number of max matches requested");
 		return -EINVAL;
 	}
 
 	if (cfg->dev_cfg_flags != 0) {
-		otx2_err("Invalid device configuration flags requested");
+		cn9k_err("Invalid device configuration flags requested");
 		return -EINVAL;
 	}
 
 	/* Unregister error interrupts */
 	if (vf->err_intr_registered)
-		otx2_ree_err_intr_unregister(dev);
+		roc_ree_err_intr_unregister(vf);
 
 	/* Detach queues */
 	if (vf->nb_queues) {
-		ret = otx2_ree_queues_detach(dev);
+		ret = roc_ree_queues_detach(vf);
 		if (ret) {
-			otx2_err("Could not detach REE queues");
+			cn9k_err("Could not detach REE queues");
 			return ret;
 		}
 	}
@@ -559,7 +551,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 
 		if (data->queue_pairs == NULL) {
 			data->nb_queue_pairs = 0;
-			otx2_err("Failed to get memory for qp meta data, nb_queues %u",
+			cn9k_err("Failed to get memory for qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -579,7 +571,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 		qp = rte_realloc(qp, sizeof(qp[0]) * cfg->nb_queue_pairs,
 				RTE_CACHE_LINE_SIZE);
 		if (qp == NULL) {
-			otx2_err("Failed to realloc qp meta data, nb_queues %u",
+			cn9k_err("Failed to realloc qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -594,52 +586,52 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	data->nb_queue_pairs = cfg->nb_queue_pairs;
 
 	/* Attach queues */
-	otx2_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
-	ret = otx2_ree_queues_attach(dev, cfg->nb_queue_pairs);
+	cn9k_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
+	ret = roc_ree_queues_attach(vf, cfg->nb_queue_pairs);
 	if (ret) {
-		otx2_err("Could not attach queues");
+		cn9k_err("Could not attach queues");
 		return -ENODEV;
 	}
 
-	ret = otx2_ree_msix_offsets_get(dev);
+	ret = roc_ree_msix_offsets_get(vf);
 	if (ret) {
-		otx2_err("Could not get MSI-X offsets");
+		cn9k_err("Could not get MSI-X offsets");
 		goto queues_detach;
 	}
 
 	if (cfg->rule_db && cfg->rule_db_len) {
-		otx2_ree_dbg("rule_db length %d", cfg->rule_db_len);
+		cn9k_ree_dbg("rule_db length %d", cfg->rule_db_len);
 		rule_db = (const struct ree_rule_db *)cfg->rule_db;
 		rule_db_len = rule_db->number_of_entries *
 				sizeof(struct ree_rule_db_entry);
-		otx2_ree_dbg("rule_db number of entries %d",
+		cn9k_ree_dbg("rule_db number of entries %d",
 				rule_db->number_of_entries);
 		if (rule_db_len > cfg->rule_db_len) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			ret = -EINVAL;
 			goto queues_detach;
 		}
-		ret = otx2_ree_rule_db_prog(dev, (const char *)rule_db->entries,
-				rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+		ret = roc_ree_rule_db_prog(vf, (const char *)rule_db->entries,
+				rule_db_len, NULL, REE_NON_INC_PROG);
 		if (ret) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			goto queues_detach;
 		}
 	}
 
-	dev->enqueue = otx2_ree_enqueue_burst;
-	dev->dequeue = otx2_ree_dequeue_burst;
+	dev->enqueue = cn9k_ree_enqueue_burst;
+	dev->dequeue = cn9k_ree_dequeue_burst;
 
 	rte_mb();
 	return 0;
 
 queues_detach:
-	otx2_ree_queues_detach(dev);
+	roc_ree_queues_detach(vf);
 	return ret;
 }
 
 static int
-otx2_ree_stop(struct rte_regexdev *dev)
+cn9k_ree_stop(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 
@@ -648,18 +640,20 @@ otx2_ree_stop(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_start(struct rte_regexdev *dev)
+cn9k_ree_start(struct rte_regexdev *dev)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	uint32_t rule_db_len = 0;
 	int ret;
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, NULL);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, NULL);
 	if (ret)
 		return ret;
 	if (rule_db_len == 0) {
-		otx2_err("Rule db not programmed");
+		cn9k_err("Rule db not programmed");
 		return -EFAULT;
 	}
 
@@ -667,56 +661,55 @@ otx2_ree_start(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_close(struct rte_regexdev *dev)
+cn9k_ree_close(struct rte_regexdev *dev)
 {
 	return ree_dev_fini(dev);
 }
 
 static int
-otx2_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
 		const struct rte_regexdev_qp_conf *qp_conf)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp;
 
 	ree_func_trace("Queue=%d", qp_id);
 
 	if (data->queue_pairs[qp_id] != NULL)
 		ree_queue_pair_release(dev, qp_id);
 
-	if (qp_conf->nb_desc > OTX2_REE_DEFAULT_CMD_QLEN) {
-		otx2_err("Could not setup queue pair for %u descriptors",
+	if (qp_conf->nb_desc > REE_DEFAULT_CMD_QLEN) {
+		cn9k_err("Could not setup queue pair for %u descriptors",
 				qp_conf->nb_desc);
 		return -EINVAL;
 	}
 	if (qp_conf->qp_conf_flags != 0) {
-		otx2_err("Could not setup queue pair with configuration flags 0x%x",
+		cn9k_err("Could not setup queue pair with configuration flags 0x%x",
 				qp_conf->qp_conf_flags);
 		return -EINVAL;
 	}
 
 	qp = ree_qp_create(dev, qp_id);
 	if (qp == NULL) {
-		otx2_err("Could not create queue pair %d", qp_id);
+		cn9k_err("Could not create queue pair %d", qp_id);
 		return -ENOMEM;
 	}
-	qp->cb = qp_conf->cb;
 	data->queue_pairs[qp_id] = qp;
 
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_compile_activate(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_activate(struct rte_regexdev *dev)
 {
-	return otx2_ree_rule_db_compile_prog(dev);
+	return cn9k_ree_rule_db_compile_prog(dev);
 }
 
 static int
-otx2_ree_rule_db_update(struct rte_regexdev *dev,
+cn9k_ree_rule_db_update(struct rte_regexdev *dev,
 		const struct rte_regexdev_rule *rules, uint16_t nb_rules)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	struct rte_regexdev_rule *old_ptr;
 	uint32_t i, sum_nb_rules;
 
@@ -770,10 +763,11 @@ otx2_ree_rule_db_update(struct rte_regexdev *dev,
 }
 
 static int
-otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
+cn9k_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 		uint32_t rule_db_len)
 {
-
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *ree_rule_db;
 	uint32_t ree_rule_db_len;
 	int ret;
@@ -784,21 +778,23 @@ otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 	ree_rule_db_len = ree_rule_db->number_of_entries *
 			sizeof(struct ree_rule_db_entry);
 	if (ree_rule_db_len > rule_db_len) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -EINVAL;
 	}
-	ret = otx2_ree_rule_db_prog(dev, (const char *)ree_rule_db->entries,
-			ree_rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+	ret = roc_ree_rule_db_prog(vf, (const char *)ree_rule_db->entries,
+			ree_rule_db_len, NULL, REE_NON_INC_PROG);
 	if (ret) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -ENOSPC;
 	}
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
+cn9k_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	struct ree_rule_db *ree_rule_db;
 	uint32_t rule_dbi_len;
 	uint32_t rule_db_len;
@@ -806,7 +802,7 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret)
 		return ret;
 
@@ -816,10 +812,10 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	}
 
 	ree_rule_db = (struct ree_rule_db *)rule_db;
-	ret = otx2_ree_rule_db_get(dev, (char *)ree_rule_db->entries,
+	ret = roc_ree_rule_db_get(vf, (char *)ree_rule_db->entries,
 			rule_db_len, NULL, 0);
 	if (ret) {
-		otx2_err("Could not export rule db");
+		cn9k_err("Could not export rule db");
 		return -EFAULT;
 	}
 	ree_rule_db->number_of_entries =
@@ -830,55 +826,44 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	return 0;
 }
 
-static int
-ree_get_blkaddr(struct otx2_dev *dev)
-{
-	int pf;
-
-	pf = otx2_get_pf(dev->pf_func);
-	if (pf == REE0_PF)
-		return RVU_BLOCK_ADDR_REE0;
-	else if (pf == REE1_PF)
-		return RVU_BLOCK_ADDR_REE1;
-	else
-		return 0;
-}
-
-static struct rte_regexdev_ops otx2_ree_ops = {
-		.dev_info_get = otx2_ree_dev_info_get,
-		.dev_configure = otx2_ree_dev_config,
-		.dev_qp_setup = otx2_ree_queue_pair_setup,
-		.dev_start = otx2_ree_start,
-		.dev_stop = otx2_ree_stop,
-		.dev_close = otx2_ree_close,
-		.dev_attr_get = NULL,
-		.dev_attr_set = NULL,
-		.dev_rule_db_update = otx2_ree_rule_db_update,
-		.dev_rule_db_compile_activate =
-				otx2_ree_rule_db_compile_activate,
-		.dev_db_import = otx2_ree_rule_db_import,
-		.dev_db_export = otx2_ree_rule_db_export,
-		.dev_xstats_names_get = NULL,
-		.dev_xstats_get = NULL,
-		.dev_xstats_by_name_get = NULL,
-		.dev_xstats_reset = NULL,
-		.dev_selftest = NULL,
-		.dev_dump = NULL,
+static struct rte_regexdev_ops cn9k_ree_ops = {
+	.dev_info_get = cn9k_ree_dev_info_get,
+	.dev_configure = cn9k_ree_dev_config,
+	.dev_qp_setup = cn9k_ree_queue_pair_setup,
+	.dev_start = cn9k_ree_start,
+	.dev_stop = cn9k_ree_stop,
+	.dev_close = cn9k_ree_close,
+	.dev_attr_get = NULL,
+	.dev_attr_set = NULL,
+	.dev_rule_db_update = cn9k_ree_rule_db_update,
+	.dev_rule_db_compile_activate =
+			cn9k_ree_rule_db_compile_activate,
+	.dev_db_import = cn9k_ree_rule_db_import,
+	.dev_db_export = cn9k_ree_rule_db_export,
+	.dev_xstats_names_get = NULL,
+	.dev_xstats_get = NULL,
+	.dev_xstats_by_name_get = NULL,
+	.dev_xstats_reset = NULL,
+	.dev_selftest = NULL,
+	.dev_dump = NULL,
 };
 
 static int
-otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+cn9k_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		   struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
-	struct otx2_ree_data *data;
-	struct otx2_dev *otx2_dev;
+	struct cn9k_ree_data *data;
 	struct rte_regexdev *dev;
-	uint8_t max_matches = 0;
-	struct otx2_ree_vf *vf;
-	uint16_t nb_queues = 0;
+	struct roc_ree_vf *vf;
 	int ret;
 
+	ret = roc_plt_init();
+	if (ret < 0) {
+		plt_err("Failed to initialize platform model");
+		return ret;
+	}
+
 	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
 
 	dev = ree_dev_register(name);
@@ -887,63 +872,19 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		goto exit;
 	}
 
-	dev->dev_ops = &otx2_ree_ops;
+	dev->dev_ops = &cn9k_ree_ops;
 	dev->device = &pci_dev->device;
 
 	/* Get private data space allocated */
 	data = dev->data->dev_private;
 	vf = &data->vf;
-
-	otx2_dev = &vf->otx2_dev;
-
-	/* Initialize the base otx2_dev object */
-	ret = otx2_dev_init(pci_dev, otx2_dev);
+	vf->pci_dev = pci_dev;
+	ret = roc_ree_dev_init(vf);
 	if (ret) {
-		otx2_err("Could not initialize otx2_dev");
+		plt_err("Failed to initialize roc cpt rc=%d", ret);
 		goto dev_unregister;
 	}
-	/* Get REE block address */
-	vf->block_address = ree_get_blkaddr(otx2_dev);
-	if (!vf->block_address) {
-		otx2_err("Could not determine block PF number");
-		goto otx2_dev_fini;
-	}
-
-	/* Get number of queues available on the device */
-	ret = otx2_ree_available_queues_get(dev, &nb_queues);
-	if (ret) {
-		otx2_err("Could not determine the number of queues available");
-		goto otx2_dev_fini;
-	}
-
-	/* Don't exceed the limits set per VF */
-	nb_queues = RTE_MIN(nb_queues, OTX2_REE_MAX_QUEUES_PER_VF);
-
-	if (nb_queues == 0) {
-		otx2_err("No free queues available on the device");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_queues = nb_queues;
-
-	otx2_ree_dbg("Max queues supported by device: %d", vf->max_queues);
-
-	/* Get number of maximum matches supported on the device */
-	ret = otx2_ree_max_matches_get(dev, &max_matches);
-	if (ret) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-	/* Don't exceed the limits set per VF */
-	max_matches = RTE_MIN(max_matches, OTX2_REE_MAX_MATCHES_PER_VF);
-	if (max_matches == 0) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_matches = max_matches;
 
-	otx2_ree_dbg("Max matches supported by device: %d", vf->max_matches);
 	data->rule_flags = RTE_REGEX_PCRE_RULE_ALLOW_EMPTY_F |
 			RTE_REGEX_PCRE_RULE_ANCHORED_F;
 	data->regexdev_capa = 0;
@@ -954,18 +895,16 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	dev->state = RTE_REGEXDEV_READY;
 	return 0;
 
-otx2_dev_fini:
-	otx2_dev_fini(pci_dev, otx2_dev);
 dev_unregister:
 	ree_dev_unregister(dev);
 exit:
-	otx2_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
+	cn9k_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
 		    pci_dev->id.vendor_id, pci_dev->id.device_id);
 	return ret;
 }
 
 static int
-otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
+cn9k_ree_pci_remove(struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
 	struct rte_regexdev *dev = NULL;
@@ -986,20 +925,20 @@ otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
 static struct rte_pci_id pci_id_ree_table[] = {
 	{
 		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-				PCI_DEVID_OCTEONTX2_RVU_REE_PF)
+				PCI_DEVID_CNXK_RVU_REE_PF)
 	},
 	{
 		.vendor_id = 0,
 	}
 };
 
-static struct rte_pci_driver otx2_regexdev_pmd = {
+static struct rte_pci_driver cn9k_regexdev_pmd = {
 	.id_table = pci_id_ree_table,
 	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
-	.probe = otx2_ree_pci_probe,
-	.remove = otx2_ree_pci_remove,
+	.probe = cn9k_ree_pci_probe,
+	.remove = cn9k_ree_pci_remove,
 };
 
 
-RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_OCTEONTX2_PMD, otx2_regexdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_OCTEONTX2_PMD, pci_id_ree_table);
+RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_CN9K_PMD, cn9k_regexdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_CN9K_PMD, pci_id_ree_table);
diff --git a/drivers/regex/cn9k/cn9k_regexdev.h b/drivers/regex/cn9k/cn9k_regexdev.h
new file mode 100644
index 0000000000..c715502167
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_H_
+#define _CN9K_REGEXDEV_H_
+
+#include <rte_common.h>
+#include <rte_regexdev.h>
+
+#include "roc_api.h"
+
+#define cn9k_ree_dbg plt_ree_dbg
+#define cn9k_err plt_err
+
+#define ree_func_trace cn9k_ree_dbg
+
+/* Marvell CN9K Regex PMD device name */
+#define REGEXDEV_NAME_CN9K_PMD	regex_cn9k
+
+/**
+ * Device private data
+ */
+struct cn9k_ree_data {
+	uint32_t regexdev_capa;
+	uint64_t rule_flags;
+	/**< Feature flags exposes HW/SW features for the given device */
+	uint16_t max_rules_per_group;
+	/**< Maximum rules supported per subset by this device */
+	uint16_t max_groups;
+	/**< Maximum subset supported by this device */
+	void **queue_pairs;
+	/**< Array of pointers to queue pairs. */
+	uint16_t nb_queue_pairs;
+	/**< Number of device queue pairs. */
+	struct roc_ree_vf vf;
+	/**< vf data */
+	struct rte_regexdev_rule *rules;
+	/**< rules to be compiled */
+	uint16_t nb_rules;
+	/**< number of rules */
+} __rte_cache_aligned;
+
+#endif /* _CN9K_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.c b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
similarity index 86%
rename from drivers/regex/octeontx2/otx2_regexdev_compiler.c
rename to drivers/regex/cn9k/cn9k_regexdev_compiler.c
index 785459f741..935b8a53b4 100644
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.c
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
@@ -5,9 +5,8 @@
 #include <rte_malloc.h>
 #include <rte_regexdev.h>
 
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 #ifdef REE_COMPILER_SDK
 #include <rxp-compiler.h>
@@ -65,7 +64,7 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 			nb_rules*sizeof(struct rxp_rule_entry), 0);
 
 	if (ruleset.rules == NULL) {
-		otx2_err("Could not allocate memory for rule compilation\n");
+		cn9k_err("Could not allocate memory for rule compilation\n");
 		return -EFAULT;
 	}
 	if (rof_for_incremental_compile)
@@ -126,9 +125,10 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 }
 
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	char compiler_version[] = "20.5.2.eda0fa2";
 	char timestamp[] = "19700101_000001";
 	uint32_t rule_db_len, rule_dbi_len;
@@ -144,25 +144,25 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret != 0) {
-		otx2_err("Could not get rule db length");
+		cn9k_err("Could not get rule db length");
 		return ret;
 	}
 
 	if (rule_db_len > 0) {
-		otx2_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
+		cn9k_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
 				rule_db_len, rule_dbi_len);
 		rule_db = rte_malloc("ree_rule_db", rule_db_len, 0);
 		if (!rule_db) {
-			otx2_err("Could not allocate memory for rule db");
+			cn9k_err("Could not allocate memory for rule db");
 			return -EFAULT;
 		}
 
-		ret = otx2_ree_rule_db_get(dev, rule_db, rule_db_len,
+		ret = roc_ree_rule_db_get(vf, rule_db, rule_db_len,
 				(char *)rule_dbi, rule_dbi_len);
 		if (ret) {
-			otx2_err("Could not read rule db");
+			cn9k_err("Could not read rule db");
 			rte_free(rule_db);
 			return -EFAULT;
 		}
@@ -188,7 +188,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 		ret = ree_rule_db_compile(data->rules, data->nb_rules, &rof,
 				&rofi, &rof_inc, rofi_inc_p);
 		if (rofi->number_of_entries == 0) {
-			otx2_ree_dbg("No change to rule db");
+			cn9k_ree_dbg("No change to rule db");
 			ret = 0;
 			goto free_structs;
 		}
@@ -201,14 +201,14 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 				&rofi, NULL, NULL);
 	}
 	if (ret != 0) {
-		otx2_err("Could not compile rule db");
+		cn9k_err("Could not compile rule db");
 		goto free_structs;
 	}
 	rule_db_len = rof->number_of_entries * sizeof(struct rxp_rof_entry);
-	ret = otx2_ree_rule_db_prog(dev, (char *)rof->rof_entries, rule_db_len,
+	ret = roc_ree_rule_db_prog(vf, (char *)rof->rof_entries, rule_db_len,
 			rofi_rof_entries, rule_dbi_len);
 	if (ret)
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 
 free_structs:
 	rxp_free_structs(NULL, NULL, NULL, NULL, NULL, &rof, NULL, &rofi, NULL,
@@ -221,7 +221,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 }
 #else
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 	return -ENOTSUP;
diff --git a/drivers/regex/cn9k/cn9k_regexdev_compiler.h b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
new file mode 100644
index 0000000000..4c29a69ada
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_COMPILER_H_
+#define _CN9K_REGEXDEV_COMPILER_H_
+
+int
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev);
+
+#endif /* _CN9K_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/meson.build b/drivers/regex/cn9k/meson.build
similarity index 65%
rename from drivers/regex/octeontx2/meson.build
rename to drivers/regex/cn9k/meson.build
index 3f81add5bf..bb0504fba1 100644
--- a/drivers/regex/octeontx2/meson.build
+++ b/drivers/regex/cn9k/meson.build
@@ -16,12 +16,10 @@ if lib.found()
 endif
 
 sources = files(
-        'otx2_regexdev.c',
-        'otx2_regexdev_compiler.c',
-        'otx2_regexdev_hw_access.c',
-        'otx2_regexdev_mbox.c',
+        'cn9k_regexdev.c',
+        'cn9k_regexdev_compiler.c',
 )
 
-deps += ['bus_pci', 'common_octeontx2', 'regexdev']
+deps += ['bus_pci', 'regexdev']
+deps += ['common_cnxk', 'mempool_cnxk']
 
-includes += include_directories('../../common/octeontx2')
diff --git a/drivers/regex/octeontx2/version.map b/drivers/regex/cn9k/version.map
similarity index 100%
rename from drivers/regex/octeontx2/version.map
rename to drivers/regex/cn9k/version.map
diff --git a/drivers/regex/meson.build b/drivers/regex/meson.build
index 94222e55fe..7ad55af8ca 100644
--- a/drivers/regex/meson.build
+++ b/drivers/regex/meson.build
@@ -3,6 +3,6 @@
 
 drivers = [
         'mlx5',
-        'octeontx2',
+        'cn9k',
 ]
 std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc
diff --git a/drivers/regex/octeontx2/otx2_regexdev.h b/drivers/regex/octeontx2/otx2_regexdev.h
deleted file mode 100644
index d710535f5f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_H_
-#define _OTX2_REGEXDEV_H_
-
-#include <rte_common.h>
-#include <rte_regexdev.h>
-
-#include "otx2_dev.h"
-
-#define ree_func_trace otx2_ree_dbg
-
-/* Marvell OCTEON TX2 Regex PMD device name */
-#define REGEXDEV_NAME_OCTEONTX2_PMD	regex_octeontx2
-
-#define OTX2_REE_MAX_LFS		36
-#define OTX2_REE_MAX_QUEUES_PER_VF	36
-#define OTX2_REE_MAX_MATCHES_PER_VF	254
-
-#define OTX2_REE_MAX_PAYLOAD_SIZE	(1 << 14)
-
-#define OTX2_REE_NON_INC_PROG 0
-#define OTX2_REE_INC_PROG 1
-
-#define REE_MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
-
-
-/**
- * Device vf data
- */
-struct otx2_ree_vf {
-	struct otx2_dev otx2_dev;
-	/**< Base class */
-	uint16_t max_queues;
-	/**< Max queues supported */
-	uint8_t nb_queues;
-	/**< Number of regex queues attached */
-	uint16_t max_matches;
-	/**<  Max matches supported*/
-	uint16_t lf_msixoff[OTX2_REE_MAX_LFS];
-	/**< MSI-X offsets */
-	uint8_t block_address;
-	/**< REE Block Address */
-	uint8_t err_intr_registered:1;
-	/**< Are error interrupts registered? */
-};
-
-/**
- * Device private data
- */
-struct otx2_ree_data {
-	uint32_t regexdev_capa;
-	uint64_t rule_flags;
-	/**< Feature flags exposes HW/SW features for the given device */
-	uint16_t max_rules_per_group;
-	/**< Maximum rules supported per subset by this device */
-	uint16_t max_groups;
-	/**< Maximum subset supported by this device */
-	void **queue_pairs;
-	/**< Array of pointers to queue pairs. */
-	uint16_t nb_queue_pairs;
-	/**< Number of device queue pairs. */
-	struct otx2_ree_vf vf;
-	/**< vf data */
-	struct rte_regexdev_rule *rules;
-	/**< rules to be compiled */
-	uint16_t nb_rules;
-	/**< number of rules */
-} __rte_cache_aligned;
-
-struct otx2_ree_rid {
-	uintptr_t rid;
-	/** Request id of a ree operation */
-	uint64_t user_id;
-	/* Client data */
-	/**< IOVA address of the pattern to be matched. */
-};
-
-struct otx2_ree_pending_queue {
-	uint64_t pending_count;
-	/** Pending requests count */
-	struct otx2_ree_rid *rid_queue;
-	/** Array of pending requests */
-	uint16_t enq_tail;
-	/** Tail of queue to be used for enqueue */
-	uint16_t deq_head;
-	/** Head of queue to be used for dequeue */
-};
-
-struct otx2_ree_qp {
-	uint32_t id;
-	/**< Queue pair id */
-	uintptr_t base;
-	/**< Base address where BAR is mapped */
-	struct otx2_ree_pending_queue pend_q;
-	/**< Pending queue */
-	rte_iova_t iq_dma_addr;
-	/**< Instruction queue address */
-	uint32_t otx2_regexdev_jobid;
-	/**< Job ID */
-	uint32_t write_offset;
-	/**< write offset */
-	regexdev_stop_flush_t cb;
-	/**< Callback function called during rte_regex_dev_stop()*/
-};
-
-#endif /* _OTX2_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.h b/drivers/regex/octeontx2/otx2_regexdev_compiler.h
deleted file mode 100644
index 8d2625bf7f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_COMPILER_H_
-#define _OTX2_REGEXDEV_COMPILER_H_
-
-int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev);
-
-#endif /* _OTX2_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c b/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
deleted file mode 100644
index f8031d0f72..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
-
-static void
-ree_lf_err_intr_handler(void *param)
-{
-	uintptr_t base = (uintptr_t)param;
-	uint8_t lf_id;
-	uint64_t intr;
-
-	lf_id = (base >> 12) & 0xFF;
-
-	intr = otx2_read64(base + OTX2_REE_LF_MISC_INT);
-	if (intr == 0)
-		return;
-
-	otx2_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
-
-	/* Clear interrupt */
-	otx2_write64(intr, base + OTX2_REE_LF_MISC_INT);
-}
-
-static void
-ree_lf_err_intr_unregister(const struct rte_regexdev *dev, uint16_t msix_off,
-			   uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	otx2_unregister_irq(handle, ree_lf_err_intr_handler, (void *)base,
-			    msix_off);
-}
-
-void
-otx2_ree_err_intr_unregister(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uintptr_t base;
-	uint32_t i;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
-	}
-
-	vf->err_intr_registered = 0;
-}
-
-static int
-ree_lf_err_intr_register(const struct rte_regexdev *dev, uint16_t msix_off,
-			 uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-	int ret;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	/* Register error interrupt handler */
-	ret = otx2_register_irq(handle, ree_lf_err_intr_handler, (void *)base,
-				msix_off);
-	if (ret)
-		return ret;
-
-	/* Enable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1S);
-
-	return 0;
-}
-
-int
-otx2_ree_err_intr_register(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uint32_t i, j, ret;
-	uintptr_t base;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
-			otx2_err("Invalid REE LF MSI-X offset: 0x%x",
-				    vf->lf_msixoff[i]);
-			return -EINVAL;
-		}
-	}
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ret = ree_lf_err_intr_register(dev, vf->lf_msixoff[i], base);
-		if (ret)
-			goto intr_unregister;
-	}
-
-	vf->err_intr_registered = 1;
-	return 0;
-
-intr_unregister:
-	/* Unregister the ones already registered */
-	for (j = 0; j < i; j++) {
-		base = OTX2_REE_LF_BAR2(vf, j);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
-	}
-	return ret;
-}
-
-int
-otx2_ree_iq_enable(const struct rte_regexdev *dev, const struct otx2_ree_qp *qp,
-		   uint8_t pri, uint32_t size_div2)
-{
-	union otx2_ree_lf_sbuf_addr base;
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Set instruction queue size and priority */
-	otx2_ree_config_lf(dev, qp->id, pri, size_div2);
-
-	/* Set instruction queue base address */
-	/* Should be written after SBUF_CTL and before LF_ENA */
-
-	base.u = otx2_read64(qp->base + OTX2_REE_LF_SBUF_ADDR);
-	base.s.ptr = qp->iq_dma_addr >> 7;
-	otx2_write64(base.u, qp->base + OTX2_REE_LF_SBUF_ADDR);
-
-	/* Enable instruction queue */
-
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 1;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-
-	return 0;
-}
-
-void
-otx2_ree_iq_disable(struct otx2_ree_qp *qp)
-{
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Stop instruction execution */
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 0x0;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-}
-
-int
-otx2_ree_max_matches_get(const struct rte_regexdev *dev, uint8_t *max_matches)
-{
-	union otx2_ree_af_reexm_max_match reexm_max_match;
-	int ret;
-
-	ret = otx2_ree_af_reg_read(dev, REE_AF_REEXM_MAX_MATCH,
-				   &reexm_max_match.u);
-	if (ret)
-		return ret;
-
-	*max_matches = reexm_max_match.s.max;
-	return 0;
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h b/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
deleted file mode 100644
index dedf5f3282..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_HW_ACCESS_H_
-#define _OTX2_REGEXDEV_HW_ACCESS_H_
-
-#include <stdint.h>
-
-#include "otx2_regexdev.h"
-
-/* REE instruction queue length */
-#define OTX2_REE_IQ_LEN			(1 << 13)
-
-#define OTX2_REE_DEFAULT_CMD_QLEN	OTX2_REE_IQ_LEN
-
-/* Status register bits */
-#define OTX2_REE_STATUS_PMI_EOJ_BIT		(1 << 14)
-#define OTX2_REE_STATUS_PMI_SOJ_BIT		(1 << 13)
-#define OTX2_REE_STATUS_MP_CNT_DET_BIT		(1 << 7)
-#define OTX2_REE_STATUS_MM_CNT_DET_BIT		(1 << 6)
-#define OTX2_REE_STATUS_ML_CNT_DET_BIT		(1 << 5)
-#define OTX2_REE_STATUS_MST_CNT_DET_BIT		(1 << 4)
-#define OTX2_REE_STATUS_MPT_CNT_DET_BIT		(1 << 3)
-
-/* Register offsets */
-/* REE LF registers */
-#define OTX2_REE_LF_DONE_INT		0x120ull
-#define OTX2_REE_LF_DONE_INT_W1S	0x130ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1S	0x138ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1C	0x140ull
-#define OTX2_REE_LF_MISC_INT		0x300ull
-#define OTX2_REE_LF_MISC_INT_W1S	0x310ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1S	0x320ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1C	0x330ull
-#define OTX2_REE_LF_ENA			0x10ull
-#define OTX2_REE_LF_SBUF_ADDR		0x20ull
-#define OTX2_REE_LF_DONE		0x100ull
-#define OTX2_REE_LF_DONE_ACK		0x110ull
-#define OTX2_REE_LF_DONE_WAIT		0x148ull
-#define OTX2_REE_LF_DOORBELL		0x400ull
-#define OTX2_REE_LF_OUTSTAND_JOB	0x410ull
-
-/* BAR 0 */
-#define OTX2_REE_AF_QUE_SBUF_CTL(a)	(0x1200ull | (uint64_t)(a) << 3)
-#define OTX2_REE_PRIV_LF_CFG(a)		(0x41000ull | (uint64_t)(a) << 3)
-
-#define OTX2_REE_LF_BAR2(vf, q_id) \
-		((vf)->otx2_dev.bar2 + \
-		 (((vf)->block_address << 20) | ((q_id) << 12)))
-
-
-#define OTX2_REE_QUEUE_HI_PRIO 0x1
-
-enum ree_desc_type_e {
-	REE_TYPE_JOB_DESC    = 0x0,
-	REE_TYPE_RESULT_DESC = 0x1,
-	REE_TYPE_ENUM_LAST   = 0x2
-};
-
-union otx2_ree_priv_lf_cfg {
-	uint64_t u;
-	struct {
-		uint64_t slot                        : 8;
-		uint64_t pf_func                     : 16;
-		uint64_t reserved_24_62              : 39;
-		uint64_t ena                         : 1;
-	} s;
-};
-
-
-union otx2_ree_lf_sbuf_addr {
-	uint64_t u;
-	struct {
-		uint64_t off                         : 7;
-		uint64_t ptr                         : 46;
-		uint64_t reserved_53_63              : 11;
-	} s;
-};
-
-union otx2_ree_lf_ena {
-	uint64_t u;
-	struct {
-		uint64_t ena                         : 1;
-		uint64_t reserved_1_63               : 63;
-	} s;
-};
-
-union otx2_ree_af_reexm_max_match {
-	uint64_t u;
-	struct {
-		uint64_t max                         : 8;
-		uint64_t reserved_8_63               : 56;
-	} s;
-};
-
-union otx2_ree_lf_done {
-	uint64_t u;
-	struct {
-		uint64_t done                        : 20;
-		uint64_t reserved_20_63              : 44;
-	} s;
-};
-
-union otx2_ree_inst {
-	uint64_t u[8];
-	struct  {
-		uint64_t doneint                     :  1;
-		uint64_t reserved_1_3                :  3;
-		uint64_t dg                          :  1;
-		uint64_t reserved_5_7                :  3;
-		uint64_t ooj                         :  1;
-		uint64_t reserved_9_15               :  7;
-		uint64_t reserved_16_63              : 48;
-		uint64_t inp_ptr_addr                : 64;
-		uint64_t inp_ptr_ctl                 : 64;
-		uint64_t res_ptr_addr                : 64;
-		uint64_t wq_ptr                      : 64;
-		uint64_t tag                         : 32;
-		uint64_t tt                          :  2;
-		uint64_t ggrp                        : 10;
-		uint64_t reserved_364_383            : 20;
-		uint64_t reserved_384_391            :  8;
-		uint64_t ree_job_id                  : 24;
-		uint64_t ree_job_ctrl                : 16;
-		uint64_t ree_job_length              : 15;
-		uint64_t reserved_447_447            :  1;
-		uint64_t ree_job_subset_id_0         : 16;
-		uint64_t ree_job_subset_id_1         : 16;
-		uint64_t ree_job_subset_id_2         : 16;
-		uint64_t ree_job_subset_id_3         : 16;
-	} cn98xx;
-};
-
-union otx2_ree_res_status {
-	uint64_t u;
-	struct {
-		uint64_t job_type                    :  3;
-		uint64_t mpt_cnt_det                 :  1;
-		uint64_t mst_cnt_det                 :  1;
-		uint64_t ml_cnt_det                  :  1;
-		uint64_t mm_cnt_det                  :  1;
-		uint64_t mp_cnt_det                  :  1;
-		uint64_t mode                        :  2;
-		uint64_t reserved_10_11              :  2;
-		uint64_t reserved_12_12              :  1;
-		uint64_t pmi_soj                     :  1;
-		uint64_t pmi_eoj                     :  1;
-		uint64_t reserved_15_15              :  1;
-		uint64_t reserved_16_63              : 48;
-	} s;
-};
-
-union otx2_ree_res {
-	uint64_t u[8];
-	struct ree_res_s_98 {
-		uint64_t done			:  1;
-		uint64_t hwjid			:  7;
-		uint64_t ree_res_job_id		: 24;
-		uint64_t ree_res_status		: 16;
-		uint64_t ree_res_dmcnt		:  8;
-		uint64_t ree_res_mcnt		:  8;
-		uint64_t ree_meta_ptcnt		: 16;
-		uint64_t ree_meta_icnt		: 16;
-		uint64_t ree_meta_lcnt		: 16;
-		uint64_t ree_pmi_min_byte_ptr	: 16;
-		uint64_t ree_err		:  1;
-		uint64_t reserved_129_190	: 62;
-		uint64_t doneint		:  1;
-		uint64_t reserved_192_255	: 64;
-		uint64_t reserved_256_319	: 64;
-		uint64_t reserved_320_383	: 64;
-		uint64_t reserved_384_447	: 64;
-		uint64_t reserved_448_511	: 64;
-	} s;
-};
-
-union otx2_ree_match {
-	uint64_t u;
-	struct {
-		uint64_t ree_rule_id                 : 32;
-		uint64_t start_ptr                   : 14;
-		uint64_t reserved_46_47              :  2;
-		uint64_t match_length                : 15;
-		uint64_t reserved_63_63              :  1;
-	} s;
-};
-
-void otx2_ree_err_intr_unregister(const struct rte_regexdev *dev);
-
-int otx2_ree_err_intr_register(const struct rte_regexdev *dev);
-
-int otx2_ree_iq_enable(const struct rte_regexdev *dev,
-		       const struct otx2_ree_qp *qp,
-		       uint8_t pri, uint32_t size_div128);
-
-void otx2_ree_iq_disable(struct otx2_ree_qp *qp);
-
-int otx2_ree_max_matches_get(const struct rte_regexdev *dev,
-			     uint8_t *max_matches);
-
-#endif /* _OTX2_REGEXDEV_HW_ACCESS_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.c b/drivers/regex/octeontx2/otx2_regexdev_mbox.c
deleted file mode 100644
index 6d58d367d4..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_mbox.h"
-#include "otx2_regexdev.h"
-
-int
-otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-			      uint16_t *nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct free_rsrcs_rsp *rsp;
-	struct otx2_dev *otx2_dev;
-	int ret;
-
-	otx2_dev = &vf->otx2_dev;
-	otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);
-
-	ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
-	if (ret)
-		return -EIO;
-
-	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-		*nb_queues = rsp->ree0;
-	else
-		*nb_queues = rsp->ree1;
-	return 0;
-}
-
-int
-otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_attach_req *req;
-	struct otx2_mbox *mbox;
-
-	/* Ask AF to attach required LFs */
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_attach_resources(mbox);
-
-	/* 1 LF = 1 queue */
-	req->reelfs = nb_queues;
-	req->ree_blkaddr = vf->block_address;
-
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Update number of attached queues */
-	vf->nb_queues = nb_queues;
-
-	return 0;
-}
-
-int
-otx2_ree_queues_detach(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_detach_req *req;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_detach_resources(mbox);
-	req->reelfs = true;
-	req->partial = true;
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Queues have been detached */
-	vf->nb_queues = 0;
-
-	return 0;
-}
-
-int
-otx2_ree_msix_offsets_get(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct msix_offset_rsp *rsp;
-	struct otx2_mbox *mbox;
-	uint32_t i, ret;
-
-	/* Get REE MSI-X vector offsets */
-	mbox = vf->otx2_dev.mbox;
-	otx2_mbox_alloc_msg_msix_offset(mbox);
-
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
-		else
-			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
-		otx2_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
-	}
-
-	return 0;
-}
-
-static int
-ree_send_mbox_msg(struct otx2_ree_vf *vf)
-{
-	struct otx2_mbox *mbox = vf->otx2_dev.mbox;
-	int ret;
-
-	otx2_mbox_msg_send(mbox, 0);
-
-	ret = otx2_mbox_wait_for_rsp(mbox, 0);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-
-	return 0;
-}
-
-int
-otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		   uint32_t size)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_lf_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_ree_config_lf(mbox);
-
-	req->lf = lf;
-	req->pri =  pri ? 1 : 0;
-	req->size = size;
-	req->blkaddr = vf->block_address;
-
-	ret = otx2_mbox_process(mbox);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-	return 0;
-}
-
-int
-otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-		     uint64_t *val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox_dev *mdev;
-	struct otx2_mbox *mbox;
-	int ret, off;
-
-	mbox = vf->otx2_dev.mbox;
-	mdev = &mbox->dev[0];
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 0;
-	msg->reg_offset = reg;
-	msg->ret_val = val;
-	msg->blkaddr = vf->block_address;
-
-	ret = ree_send_mbox_msg(vf);
-	if (ret < 0)
-		return ret;
-
-	off = mbox->rx_start +
-			RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
-	msg = (struct ree_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);
-
-	*val = msg->val;
-
-	return 0;
-}
-
-int
-otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-		      uint64_t val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 1;
-	msg->reg_offset = reg;
-	msg->val = val;
-	msg->blkaddr = vf->block_address;
-
-	return ree_send_mbox_msg(vf);
-}
-
-int
-otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_get_req_msg *req;
-	struct ree_rule_db_get_rsp_msg *rsp;
-	char *rule_db_ptr = (char *)rule_db;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct otx2_mbox *mbox;
-	int ret, last = 0;
-	uint32_t len = 0;
-
-	mbox = vf->otx2_dev.mbox;
-	if (!rule_db) {
-		otx2_err("Couldn't return rule db due to NULL pointer");
-		return -EFAULT;
-	}
-
-	while (!last) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 0;
-		req->offset = len;
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_db_len < len + rsp->len) {
-			otx2_err("Rule db size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
-		len += rsp->len;
-		rule_db_ptr = rule_db_ptr + rsp->len;
-		last = rsp->is_last;
-	}
-
-	if (rule_dbi) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 1;
-		req->offset = 0;
-
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_dbi_len < rsp->len) {
-			otx2_err("Rule dbi size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-		uint32_t *rule_db_len,
-		uint32_t *rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_len_rsp_msg *rsp;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = (struct ree_req_msg *)
-		otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), sizeof(*rsp));
-	if (!req) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
-	req->hdr.sig = OTX2_MBOX_REQ_SIG;
-	req->hdr.pcifunc = vf->otx2_dev.pf_func;
-	req->blkaddr = vf->block_address;
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-	if (rule_db_len != NULL)
-		*rule_db_len = rsp->len;
-	if (rule_dbi_len != NULL)
-		*rule_dbi_len = rsp->inc_len;
-
-	return 0;
-}
-
-static int
-ree_db_msg(const struct rte_regexdev *dev, const char *db, uint32_t db_len,
-		int inc, int dbi)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	uint32_t len_left = db_len, offset = 0;
-	struct ree_rule_db_prog_req_msg *req;
-	struct otx2_ree_vf *vf = &data->vf;
-	const char *rule_db_ptr = db;
-	struct otx2_mbox *mbox;
-	struct msg_rsp *rsp;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	while (len_left) {
-		req = (struct ree_rule_db_prog_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->offset = offset;
-		req->total_len = db_len;
-		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
-		req->is_incremental = inc;
-		req->is_dbi = dbi;
-		req->blkaddr = vf->block_address;
-
-		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
-			req->is_last = true;
-			req->len = len_left;
-		}
-		otx2_mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret) {
-			otx2_err("Programming mailbox processing failed");
-			return ret;
-		}
-		len_left -= req->len;
-		offset += req->len;
-		rule_db_ptr = rule_db_ptr + req->len;
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len)
-{
-	int inc, ret;
-
-	if (rule_db_len == 0) {
-		otx2_err("Couldn't program empty rule db");
-		return -EFAULT;
-	}
-	inc = (rule_dbi_len != 0);
-	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
-		otx2_err("Couldn't program NULL rule db");
-		return -EFAULT;
-	}
-	if (inc) {
-		ret = ree_db_msg(dev, rule_dbi, rule_dbi_len, inc, 1);
-		if (ret)
-			return ret;
-	}
-	return ree_db_msg(dev, rule_db, rule_db_len, inc, 0);
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.h b/drivers/regex/octeontx2/otx2_regexdev_mbox.h
deleted file mode 100644
index 953efa6724..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_MBOX_H_
-#define _OTX2_REGEXDEV_MBOX_H_
-
-#include <rte_regexdev.h>
-
-int otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-				  uint16_t *nb_queues);
-
-int otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues);
-
-int otx2_ree_queues_detach(const struct rte_regexdev *dev);
-
-int otx2_ree_msix_offsets_get(const struct rte_regexdev *dev);
-
-int otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		       uint32_t size);
-
-int otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-			 uint64_t *val);
-
-int otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-			  uint64_t val);
-
-int otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		 uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len);
-
-int otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-			     uint32_t *rule_db_len, uint32_t *rule_dbi_len);
-
-int otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len);
-
-#endif /* _OTX2_REGEXDEV_MBOX_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 0/5] regex/cn9k: use cnxk infrastructure
  2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
                     ` (6 preceding siblings ...)
  2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
@ 2021-11-29 19:59   ` lironh
  2021-11-29 19:59     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
                       ` (4 more replies)
  7 siblings, 5 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:59 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v3:
- fix documentation issues

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 doc/guides/platform/octeontx2.rst             |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 doc/guides/rel_notes/release_20_11.rst        |   2 +-
 drivers/common/cnxk/hw/ree.h                  | 126 ++++
 drivers/common/cnxk/hw/rvu.h                  |   5 +
 drivers/common/cnxk/meson.build               |   1 +
 drivers/common/cnxk/roc_api.h                 |   4 +
 drivers/common/cnxk/roc_constants.h           |   2 +
 drivers/common/cnxk/roc_mbox.h                | 100 +++
 drivers/common/cnxk/roc_platform.c            |   1 +
 drivers/common/cnxk/roc_platform.h            |   2 +
 drivers/common/cnxk/roc_priv.h                |   3 +
 drivers/common/cnxk/roc_ree.c                 | 647 ++++++++++++++++++
 drivers/common/cnxk/roc_ree.h                 | 137 ++++
 drivers/common/cnxk/roc_ree_priv.h            |  18 +
 drivers/common/cnxk/version.map               |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +++++------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -----
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 33 files changed, 1332 insertions(+), 1206 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 1/5] common/cnxk: add REE HW definitions
  2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
@ 2021-11-29 19:59     ` lironh
  2021-11-29 19:59     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
                       ` (3 subsequent siblings)
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:59 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

adding REE (Regular Expression Engine) HW definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/hw/ree.h | 126 +++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/hw/rvu.h |   5 ++
 2 files changed, 131 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/ree.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 0000000000..30af61d704
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BIT	   BIT_ULL(14)
+#define REE_STATUS_PMI_SOJ_BIT	   BIT_ULL(13)
+#define REE_STATUS_MP_CNT_DET_BIT  BIT_ULL(7)
+#define REE_STATUS_MM_CNT_DET_BIT  BIT_ULL(6)
+#define REE_STATUS_ML_CNT_DET_BIT  BIT_ULL(5)
+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT		0x120ull
+#define REE_LF_DONE_INT_W1S	0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT		0x300ull
+#define REE_LF_MISC_INT_W1S	0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA		0x10ull
+#define REE_LF_SBUF_ADDR	0x20ull
+#define REE_LF_DONE		0x100ull
+#define REE_LF_DONE_ACK		0x110ull
+#define REE_LF_DONE_WAIT	0x148ull
+#define REE_LF_DOORBELL		0x400ull
+#define REE_LF_OUTSTAND_JOB	0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a)     (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS	(0x0ull)
+#define REE_AF_INT_VEC_RVU	(0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ	(0x3ull)
+
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC	(0x1ull)
+
+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
+
+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)
+
+#define REE_LF_BAR2(vf, q_id)                                                  \
+	((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+	REE_TYPE_JOB_DESC = 0x0,
+	REE_TYPE_RESULT_DESC = 0x1,
+	REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_res_status {
+	uint64_t u;
+	struct {
+		uint64_t job_type : 3;
+		uint64_t mpt_cnt_det : 1;
+		uint64_t mst_cnt_det : 1;
+		uint64_t ml_cnt_det : 1;
+		uint64_t mm_cnt_det : 1;
+		uint64_t mp_cnt_det : 1;
+		uint64_t mode : 2;
+		uint64_t reserved_10_11 : 2;
+		uint64_t reserved_12_12 : 1;
+		uint64_t pmi_soj : 1;
+		uint64_t pmi_eoj : 1;
+		uint64_t reserved_15_15 : 1;
+		uint64_t reserved_16_63 : 48;
+	} s;
+};
+
+union ree_res {
+	uint64_t u[8];
+	struct ree_res_s_98 {
+		uint64_t done : 1;
+		uint64_t hwjid : 7;
+		uint64_t ree_res_job_id : 24;
+		uint64_t ree_res_status : 16;
+		uint64_t ree_res_dmcnt : 8;
+		uint64_t ree_res_mcnt : 8;
+		uint64_t ree_meta_ptcnt : 16;
+		uint64_t ree_meta_icnt : 16;
+		uint64_t ree_meta_lcnt : 16;
+		uint64_t ree_pmi_min_byte_ptr : 16;
+		uint64_t ree_err : 1;
+		uint64_t reserved_129_190 : 62;
+		uint64_t doneint : 1;
+		uint64_t reserved_192_255 : 64;
+		uint64_t reserved_256_319 : 64;
+		uint64_t reserved_320_383 : 64;
+		uint64_t reserved_384_447 : 64;
+		uint64_t reserved_448_511 : 64;
+	} s;
+};
+
+union ree_match {
+	uint64_t u;
+	struct {
+		uint64_t ree_rule_id : 32;
+		uint64_t start_ptr : 14;
+		uint64_t reserved_46_47 : 2;
+		uint64_t match_length : 15;
+		uint64_t reserved_63_6 : 1;
+	} s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM    (0x0ull)
 #define RVU_BLOCK_ADDR_LMT     (0x1ull)
@@ -147,6 +148,8 @@
 #define RVU_BLOCK_ADDR_NDC2    (0xeull)
 #define RVU_BLOCK_ADDR_R_END   (0x1full)
 #define RVU_BLOCK_ADDR_R_START (0x14ull)
+#define RVU_BLOCK_ADDR_REE0    (0x14ull)
+#define RVU_BLOCK_ADDR_REE1    (0x15ull)
 
 #define RVU_VF_INT_VEC_MBOX (0x0ull)
 
@@ -167,6 +170,7 @@
 #define NPA_AF_BAR2_SEL	 (0x9000000ull)
 #define CPT_AF_BAR2_SEL	 (0x9000000ull)
 #define RVU_AF_BAR2_SEL	 (0x9000000ull)
+#define REE_AF_BAR2_SEL	 (0x9000000ull)
 
 #define AF_BAR2_ALIASX(a, b)                                                   \
 	(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))
@@ -177,6 +181,7 @@
 #define NPA_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(0, b)
 #define CPT_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 #define RVU_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
+#define REE_AF_BAR2_ALIASX(a, b)  AF_BAR2_ALIASX(a, b)
 
 /* Structures definitions */
 
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 2/5] common/cnxk: add REE mbox definitions
  2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
  2021-11-29 19:59     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
@ 2021-11-29 19:59     ` lironh
  2021-11-29 19:59     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
                       ` (2 subsequent siblings)
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:59 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add REE mbox definitions

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 100 +++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..e97d93e261 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -151,6 +151,16 @@ struct mbox_msghdr {
 	M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)        \
 	M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,            \
 	  cpt_eng_grp_rsp)                                                     \
+	/* REE mbox IDs (range 0xE00 - 0xFFF) */                               \
+	M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)        \
+	M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,    \
+	  ree_rd_wr_reg_msg)                                                   \
+	M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+	  msg_rsp)                                                             \
+	M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,        \
+	  ree_rule_db_len_rsp_msg)                                             \
+	M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,    \
+	  ree_rule_db_get_rsp_msg)                                             \
 	/* SDP mbox IDs (range 0x1000 - 0x11FF) */                             \
 	M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg,     \
 	  msg_rsp)                                                             \
@@ -1452,6 +1462,96 @@ struct cpt_eng_grp_rsp {
 	uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+	REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+	REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+	REE_AF_ERR_LF_INVALID = -1003,
+	REE_AF_ERR_ACCESS_DENIED = -1004,
+	REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+	REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+	REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+	REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+	REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+	REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+	REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+	REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+	REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+	REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+	REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+	REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+	REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+	REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+	REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+	REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+	REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+	REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+	REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io size;
+	uint8_t __io lf;
+	uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+	uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+	uint32_t __io blkaddr;	     /* REE0 or REE1 */
+	uint32_t __io total_len;     /* total len of rule db */
+	uint32_t __io offset;	     /* offset of current rule db block */
+	uint16_t __io len;	     /* length of rule db block */
+	uint8_t __io is_last;	     /* is this the last block */
+	uint8_t __io is_incremental; /* is incremental flow */
+	uint8_t __io is_dbi;	     /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io offset; /* retrieve db from this offset */
+	uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+	struct mbox_msghdr hdr;
+	uint64_t __io reg_offset;
+	uint64_t __io *ret_val;
+	uint64_t __io val;
+	uint32_t __io blkaddr;
+	uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __io blkaddr;
+	uint32_t __io len;
+	uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+	uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+	uint32_t __io total_len; /* total len of rule db */
+	uint32_t __io offset;	 /* offset of current rule db block */
+	uint16_t __io len;	 /* length of rule db block */
+	uint8_t __io is_last;	 /* is this the last block */
+};
+
 /* NPC mbox message structs */
 
 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 3/5] common/cnxk: add REE support
  2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
  2021-11-29 19:59     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
  2021-11-29 19:59     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
@ 2021-11-29 19:59     ` lironh
  2021-11-29 19:59     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
  2021-11-29 19:59     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:59 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

extend cnxk infrastructure to support REE

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/roc_ree.c      | 647 +++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ree.h      | 137 ++++++
 drivers/common/cnxk/roc_ree_priv.h |  18 +
 3 files changed, 802 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 0000000000..1eb2ae7272
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+	struct free_rsrcs_rsp *rsp;
+	struct dev *dev = vf->dev;
+	int ret;
+
+	mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+		*nb_queues = rsp->ree0;
+	else
+		*nb_queues = rsp->ree1;
+	return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+	uint64_t val;
+	int ret;
+
+	ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+	if (ret)
+		return ret;
+
+	*max_matches = val;
+	return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+	struct rsrc_attach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	/* Ask AF to attach required LFs */
+	req = mbox_alloc_msg_attach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	/* 1 LF = 1 queue */
+	req->reelfs = nb_queues;
+	req->ree_blkaddr = vf->block_address;
+
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Update number of attached queues */
+	vf->nb_queues = nb_queues;
+
+	return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+	struct rsrc_detach_req *req;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_detach_resources(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+	req->reelfs = true;
+	req->partial = true;
+	if (mbox_process(mbox) < 0)
+		return -EIO;
+
+	/* Queues have been detached */
+	vf->nb_queues = 0;
+
+	return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+	struct msix_offset_rsp *rsp;
+	struct mbox *mbox;
+	uint32_t i, ret;
+
+	/* Get REE MSI-X vector offsets */
+	mbox = vf->dev->mbox;
+	mbox_alloc_msg_msix_offset(mbox);
+
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+		else
+			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+		plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+	}
+
+	return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+	struct mbox *mbox = vf->dev->mbox;
+	int ret;
+
+	mbox_msg_send(mbox, 0);
+
+	ret = mbox_wait_for_rsp(mbox, 0);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+
+	return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t size)
+{
+	struct ree_lf_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = mbox_alloc_msg_ree_config_lf(mbox);
+	if (req == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->lf = lf;
+	req->pri = pri ? 1 : 0;
+	req->size = size;
+	req->blkaddr = vf->block_address;
+
+	ret = mbox_process(mbox);
+	if (ret < 0) {
+		plt_err("Could not get mailbox response");
+		return ret;
+	}
+	return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox_dev *mdev;
+	struct mbox *mbox;
+	int ret, off;
+
+	mbox = vf->dev->mbox;
+	mdev = &mbox->dev[0];
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 0;
+	msg->reg_offset = reg;
+	msg->ret_val = val;
+	msg->blkaddr = vf->block_address;
+
+	ret = ree_send_mbox_msg(vf);
+	if (ret < 0)
+		return ret;
+
+	off = mbox->rx_start +
+	      RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+	msg = (struct ree_rd_wr_reg_msg *)((uintptr_t)mdev->mbase + off);
+
+	*val = msg->val;
+
+	return 0;
+}
+
+int
+roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg, uint64_t val)
+{
+	struct ree_rd_wr_reg_msg *msg;
+	struct mbox *mbox;
+
+	mbox = vf->dev->mbox;
+	msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+		mbox, 0, sizeof(*msg), sizeof(*msg));
+	if (msg == NULL) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
+	msg->hdr.sig = MBOX_REQ_SIG;
+	msg->hdr.pcifunc = vf->dev->pf_func;
+	msg->is_write = 1;
+	msg->reg_offset = reg;
+	msg->val = val;
+	msg->blkaddr = vf->block_address;
+
+	return ree_send_mbox_msg(vf);
+}
+
+int
+roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db, uint32_t rule_db_len,
+		    char *rule_dbi, uint32_t rule_dbi_len)
+{
+	struct ree_rule_db_get_req_msg *req;
+	struct ree_rule_db_get_rsp_msg *rsp;
+	char *rule_db_ptr = (char *)rule_db;
+	struct mbox *mbox;
+	int ret, last = 0;
+	uint32_t len = 0;
+
+	mbox = vf->dev->mbox;
+	if (!rule_db) {
+		plt_err("Couldn't return rule db due to NULL pointer");
+		return -EFAULT;
+	}
+
+	while (!last) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 0;
+		req->offset = len;
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_db_len < len + rsp->len) {
+			plt_err("Rule db size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
+		len += rsp->len;
+		rule_db_ptr = rule_db_ptr + rsp->len;
+		last = rsp->is_last;
+	}
+
+	if (rule_dbi) {
+		req = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->blkaddr = vf->block_address;
+		req->is_dbi = 1;
+		req->offset = 0;
+
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret)
+			return ret;
+		if (rule_dbi_len < rsp->len) {
+			plt_err("Rule dbi size is too small");
+			return -EFAULT;
+		}
+		mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_len_get(struct roc_ree_vf *vf, uint32_t *rule_db_len,
+			uint32_t *rule_dbi_len)
+{
+	struct ree_rule_db_len_rsp_msg *rsp;
+	struct ree_req_msg *req;
+	struct mbox *mbox;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	req = (struct ree_req_msg *)mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
+						       sizeof(*rsp));
+	if (!req) {
+		plt_err("Could not allocate mailbox message");
+		return -EFAULT;
+	}
+
+	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
+	req->hdr.sig = MBOX_REQ_SIG;
+	req->hdr.pcifunc = vf->dev->pf_func;
+	req->blkaddr = vf->block_address;
+	ret = mbox_process_msg(mbox, (void *)&rsp);
+	if (ret)
+		return ret;
+	if (rule_db_len != NULL)
+		*rule_db_len = rsp->len;
+	if (rule_dbi_len != NULL)
+		*rule_dbi_len = rsp->inc_len;
+
+	return 0;
+}
+
+static int
+ree_db_msg(struct roc_ree_vf *vf, const char *db, uint32_t db_len, int inc,
+	   int dbi)
+{
+	uint32_t len_left = db_len, offset = 0;
+	struct ree_rule_db_prog_req_msg *req;
+	const char *rule_db_ptr = db;
+	struct mbox *mbox;
+	struct msg_rsp *rsp;
+	int ret;
+
+	mbox = vf->dev->mbox;
+	while (len_left) {
+		req = (struct ree_rule_db_prog_req_msg *)mbox_alloc_msg_rsp(
+			mbox, 0, sizeof(*req), sizeof(*rsp));
+		if (!req) {
+			plt_err("Could not allocate mailbox message");
+			return -EFAULT;
+		}
+		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
+		req->hdr.sig = MBOX_REQ_SIG;
+		req->hdr.pcifunc = vf->dev->pf_func;
+		req->offset = offset;
+		req->total_len = db_len;
+		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
+		req->is_incremental = inc;
+		req->is_dbi = dbi;
+		req->blkaddr = vf->block_address;
+
+		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
+			req->is_last = true;
+			req->len = len_left;
+		}
+		mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
+		ret = mbox_process_msg(mbox, (void *)&rsp);
+		if (ret) {
+			plt_err("Programming mailbox processing failed");
+			return ret;
+		}
+		len_left -= req->len;
+		offset += req->len;
+		rule_db_ptr = rule_db_ptr + req->len;
+	}
+	return 0;
+}
+
+int
+roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+		     uint32_t rule_db_len, const char *rule_dbi,
+		     uint32_t rule_dbi_len)
+{
+	int inc, ret;
+
+	if (rule_db_len == 0) {
+		plt_err("Couldn't program empty rule db");
+		return -EFAULT;
+	}
+	inc = (rule_dbi_len != 0);
+	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
+		plt_err("Couldn't program NULL rule db");
+		return -EFAULT;
+	}
+	if (inc) {
+		ret = ree_db_msg(vf, rule_dbi, rule_dbi_len, inc, 1);
+		if (ret)
+			return ret;
+	}
+	return ree_db_msg(vf, rule_db, rule_db_len, inc, 0);
+}
+
+static int
+ree_get_blkaddr(struct dev *dev)
+{
+	int pf;
+
+	pf = dev_get_pf(dev->pf_func);
+	if (pf == REE0_PF)
+		return RVU_BLOCK_ADDR_REE0;
+	else if (pf == REE1_PF)
+		return RVU_BLOCK_ADDR_REE1;
+	else
+		return 0;
+}
+
+uintptr_t
+roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id)
+{
+	return REE_LF_BAR2(vf, qp_id);
+}
+
+static void
+roc_ree_lf_err_intr_handler(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint8_t lf_id;
+	uint64_t intr;
+
+	lf_id = (base >> 12) & 0xFF;
+
+	intr = plt_read64(base + REE_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
+
+	/* Clear interrupt */
+	plt_write64(intr, base + REE_LF_MISC_INT);
+}
+
+static void
+roc_ree_lf_err_intr_unregister(struct roc_ree_vf *vf, uint16_t msix_off,
+			       uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	dev_irq_unregister(pci_dev->intr_handle,
+			   roc_ree_lf_err_intr_handler, (void *)base, msix_off);
+}
+
+void
+roc_ree_err_intr_unregister(struct roc_ree_vf *vf)
+{
+	uintptr_t base;
+	uint32_t i;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base);
+	}
+
+	vf->err_intr_registered = 0;
+}
+
+static int
+roc_ree_lf_err_intr_register(struct roc_ree_vf *vf, uint16_t msix_off,
+			     uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = vf->pci_dev;
+	int ret;
+
+	/* Disable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);
+
+	/* Register error interrupt handler */
+	ret = dev_irq_register(pci_dev->intr_handle,
+			       roc_ree_lf_err_intr_handler, (void *)base,
+			       msix_off);
+	if (ret)
+		return ret;
+
+	/* Enable error interrupts */
+	plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1S);
+
+	return 0;
+}
+
+int
+roc_ree_err_intr_register(struct roc_ree_vf *vf)
+{
+	uint32_t i, j, ret;
+	uintptr_t base;
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
+			plt_err("Invalid REE LF MSI-X offset: 0x%x",
+				vf->lf_msixoff[i]);
+			return -EINVAL;
+		}
+	}
+
+	for (i = 0; i < vf->nb_queues; i++) {
+		base = REE_LF_BAR2(vf, i);
+		ret = roc_ree_lf_err_intr_register(vf, vf->lf_msixoff[i], base);
+		if (ret)
+			goto intr_unregister;
+	}
+
+	vf->err_intr_registered = 1;
+	return 0;
+
+intr_unregister:
+	/* Unregister the ones already registered */
+	for (j = 0; j < i; j++) {
+		base = REE_LF_BAR2(vf, j);
+		roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[j], base);
+	}
+	return ret;
+}
+
+int
+roc_ree_iq_enable(struct roc_ree_vf *vf, const struct roc_ree_qp *qp,
+		  uint8_t pri, uint32_t size_div2)
+{
+	uint64_t val;
+
+	/* Set instruction queue size and priority */
+	roc_ree_config_lf(vf, qp->id, pri, size_div2);
+
+	/* Set instruction queue base address */
+	/* Should be written after SBUF_CTL and before LF_ENA */
+
+	val = plt_read64(qp->base + REE_LF_SBUF_ADDR);
+	val &= ~REE_LF_SBUF_ADDR_PTR_MASK;
+	val |= FIELD_PREP(REE_LF_SBUF_ADDR_PTR_MASK, qp->iq_dma_addr >> 7);
+	plt_write64(val, qp->base + REE_LF_SBUF_ADDR);
+
+	/* Enable instruction queue */
+
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 1);
+	plt_write64(val, qp->base + REE_LF_ENA);
+
+	return 0;
+}
+
+void
+roc_ree_iq_disable(struct roc_ree_qp *qp)
+{
+	uint64_t val;
+
+	/* Stop instruction execution */
+	val = plt_read64(qp->base + REE_LF_ENA);
+	val &= ~REE_LF_ENA_ENA_MASK;
+	val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 0);
+	plt_write64(val, qp->base + REE_LF_ENA);
+}
+
+int
+roc_ree_dev_init(struct roc_ree_vf *vf)
+{
+	struct plt_pci_device *pci_dev;
+	struct ree *ree;
+	struct dev *dev;
+	uint8_t max_matches = 0;
+	uint16_t nb_queues = 0;
+	int rc;
+
+	if (vf == NULL || vf->pci_dev == NULL)
+		return -EINVAL;
+
+	PLT_STATIC_ASSERT(sizeof(struct ree) <= ROC_REE_MEM_SZ);
+
+	ree = roc_ree_to_ree_priv(vf);
+	memset(ree, 0, sizeof(*ree));
+	vf->dev = &ree->dev;
+
+	pci_dev = vf->pci_dev;
+	dev = vf->dev;
+
+	/* Initialize device  */
+	rc = dev_init(dev, pci_dev);
+	if (rc) {
+		plt_err("Failed to init roc device");
+		goto fail;
+	}
+
+	/* Get REE block address */
+	vf->block_address = ree_get_blkaddr(dev);
+	if (!vf->block_address) {
+		plt_err("Could not determine block PF number");
+		goto fail;
+	}
+
+	/* Get number of queues available on the device */
+	rc = roc_ree_available_queues_get(vf, &nb_queues);
+	if (rc) {
+		plt_err("Could not determine the number of queues available");
+		goto fail;
+	}
+
+	/* Don't exceed the limits set per VF */
+	nb_queues = RTE_MIN(nb_queues, REE_MAX_QUEUES_PER_VF);
+
+	if (nb_queues == 0) {
+		plt_err("No free queues available on the device");
+		goto fail;
+	}
+
+	vf->max_queues = nb_queues;
+
+	plt_ree_dbg("Max queues supported by device: %d", vf->max_queues);
+
+	/* Get number of maximum matches supported on the device */
+	rc = roc_ree_max_matches_get(vf, &max_matches);
+	if (rc) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+	/* Don't exceed the limits set per VF */
+	max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
+	if (max_matches == 0) {
+		plt_err("Could not determine the maximum matches supported");
+		goto fail;
+	}
+
+	vf->max_matches = max_matches;
+
+	plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+fail:
+	return rc;
+}
+
+int
+roc_ree_dev_fini(struct roc_ree_vf *vf)
+{
+	if (vf == NULL)
+		return -EINVAL;
+
+	vf->max_matches = 0;
+	vf->max_queues = 0;
+
+	return dev_fini(vf->dev, vf->pci_dev);
+}
diff --git a/drivers/common/cnxk/roc_ree.h b/drivers/common/cnxk/roc_ree.h
new file mode 100644
index 0000000000..e138e4de66
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_H_
+#define _ROC_REE_H_
+
+#include "roc_api.h"
+
+#define REE_MAX_LFS	       36
+#define REE_MAX_QUEUES_PER_VF  36
+#define REE_MAX_MATCHES_PER_VF 254
+
+#define REE_MAX_PAYLOAD_SIZE (1 << 14)
+
+#define REE_NON_INC_PROG 0
+#define REE_INC_PROG	 1
+
+#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)
+
+/**
+ * Device vf data
+ */
+struct roc_ree_vf {
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	/**< Base class */
+	uint16_t max_queues;
+	/**< Max queues supported */
+	uint8_t nb_queues;
+	/**< Number of regex queues attached */
+	uint16_t max_matches;
+	/**<  Max matches supported*/
+	uint16_t lf_msixoff[REE_MAX_LFS];
+	/**< MSI-X offsets */
+	uint8_t block_address;
+	/**< REE Block Address */
+	uint8_t err_intr_registered : 1;
+	/**< Are error interrupts registered? */
+
+#define ROC_REE_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_REE_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+struct roc_ree_rid {
+	uintptr_t rid;
+	/** Request id of a ree operation */
+	uint64_t user_id;
+	/* Client data */
+	/**< IOVA address of the pattern to be matched. */
+};
+
+struct roc_ree_pending_queue {
+	uint64_t pending_count;
+	/** Pending requests count */
+	struct roc_ree_rid *rid_queue;
+	/** Array of pending requests */
+	uint16_t enq_tail;
+	/** Tail of queue to be used for enqueue */
+	uint16_t deq_head;
+	/** Head of queue to be used for dequeue */
+};
+
+struct roc_ree_qp {
+	uint32_t id;
+	/**< Queue pair id */
+	uintptr_t base;
+	/**< Base address where BAR is mapped */
+	struct roc_ree_pending_queue pend_q;
+	/**< Pending queue */
+	rte_iova_t iq_dma_addr;
+	/**< Instruction queue address */
+	uint32_t roc_regexdev_jobid;
+	/**< Job ID */
+	uint32_t write_offset;
+	/**< write offset */
+};
+
+union roc_ree_inst {
+	uint64_t u[8];
+	struct {
+		uint64_t doneint : 1;
+		uint64_t reserved_1_3 : 3;
+		uint64_t dg : 1;
+		uint64_t reserved_5_7 : 3;
+		uint64_t ooj : 1;
+		uint64_t reserved_9_15 : 7;
+		uint64_t reserved_16_63 : 48;
+		uint64_t inp_ptr_addr : 64;
+		uint64_t inp_ptr_ctl : 64;
+		uint64_t res_ptr_addr : 64;
+		uint64_t wq_ptr : 64;
+		uint64_t tag : 32;
+		uint64_t tt : 2;
+		uint64_t ggrp : 10;
+		uint64_t reserved_364_383 : 20;
+		uint64_t reserved_384_391 : 8;
+		uint64_t ree_job_id : 24;
+		uint64_t ree_job_ctrl : 16;
+		uint64_t ree_job_length : 15;
+		uint64_t reserved_447_447 : 1;
+		uint64_t ree_job_subset_id_0 : 16;
+		uint64_t ree_job_subset_id_1 : 16;
+		uint64_t ree_job_subset_id_2 : 16;
+		uint64_t ree_job_subset_id_3 : 16;
+	} cn98xx;
+};
+
+int __roc_api roc_ree_dev_init(struct roc_ree_vf *vf);
+int __roc_api roc_ree_dev_fini(struct roc_ree_vf *vf);
+int __roc_api roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues);
+int __roc_api roc_ree_queues_detach(struct roc_ree_vf *vf);
+int __roc_api roc_ree_msix_offsets_get(struct roc_ree_vf *vf);
+int __roc_api roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri,
+				uint32_t size);
+int __roc_api roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg,
+				  uint64_t *val);
+int __roc_api roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg,
+				   uint64_t val);
+int __roc_api roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db,
+				  uint32_t rule_db_len, char *rule_dbi,
+				  uint32_t rule_dbi_len);
+int __roc_api roc_ree_rule_db_len_get(struct roc_ree_vf *vf,
+				      uint32_t *rule_db_len,
+				      uint32_t *rule_dbi_len);
+int __roc_api roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,
+				   uint32_t rule_db_len, const char *rule_dbi,
+				   uint32_t rule_dbi_len);
+uintptr_t __roc_api roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id);
+void __roc_api roc_ree_err_intr_unregister(struct roc_ree_vf *vf);
+int __roc_api roc_ree_err_intr_register(struct roc_ree_vf *vf);
+int __roc_api roc_ree_iq_enable(struct roc_ree_vf *vf,
+				const struct roc_ree_qp *qp, uint8_t pri,
+				uint32_t size_div128);
+void __roc_api roc_ree_iq_disable(struct roc_ree_qp *qp);
+
+#endif /* _ROC_REE_H_ */
diff --git a/drivers/common/cnxk/roc_ree_priv.h b/drivers/common/cnxk/roc_ree_priv.h
new file mode 100644
index 0000000000..c39f7cf986
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree_priv.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_REE_PRIV_H_
+#define _ROC_REE_PRIV_H_
+
+struct ree {
+	struct dev dev;
+} __plt_cache_aligned;
+
+static inline struct ree *
+roc_ree_to_ree_priv(struct roc_ree_vf *roc_ree)
+{
+	return (struct ree *)&roc_ree->reserved[0];
+}
+
+#endif /* _ROC_REE_PRIV_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 4/5] common/cnxk: link REE support to ROC files
  2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
                       ` (2 preceding siblings ...)
  2021-11-29 19:59     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
@ 2021-11-29 19:59     ` lironh
  2021-11-29 19:59     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:59 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

add references to REE files from ROC files

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 drivers/common/cnxk/meson.build     |  1 +
 drivers/common/cnxk/roc_api.h       |  4 ++++
 drivers/common/cnxk/roc_constants.h |  2 ++
 drivers/common/cnxk/roc_platform.c  |  1 +
 drivers/common/cnxk/roc_platform.h  |  2 ++
 drivers/common/cnxk/roc_priv.h      |  3 +++
 drivers/common/cnxk/version.map     | 18 +++++++++++++++++-
 7 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4928f7e549..7e27b3cc0a 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -61,6 +61,7 @@ sources = files(
         'roc_tim.c',
         'roc_tim_irq.c',
         'roc_utils.c',
+        'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index e7aaa07563..1b46c21f7f 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -37,6 +37,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -90,6 +91,9 @@
 /* DPI */
 #include "roc_dpi.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
index ac7335061c..5f78823642 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY	      0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF     0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF     0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 61d4781209..85aa6dcebc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)                                                  \
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)	plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)	plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)	plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)	plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)                                               \
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 782b90cf8d..122d411fe7 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,4 +44,7 @@
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..5a03b91784 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_nix;
 	cnxk_logtype_npa;
 	cnxk_logtype_npc;
+	cnxk_logtype_ree;
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
@@ -347,6 +348,21 @@ INTERNAL {
 	roc_tim_lf_enable;
 	roc_tim_lf_free;
 	roc_se_ctx_swap;
-
+	roc_ree_af_reg_read;
+	roc_ree_af_reg_write;
+	roc_ree_config_lf;
+	roc_ree_dev_fini;
+	roc_ree_dev_init;
+	roc_ree_err_intr_register;
+	roc_ree_err_intr_unregister;
+	roc_ree_iq_disable;
+	roc_ree_iq_enable;
+	roc_ree_msix_offsets_get;
+	roc_ree_qp_get_base;
+	roc_ree_queues_attach;
+	roc_ree_queues_detach;
+	roc_ree_rule_db_get;
+	roc_ree_rule_db_len_get;
+	roc_ree_rule_db_prog;
 	local: *;
 };
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure
  2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
                       ` (3 preceding siblings ...)
  2021-11-29 19:59     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
@ 2021-11-29 19:59     ` lironh
  4 siblings, 0 replies; 31+ messages in thread
From: lironh @ 2021-11-29 19:59 UTC (permalink / raw)
  To: jerinj; +Cc: dev, Liron Himi

From: Liron Himi <lironh@marvell.com>

update driver to use the REE cnxk code
replace octeontx2/otx2 with cn9k

Signed-off-by: Liron Himi <lironh@marvell.com>
---
 MAINTAINERS                                   |   8 +-
 doc/guides/platform/cnxk.rst                  |   3 +
 doc/guides/platform/octeontx2.rst             |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst}     |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}      |   2 +-
 doc/guides/regexdevs/index.rst                |   2 +-
 doc/guides/rel_notes/release_20_11.rst        |   2 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 ++++++++----------
 drivers/regex/cn9k/cn9k_regexdev.h            |  44 ++
 .../cn9k_regexdev_compiler.c}                 |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build                     |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h       | 109 -----
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 --------
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ---------
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -----------------
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 --
 20 files changed, 269 insertions(+), 1205 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..5f45b35c51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst
 RegEx Drivers
 -------------
 
-Marvell OCTEON TX2 regex
+Marvell OCTEON CN9K regex
 M: Liron Himi <lironh@marvell.com>
-F: drivers/regex/octeontx2/
-F: doc/guides/regexdevs/octeontx2.rst
-F: doc/guides/regexdevs/features/octeontx2.ini
+F: drivers/regex/cn9k/
+F: doc/guides/regexdevs/cn9k.rst
+F: doc/guides/regexdevs/features/cn9k.ini
 
 Mellanox mlx5
 M: Ori Kam <orika@nvidia.com>
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 88995cc70c..5213df3ccd 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
 #. **Dmadev Driver**
    See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
 
+#. **Regex Device Driver**
+   See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 3a3d28571c..5ab43abbdd 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -155,9 +155,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
 #. **Crypto Device Driver**
    See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
-#. **Regex Device Driver**
-   See :doc:`../regexdevs/octeontx2` for REE regex device driver information.
-
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst
similarity index 69%
rename from doc/guides/regexdevs/octeontx2.rst
rename to doc/guides/regexdevs/cn9k.rst
index b39d457d60..c23c295b93 100644
--- a/doc/guides/regexdevs/octeontx2.rst
+++ b/doc/guides/regexdevs/cn9k.rst
@@ -1,20 +1,20 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
     Copyright(c) 2020 Marvell International Ltd.
 
-OCTEON TX2 REE Regexdev Driver
+CN9K REE Regexdev Driver
 ==============================
 
-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode
-regexdev driver support for the inbuilt regex device found in the **Marvell OCTEON TX2**
+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode
+regexdev driver support for the inbuilt regex device found in the **Marvell CN9K**
 SoC family.
 
-More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+More information about CN9K SoC can be found at `Marvell Official Website
 <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
 
 Features
 --------
 
-Features of the OCTEON TX2 REE PMD are:
+Features of the CN9K REE PMD are:
 
 - 36 queues
 - Up to 254 matches for each regex operation
@@ -22,12 +22,12 @@ Features of the OCTEON TX2 REE PMD are:
 Prerequisites and Compilation procedure
 ---------------------------------------
 
-   See :doc:`../platform/octeontx2` for setup information.
+   See :doc:`../platform/cnxk` for setup information.
 
 Device Setup
 ------------
 
-The OCTEON TX2 REE devices will need to be bound to a user-space IO driver
+The CN9K REE devices will need to be bound to a user-space IO driver
 for use. The script ``dpdk-devbind.py`` script included with DPDK can be
 used to view the state of the devices and to bind them to a suitable
 DPDK-supported kernel driver. When querying the status of the devices,
@@ -38,12 +38,12 @@ those devices alone.
 Debugging Options
 -----------------
 
-.. _table_octeontx2_regex_debug_options:
+.. _table_cn9k_regex_debug_options:
 
-.. table:: OCTEON TX2 regex device debug options
+.. table:: CN9K regex device debug options
 
    +---+------------+-------------------------------------------------------+
    | # | Component  | EAL log command                                       |
    +===+============+=======================================================+
-   | 1 | REE        | --log-level='pmd\.regex\.octeontx2,8'                 |
+   | 1 | REE        | --log-level='pmd\.regex\.cn9k,8'                      |
    +---+------------+-------------------------------------------------------+
diff --git a/doc/guides/regexdevs/features/octeontx2.ini b/doc/guides/regexdevs/features/cn9k.ini
similarity index 80%
rename from doc/guides/regexdevs/features/octeontx2.ini
rename to doc/guides/regexdevs/features/cn9k.ini
index c9b421a16d..b029af8ac2 100644
--- a/doc/guides/regexdevs/features/octeontx2.ini
+++ b/doc/guides/regexdevs/features/cn9k.ini
@@ -1,5 +1,5 @@
 ;
-; Supported features of the 'octeontx2' regex driver.
+; Supported features of the 'cn9k' regex driver.
 ;
 ; Refer to default.ini for the full list of available driver features.
 ;
diff --git a/doc/guides/regexdevs/index.rst b/doc/guides/regexdevs/index.rst
index b1abc826bd..11a33fc09e 100644
--- a/doc/guides/regexdevs/index.rst
+++ b/doc/guides/regexdevs/index.rst
@@ -13,4 +13,4 @@ which can be used from an application through RegEx API.
 
    features_overview
    mlx5
-   octeontx2
+   cn9k
diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index 90cc3ed680..d6d40c31df 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -290,7 +290,7 @@ New Features
 
   Added a new PMD driver for the hardware regex offload block for OCTEON TX2 SoC.
 
-  See the :doc:`../regexdevs/octeontx2` for more details.
+  See ``regexdevs/octeontx2`` for more details.
 
 * **Updated Software Eventdev driver.**
 
diff --git a/drivers/regex/octeontx2/otx2_regexdev.c b/drivers/regex/cn9k/cn9k_regexdev.c
similarity index 61%
rename from drivers/regex/octeontx2/otx2_regexdev.c
rename to drivers/regex/cn9k/cn9k_regexdev.c
index b6e55853e9..32d20c1be8 100644
--- a/drivers/regex/octeontx2/otx2_regexdev.c
+++ b/drivers/regex/cn9k/cn9k_regexdev.c
@@ -13,12 +13,8 @@
 
 
 /* REE common headers */
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 
 /* HW matches are at offset 0x80 from RES_PTR_ADDR
@@ -35,9 +31,6 @@
 #define REE_MAX_RULES_PER_GROUP 0xFFFF
 #define REE_MAX_GROUPS 0xFFFF
 
-/* This is temporarily here */
-#define REE0_PF	19
-#define REE1_PF	20
 
 #define REE_RULE_DB_VERSION	2
 #define REE_RULE_DB_REVISION	0
@@ -58,32 +51,32 @@ struct ree_rule_db {
 static void
 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
 {
-	snprintf(name, size, "otx2_ree_lf_mem_%u:%u", dev_id, qp_id);
+	snprintf(name, size, "cn9k_ree_lf_mem_%u:%u", dev_id, qp_id);
 }
 
-static struct otx2_ree_qp *
+static struct roc_ree_qp *
 ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
-	struct otx2_ree_vf *vf = &data->vf;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct rte_memzone *lf_mem;
 	uint32_t len, iq_len, size_div2;
 	char name[RTE_MEMZONE_NAMESIZE];
 	uint64_t used_len, iova;
-	struct otx2_ree_qp *qp;
+	struct roc_ree_qp *qp;
 	uint8_t *va;
 	int ret;
 
 	/* Allocate queue pair */
-	qp = rte_zmalloc("OCTEON TX2 Regex PMD Queue Pair", sizeof(*qp),
-				OTX2_ALIGN);
+	qp = rte_zmalloc("CN9K Regex PMD Queue Pair", sizeof(*qp),
+				ROC_ALIGN);
 	if (qp == NULL) {
-		otx2_err("Could not allocate queue pair");
+		cn9k_err("Could not allocate queue pair");
 		return NULL;
 	}
 
-	iq_len = OTX2_REE_IQ_LEN;
+	iq_len = REE_IQ_LEN;
 
 	/*
 	 * Queue size must be in units of 128B 2 * REE_INST_S (which is 64B),
@@ -93,13 +86,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	size_div2 = iq_len >> 1;
 
 	/* For pending queue */
-	len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 
 	/* So that instruction queues start as pg size aligned */
 	len = RTE_ALIGN(len, pg_sz);
 
 	/* For instruction queues */
-	len += OTX2_REE_IQ_LEN * sizeof(union otx2_ree_inst);
+	len += REE_IQ_LEN * sizeof(union roc_ree_inst);
 
 	/* Waste after instruction queues */
 	len = RTE_ALIGN(len, pg_sz);
@@ -107,11 +100,11 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp_id);
 
-	lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
+	lf_mem = rte_memzone_reserve_aligned(name, len, rte_socket_id(),
 			RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
 			RTE_CACHE_LINE_SIZE);
 	if (lf_mem == NULL) {
-		otx2_err("Could not allocate reserved memzone");
+		cn9k_err("Could not allocate reserved memzone");
 		goto qp_free;
 	}
 
@@ -121,24 +114,24 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 	memset(va, 0, len);
 
 	/* Initialize pending queue */
-	qp->pend_q.rid_queue = (struct otx2_ree_rid *)va;
+	qp->pend_q.rid_queue = (struct roc_ree_rid *)va;
 	qp->pend_q.enq_tail = 0;
 	qp->pend_q.deq_head = 0;
 	qp->pend_q.pending_count = 0;
 
-	used_len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);
+	used_len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);
 	used_len = RTE_ALIGN(used_len, pg_sz);
 	iova += used_len;
 
 	qp->iq_dma_addr = iova;
 	qp->id = qp_id;
-	qp->base = OTX2_REE_LF_BAR2(vf, qp_id);
-	qp->otx2_regexdev_jobid = 0;
+	qp->base = roc_ree_qp_get_base(vf, qp_id);
+	qp->roc_regexdev_jobid = 0;
 	qp->write_offset = 0;
 
-	ret = otx2_ree_iq_enable(dev, qp, OTX2_REE_QUEUE_HI_PRIO, size_div2);
+	ret = roc_ree_iq_enable(vf, qp, REE_QUEUE_HI_PRIO, size_div2);
 	if (ret) {
-		otx2_err("Could not enable instruction queue");
+		cn9k_err("Could not enable instruction queue");
 		goto qp_free;
 	}
 
@@ -150,13 +143,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)
 }
 
 static int
-ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
+ree_qp_destroy(const struct rte_regexdev *dev, struct roc_ree_qp *qp)
 {
 	const struct rte_memzone *lf_mem;
 	char name[RTE_MEMZONE_NAMESIZE];
 	int ret;
 
-	otx2_ree_iq_disable(qp);
+	roc_ree_iq_disable(qp);
 
 	qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 			    qp->id);
@@ -175,8 +168,8 @@ ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)
 static int
 ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
 	int ret;
 
 	ree_func_trace("Queue=%d", qp_id);
@@ -186,7 +179,7 @@ ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)
 
 	ret = ree_qp_destroy(dev, qp);
 	if (ret) {
-		otx2_err("Could not destroy queue pair %d", qp_id);
+		cn9k_err("Could not destroy queue pair %d", qp_id);
 		return ret;
 	}
 
@@ -200,12 +193,12 @@ ree_dev_register(const char *name)
 {
 	struct rte_regexdev *dev;
 
-	otx2_ree_dbg("Creating regexdev %s\n", name);
+	cn9k_ree_dbg("Creating regexdev %s\n", name);
 
 	/* allocate device structure */
 	dev = rte_regexdev_register(name);
 	if (dev == NULL) {
-		otx2_err("Failed to allocate regex device for %s", name);
+		cn9k_err("Failed to allocate regex device for %s", name);
 		return NULL;
 	}
 
@@ -213,12 +206,12 @@ ree_dev_register(const char *name)
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		dev->data->dev_private =
 				rte_zmalloc_socket("regexdev device private",
-						sizeof(struct otx2_ree_data),
+						sizeof(struct cn9k_ree_data),
 						RTE_CACHE_LINE_SIZE,
 						rte_socket_id());
 
 		if (dev->data->dev_private == NULL) {
-			otx2_err("Cannot allocate memory for dev %s private data",
+			cn9k_err("Cannot allocate memory for dev %s private data",
 					name);
 
 			rte_regexdev_unregister(dev);
@@ -232,7 +225,7 @@ ree_dev_register(const char *name)
 static int
 ree_dev_unregister(struct rte_regexdev *dev)
 {
-	otx2_ree_dbg("Closing regex device %s", dev->device->name);
+	cn9k_ree_dbg("Closing regex device %s", dev->device->name);
 
 	/* free regex device */
 	rte_regexdev_unregister(dev);
@@ -246,8 +239,8 @@ ree_dev_unregister(struct rte_regexdev *dev)
 static int
 ree_dev_fini(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct rte_pci_device *pci_dev;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	int i, ret;
 
 	ree_func_trace();
@@ -258,9 +251,9 @@ ree_dev_fini(struct rte_regexdev *dev)
 			return ret;
 	}
 
-	ret = otx2_ree_queues_detach(dev);
+	ret = roc_ree_queues_detach(vf);
 	if (ret)
-		otx2_err("Could not detach queues");
+		cn9k_err("Could not detach queues");
 
 	/* TEMP : should be in lib */
 	if (data->queue_pairs)
@@ -268,33 +261,32 @@ ree_dev_fini(struct rte_regexdev *dev)
 	if (data->rules)
 		rte_free(data->rules);
 
-	pci_dev = container_of(dev->device, struct rte_pci_device, device);
-	otx2_dev_fini(pci_dev, &(data->vf.otx2_dev));
+	roc_ree_dev_fini(vf);
 
 	ret = ree_dev_unregister(dev);
 	if (ret)
-		otx2_err("Could not destroy PMD");
+		cn9k_err("Could not destroy PMD");
 
 	return ret;
 }
 
 static inline int
-ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
-		 struct otx2_ree_pending_queue *pend_q)
+ree_enqueue(struct roc_ree_qp *qp, struct rte_regex_ops *op,
+		 struct roc_ree_pending_queue *pend_q)
 {
-	union otx2_ree_inst inst;
-	union otx2_ree_res *res;
+	union roc_ree_inst inst;
+	union ree_res *res;
 	uint32_t offset;
 
-	if (unlikely(pend_q->pending_count >= OTX2_REE_DEFAULT_CMD_QLEN)) {
-		otx2_err("Pending count %" PRIu64 " is greater than Q size %d",
-		pend_q->pending_count, OTX2_REE_DEFAULT_CMD_QLEN);
+	if (unlikely(pend_q->pending_count >= REE_DEFAULT_CMD_QLEN)) {
+		cn9k_err("Pending count %" PRIu64 " is greater than Q size %d",
+		pend_q->pending_count, REE_DEFAULT_CMD_QLEN);
 		return -EAGAIN;
 	}
-	if (unlikely(op->mbuf->data_len > OTX2_REE_MAX_PAYLOAD_SIZE ||
+	if (unlikely(op->mbuf->data_len > REE_MAX_PAYLOAD_SIZE ||
 			op->mbuf->data_len == 0)) {
-		otx2_err("Packet length %d is greater than MAX payload %d",
-				op->mbuf->data_len, OTX2_REE_MAX_PAYLOAD_SIZE);
+		cn9k_err("Packet length %d is greater than MAX payload %d",
+				op->mbuf->data_len, REE_MAX_PAYLOAD_SIZE);
 		return -EAGAIN;
 	}
 
@@ -324,7 +316,7 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 		inst.cn98xx.ree_job_ctrl = (0x1 << 8);
 	else
 		inst.cn98xx.ree_job_ctrl = 0;
-	inst.cn98xx.ree_job_id = qp->otx2_regexdev_jobid;
+	inst.cn98xx.ree_job_id = qp->roc_regexdev_jobid;
 	/* W 7 */
 	inst.cn98xx.ree_job_subset_id_0 = op->group_id0;
 	if (op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F)
@@ -348,33 +340,33 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,
 	pend_q->rid_queue[pend_q->enq_tail].user_id = op->user_id;
 
 	/* Mark result as not done */
-	res = (union otx2_ree_res *)(op);
+	res = (union ree_res *)(op);
 	res->s.done = 0;
 	res->s.ree_err = 0;
 
 	/* We will use soft queue length here to limit requests */
-	REE_MOD_INC(pend_q->enq_tail, OTX2_REE_DEFAULT_CMD_QLEN);
+	REE_MOD_INC(pend_q->enq_tail, REE_DEFAULT_CMD_QLEN);
 	pend_q->pending_count += 1;
-	REE_MOD_INC(qp->otx2_regexdev_jobid, 0xFFFFFF);
-	REE_MOD_INC(qp->write_offset, OTX2_REE_IQ_LEN);
+	REE_MOD_INC(qp->roc_regexdev_jobid, 0xFFFFFF);
+	REE_MOD_INC(qp->write_offset, REE_IQ_LEN);
 
 	return 0;
 }
 
 static uint16_t
-otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	uint16_t nb_allowed, count = 0;
 	struct rte_regex_ops *op;
 	int ret;
 
 	pend_q = &qp->pend_q;
 
-	nb_allowed = OTX2_REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
+	nb_allowed = REE_DEFAULT_CMD_QLEN - pend_q->pending_count;
 	if (nb_ops > nb_allowed)
 		nb_ops = nb_allowed;
 
@@ -392,7 +384,7 @@ otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 	rte_io_wmb();
 
 	/* Update Doorbell */
-	otx2_write64(count, qp->base + OTX2_REE_LF_DOORBELL);
+	plt_write64(count, qp->base + REE_LF_DOORBELL);
 
 	return count;
 }
@@ -422,15 +414,15 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 	}
 
 	if (unlikely(ree_res_status != REE_TYPE_RESULT_DESC)) {
-		if (ree_res_status & OTX2_REE_STATUS_PMI_SOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_SOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_PMI_EOJ_BIT)
+		if (ree_res_status & REE_STATUS_PMI_EOJ_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F;
-		if (ree_res_status & OTX2_REE_STATUS_ML_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_ML_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F;
-		if (ree_res_status & OTX2_REE_STATUS_MM_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MM_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F;
-		if (ree_res_status & OTX2_REE_STATUS_MP_CNT_DET_BIT)
+		if (ree_res_status & REE_STATUS_MP_CNT_DET_BIT)
 			ops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F;
 	}
 	if (ops->nb_matches > 0) {
@@ -439,22 +431,22 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)
 			ops->nb_matches : REE_NUM_MATCHES_ALIGN);
 		match = (uint64_t)ops + REE_MATCH_OFFSET;
 		match += (ops->nb_matches - off) *
-			sizeof(union otx2_ree_match);
+			sizeof(union ree_match);
 		memcpy((void *)ops->matches, (void *)match,
-			off * sizeof(union otx2_ree_match));
+			off * sizeof(union ree_match));
 	}
 }
 
 static uint16_t
-otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp = data->queue_pairs[qp_id];
-	struct otx2_ree_pending_queue *pend_q;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp = data->queue_pairs[qp_id];
+	struct roc_ree_pending_queue *pend_q;
 	int i, nb_pending, nb_completed = 0;
 	volatile struct ree_res_s_98 *res;
-	struct otx2_ree_rid *rid;
+	struct roc_ree_rid *rid;
 
 	pend_q = &qp->pend_q;
 
@@ -474,7 +466,7 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 		ops[i] = (struct rte_regex_ops *)(rid->rid);
 		ops[i]->user_id = rid->user_id;
 
-		REE_MOD_INC(pend_q->deq_head, OTX2_REE_DEFAULT_CMD_QLEN);
+		REE_MOD_INC(pend_q->deq_head, REE_DEFAULT_CMD_QLEN);
 		pend_q->pending_count -= 1;
 	}
 
@@ -487,10 +479,10 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,
 }
 
 static int
-otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
+cn9k_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 
 	ree_func_trace();
 
@@ -502,7 +494,7 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 
 	info->max_queue_pairs = vf->max_queues;
 	info->max_matches = vf->max_matches;
-	info->max_payload_size = OTX2_REE_MAX_PAYLOAD_SIZE;
+	info->max_payload_size = REE_MAX_PAYLOAD_SIZE;
 	info->max_rules_per_group = data->max_rules_per_group;
 	info->max_groups = data->max_groups;
 	info->regexdev_capa = data->regexdev_capa;
@@ -512,11 +504,11 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)
 }
 
 static int
-otx2_ree_dev_config(struct rte_regexdev *dev,
+cn9k_ree_dev_config(struct rte_regexdev *dev,
 		    const struct rte_regexdev_config *cfg)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *rule_db;
 	uint32_t rule_db_len;
 	int ret;
@@ -524,29 +516,29 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	ree_func_trace();
 
 	if (cfg->nb_queue_pairs > vf->max_queues) {
-		otx2_err("Invalid number of queue pairs requested");
+		cn9k_err("Invalid number of queue pairs requested");
 		return -EINVAL;
 	}
 
 	if (cfg->nb_max_matches != vf->max_matches) {
-		otx2_err("Invalid number of max matches requested");
+		cn9k_err("Invalid number of max matches requested");
 		return -EINVAL;
 	}
 
 	if (cfg->dev_cfg_flags != 0) {
-		otx2_err("Invalid device configuration flags requested");
+		cn9k_err("Invalid device configuration flags requested");
 		return -EINVAL;
 	}
 
 	/* Unregister error interrupts */
 	if (vf->err_intr_registered)
-		otx2_ree_err_intr_unregister(dev);
+		roc_ree_err_intr_unregister(vf);
 
 	/* Detach queues */
 	if (vf->nb_queues) {
-		ret = otx2_ree_queues_detach(dev);
+		ret = roc_ree_queues_detach(vf);
 		if (ret) {
-			otx2_err("Could not detach REE queues");
+			cn9k_err("Could not detach REE queues");
 			return ret;
 		}
 	}
@@ -559,7 +551,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 
 		if (data->queue_pairs == NULL) {
 			data->nb_queue_pairs = 0;
-			otx2_err("Failed to get memory for qp meta data, nb_queues %u",
+			cn9k_err("Failed to get memory for qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -579,7 +571,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 		qp = rte_realloc(qp, sizeof(qp[0]) * cfg->nb_queue_pairs,
 				RTE_CACHE_LINE_SIZE);
 		if (qp == NULL) {
-			otx2_err("Failed to realloc qp meta data, nb_queues %u",
+			cn9k_err("Failed to realloc qp meta data, nb_queues %u",
 					cfg->nb_queue_pairs);
 			return -ENOMEM;
 		}
@@ -594,52 +586,52 @@ otx2_ree_dev_config(struct rte_regexdev *dev,
 	data->nb_queue_pairs = cfg->nb_queue_pairs;
 
 	/* Attach queues */
-	otx2_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
-	ret = otx2_ree_queues_attach(dev, cfg->nb_queue_pairs);
+	cn9k_ree_dbg("Attach %d queues", cfg->nb_queue_pairs);
+	ret = roc_ree_queues_attach(vf, cfg->nb_queue_pairs);
 	if (ret) {
-		otx2_err("Could not attach queues");
+		cn9k_err("Could not attach queues");
 		return -ENODEV;
 	}
 
-	ret = otx2_ree_msix_offsets_get(dev);
+	ret = roc_ree_msix_offsets_get(vf);
 	if (ret) {
-		otx2_err("Could not get MSI-X offsets");
+		cn9k_err("Could not get MSI-X offsets");
 		goto queues_detach;
 	}
 
 	if (cfg->rule_db && cfg->rule_db_len) {
-		otx2_ree_dbg("rule_db length %d", cfg->rule_db_len);
+		cn9k_ree_dbg("rule_db length %d", cfg->rule_db_len);
 		rule_db = (const struct ree_rule_db *)cfg->rule_db;
 		rule_db_len = rule_db->number_of_entries *
 				sizeof(struct ree_rule_db_entry);
-		otx2_ree_dbg("rule_db number of entries %d",
+		cn9k_ree_dbg("rule_db number of entries %d",
 				rule_db->number_of_entries);
 		if (rule_db_len > cfg->rule_db_len) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			ret = -EINVAL;
 			goto queues_detach;
 		}
-		ret = otx2_ree_rule_db_prog(dev, (const char *)rule_db->entries,
-				rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+		ret = roc_ree_rule_db_prog(vf, (const char *)rule_db->entries,
+				rule_db_len, NULL, REE_NON_INC_PROG);
 		if (ret) {
-			otx2_err("Could not program rule db");
+			cn9k_err("Could not program rule db");
 			goto queues_detach;
 		}
 	}
 
-	dev->enqueue = otx2_ree_enqueue_burst;
-	dev->dequeue = otx2_ree_dequeue_burst;
+	dev->enqueue = cn9k_ree_enqueue_burst;
+	dev->dequeue = cn9k_ree_dequeue_burst;
 
 	rte_mb();
 	return 0;
 
 queues_detach:
-	otx2_ree_queues_detach(dev);
+	roc_ree_queues_detach(vf);
 	return ret;
 }
 
 static int
-otx2_ree_stop(struct rte_regexdev *dev)
+cn9k_ree_stop(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 
@@ -648,18 +640,20 @@ otx2_ree_stop(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_start(struct rte_regexdev *dev)
+cn9k_ree_start(struct rte_regexdev *dev)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	uint32_t rule_db_len = 0;
 	int ret;
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, NULL);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, NULL);
 	if (ret)
 		return ret;
 	if (rule_db_len == 0) {
-		otx2_err("Rule db not programmed");
+		cn9k_err("Rule db not programmed");
 		return -EFAULT;
 	}
 
@@ -667,56 +661,55 @@ otx2_ree_start(struct rte_regexdev *dev)
 }
 
 static int
-otx2_ree_close(struct rte_regexdev *dev)
+cn9k_ree_close(struct rte_regexdev *dev)
 {
 	return ree_dev_fini(dev);
 }
 
 static int
-otx2_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
+cn9k_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,
 		const struct rte_regexdev_qp_conf *qp_conf)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_qp *qp;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_qp *qp;
 
 	ree_func_trace("Queue=%d", qp_id);
 
 	if (data->queue_pairs[qp_id] != NULL)
 		ree_queue_pair_release(dev, qp_id);
 
-	if (qp_conf->nb_desc > OTX2_REE_DEFAULT_CMD_QLEN) {
-		otx2_err("Could not setup queue pair for %u descriptors",
+	if (qp_conf->nb_desc > REE_DEFAULT_CMD_QLEN) {
+		cn9k_err("Could not setup queue pair for %u descriptors",
 				qp_conf->nb_desc);
 		return -EINVAL;
 	}
 	if (qp_conf->qp_conf_flags != 0) {
-		otx2_err("Could not setup queue pair with configuration flags 0x%x",
+		cn9k_err("Could not setup queue pair with configuration flags 0x%x",
 				qp_conf->qp_conf_flags);
 		return -EINVAL;
 	}
 
 	qp = ree_qp_create(dev, qp_id);
 	if (qp == NULL) {
-		otx2_err("Could not create queue pair %d", qp_id);
+		cn9k_err("Could not create queue pair %d", qp_id);
 		return -ENOMEM;
 	}
-	qp->cb = qp_conf->cb;
 	data->queue_pairs[qp_id] = qp;
 
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_compile_activate(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_activate(struct rte_regexdev *dev)
 {
-	return otx2_ree_rule_db_compile_prog(dev);
+	return cn9k_ree_rule_db_compile_prog(dev);
 }
 
 static int
-otx2_ree_rule_db_update(struct rte_regexdev *dev,
+cn9k_ree_rule_db_update(struct rte_regexdev *dev,
 		const struct rte_regexdev_rule *rules, uint16_t nb_rules)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
 	struct rte_regexdev_rule *old_ptr;
 	uint32_t i, sum_nb_rules;
 
@@ -770,10 +763,11 @@ otx2_ree_rule_db_update(struct rte_regexdev *dev,
 }
 
 static int
-otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
+cn9k_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 		uint32_t rule_db_len)
 {
-
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	const struct ree_rule_db *ree_rule_db;
 	uint32_t ree_rule_db_len;
 	int ret;
@@ -784,21 +778,23 @@ otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,
 	ree_rule_db_len = ree_rule_db->number_of_entries *
 			sizeof(struct ree_rule_db_entry);
 	if (ree_rule_db_len > rule_db_len) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -EINVAL;
 	}
-	ret = otx2_ree_rule_db_prog(dev, (const char *)ree_rule_db->entries,
-			ree_rule_db_len, NULL, OTX2_REE_NON_INC_PROG);
+	ret = roc_ree_rule_db_prog(vf, (const char *)ree_rule_db->entries,
+			ree_rule_db_len, NULL, REE_NON_INC_PROG);
 	if (ret) {
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 		return -ENOSPC;
 	}
 	return 0;
 }
 
 static int
-otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
+cn9k_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 {
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	struct ree_rule_db *ree_rule_db;
 	uint32_t rule_dbi_len;
 	uint32_t rule_db_len;
@@ -806,7 +802,7 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret)
 		return ret;
 
@@ -816,10 +812,10 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	}
 
 	ree_rule_db = (struct ree_rule_db *)rule_db;
-	ret = otx2_ree_rule_db_get(dev, (char *)ree_rule_db->entries,
+	ret = roc_ree_rule_db_get(vf, (char *)ree_rule_db->entries,
 			rule_db_len, NULL, 0);
 	if (ret) {
-		otx2_err("Could not export rule db");
+		cn9k_err("Could not export rule db");
 		return -EFAULT;
 	}
 	ree_rule_db->number_of_entries =
@@ -830,55 +826,44 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)
 	return 0;
 }
 
-static int
-ree_get_blkaddr(struct otx2_dev *dev)
-{
-	int pf;
-
-	pf = otx2_get_pf(dev->pf_func);
-	if (pf == REE0_PF)
-		return RVU_BLOCK_ADDR_REE0;
-	else if (pf == REE1_PF)
-		return RVU_BLOCK_ADDR_REE1;
-	else
-		return 0;
-}
-
-static struct rte_regexdev_ops otx2_ree_ops = {
-		.dev_info_get = otx2_ree_dev_info_get,
-		.dev_configure = otx2_ree_dev_config,
-		.dev_qp_setup = otx2_ree_queue_pair_setup,
-		.dev_start = otx2_ree_start,
-		.dev_stop = otx2_ree_stop,
-		.dev_close = otx2_ree_close,
-		.dev_attr_get = NULL,
-		.dev_attr_set = NULL,
-		.dev_rule_db_update = otx2_ree_rule_db_update,
-		.dev_rule_db_compile_activate =
-				otx2_ree_rule_db_compile_activate,
-		.dev_db_import = otx2_ree_rule_db_import,
-		.dev_db_export = otx2_ree_rule_db_export,
-		.dev_xstats_names_get = NULL,
-		.dev_xstats_get = NULL,
-		.dev_xstats_by_name_get = NULL,
-		.dev_xstats_reset = NULL,
-		.dev_selftest = NULL,
-		.dev_dump = NULL,
+static struct rte_regexdev_ops cn9k_ree_ops = {
+	.dev_info_get = cn9k_ree_dev_info_get,
+	.dev_configure = cn9k_ree_dev_config,
+	.dev_qp_setup = cn9k_ree_queue_pair_setup,
+	.dev_start = cn9k_ree_start,
+	.dev_stop = cn9k_ree_stop,
+	.dev_close = cn9k_ree_close,
+	.dev_attr_get = NULL,
+	.dev_attr_set = NULL,
+	.dev_rule_db_update = cn9k_ree_rule_db_update,
+	.dev_rule_db_compile_activate =
+			cn9k_ree_rule_db_compile_activate,
+	.dev_db_import = cn9k_ree_rule_db_import,
+	.dev_db_export = cn9k_ree_rule_db_export,
+	.dev_xstats_names_get = NULL,
+	.dev_xstats_get = NULL,
+	.dev_xstats_by_name_get = NULL,
+	.dev_xstats_reset = NULL,
+	.dev_selftest = NULL,
+	.dev_dump = NULL,
 };
 
 static int
-otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+cn9k_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		   struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
-	struct otx2_ree_data *data;
-	struct otx2_dev *otx2_dev;
+	struct cn9k_ree_data *data;
 	struct rte_regexdev *dev;
-	uint8_t max_matches = 0;
-	struct otx2_ree_vf *vf;
-	uint16_t nb_queues = 0;
+	struct roc_ree_vf *vf;
 	int ret;
 
+	ret = roc_plt_init();
+	if (ret < 0) {
+		plt_err("Failed to initialize platform model");
+		return ret;
+	}
+
 	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
 
 	dev = ree_dev_register(name);
@@ -887,63 +872,19 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		goto exit;
 	}
 
-	dev->dev_ops = &otx2_ree_ops;
+	dev->dev_ops = &cn9k_ree_ops;
 	dev->device = &pci_dev->device;
 
 	/* Get private data space allocated */
 	data = dev->data->dev_private;
 	vf = &data->vf;
-
-	otx2_dev = &vf->otx2_dev;
-
-	/* Initialize the base otx2_dev object */
-	ret = otx2_dev_init(pci_dev, otx2_dev);
+	vf->pci_dev = pci_dev;
+	ret = roc_ree_dev_init(vf);
 	if (ret) {
-		otx2_err("Could not initialize otx2_dev");
+		plt_err("Failed to initialize roc cpt rc=%d", ret);
 		goto dev_unregister;
 	}
-	/* Get REE block address */
-	vf->block_address = ree_get_blkaddr(otx2_dev);
-	if (!vf->block_address) {
-		otx2_err("Could not determine block PF number");
-		goto otx2_dev_fini;
-	}
-
-	/* Get number of queues available on the device */
-	ret = otx2_ree_available_queues_get(dev, &nb_queues);
-	if (ret) {
-		otx2_err("Could not determine the number of queues available");
-		goto otx2_dev_fini;
-	}
-
-	/* Don't exceed the limits set per VF */
-	nb_queues = RTE_MIN(nb_queues, OTX2_REE_MAX_QUEUES_PER_VF);
-
-	if (nb_queues == 0) {
-		otx2_err("No free queues available on the device");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_queues = nb_queues;
-
-	otx2_ree_dbg("Max queues supported by device: %d", vf->max_queues);
-
-	/* Get number of maximum matches supported on the device */
-	ret = otx2_ree_max_matches_get(dev, &max_matches);
-	if (ret) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-	/* Don't exceed the limits set per VF */
-	max_matches = RTE_MIN(max_matches, OTX2_REE_MAX_MATCHES_PER_VF);
-	if (max_matches == 0) {
-		otx2_err("Could not determine the maximum matches supported");
-		goto otx2_dev_fini;
-	}
-
-	vf->max_matches = max_matches;
 
-	otx2_ree_dbg("Max matches supported by device: %d", vf->max_matches);
 	data->rule_flags = RTE_REGEX_PCRE_RULE_ALLOW_EMPTY_F |
 			RTE_REGEX_PCRE_RULE_ANCHORED_F;
 	data->regexdev_capa = 0;
@@ -954,18 +895,16 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	dev->state = RTE_REGEXDEV_READY;
 	return 0;
 
-otx2_dev_fini:
-	otx2_dev_fini(pci_dev, otx2_dev);
 dev_unregister:
 	ree_dev_unregister(dev);
 exit:
-	otx2_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
+	cn9k_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
 		    pci_dev->id.vendor_id, pci_dev->id.device_id);
 	return ret;
 }
 
 static int
-otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
+cn9k_ree_pci_remove(struct rte_pci_device *pci_dev)
 {
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
 	struct rte_regexdev *dev = NULL;
@@ -986,20 +925,20 @@ otx2_ree_pci_remove(struct rte_pci_device *pci_dev)
 static struct rte_pci_id pci_id_ree_table[] = {
 	{
 		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-				PCI_DEVID_OCTEONTX2_RVU_REE_PF)
+				PCI_DEVID_CNXK_RVU_REE_PF)
 	},
 	{
 		.vendor_id = 0,
 	}
 };
 
-static struct rte_pci_driver otx2_regexdev_pmd = {
+static struct rte_pci_driver cn9k_regexdev_pmd = {
 	.id_table = pci_id_ree_table,
 	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
-	.probe = otx2_ree_pci_probe,
-	.remove = otx2_ree_pci_remove,
+	.probe = cn9k_ree_pci_probe,
+	.remove = cn9k_ree_pci_remove,
 };
 
 
-RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_OCTEONTX2_PMD, otx2_regexdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_OCTEONTX2_PMD, pci_id_ree_table);
+RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_CN9K_PMD, cn9k_regexdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_CN9K_PMD, pci_id_ree_table);
diff --git a/drivers/regex/cn9k/cn9k_regexdev.h b/drivers/regex/cn9k/cn9k_regexdev.h
new file mode 100644
index 0000000000..c715502167
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_H_
+#define _CN9K_REGEXDEV_H_
+
+#include <rte_common.h>
+#include <rte_regexdev.h>
+
+#include "roc_api.h"
+
+#define cn9k_ree_dbg plt_ree_dbg
+#define cn9k_err plt_err
+
+#define ree_func_trace cn9k_ree_dbg
+
+/* Marvell CN9K Regex PMD device name */
+#define REGEXDEV_NAME_CN9K_PMD	regex_cn9k
+
+/**
+ * Device private data
+ */
+struct cn9k_ree_data {
+	uint32_t regexdev_capa;
+	uint64_t rule_flags;
+	/**< Feature flags exposes HW/SW features for the given device */
+	uint16_t max_rules_per_group;
+	/**< Maximum rules supported per subset by this device */
+	uint16_t max_groups;
+	/**< Maximum subset supported by this device */
+	void **queue_pairs;
+	/**< Array of pointers to queue pairs. */
+	uint16_t nb_queue_pairs;
+	/**< Number of device queue pairs. */
+	struct roc_ree_vf vf;
+	/**< vf data */
+	struct rte_regexdev_rule *rules;
+	/**< rules to be compiled */
+	uint16_t nb_rules;
+	/**< number of rules */
+} __rte_cache_aligned;
+
+#endif /* _CN9K_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.c b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
similarity index 86%
rename from drivers/regex/octeontx2/otx2_regexdev_compiler.c
rename to drivers/regex/cn9k/cn9k_regexdev_compiler.c
index 785459f741..935b8a53b4 100644
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.c
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.c
@@ -5,9 +5,8 @@
 #include <rte_malloc.h>
 #include <rte_regexdev.h>
 
-#include "otx2_regexdev.h"
-#include "otx2_regexdev_compiler.h"
-#include "otx2_regexdev_mbox.h"
+#include "cn9k_regexdev.h"
+#include "cn9k_regexdev_compiler.h"
 
 #ifdef REE_COMPILER_SDK
 #include <rxp-compiler.h>
@@ -65,7 +64,7 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 			nb_rules*sizeof(struct rxp_rule_entry), 0);
 
 	if (ruleset.rules == NULL) {
-		otx2_err("Could not allocate memory for rule compilation\n");
+		cn9k_err("Could not allocate memory for rule compilation\n");
 		return -EFAULT;
 	}
 	if (rof_for_incremental_compile)
@@ -126,9 +125,10 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,
 }
 
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
-	struct otx2_ree_data *data = dev->data->dev_private;
+	struct cn9k_ree_data *data = dev->data->dev_private;
+	struct roc_ree_vf *vf = &data->vf;
 	char compiler_version[] = "20.5.2.eda0fa2";
 	char timestamp[] = "19700101_000001";
 	uint32_t rule_db_len, rule_dbi_len;
@@ -144,25 +144,25 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 
 	ree_func_trace();
 
-	ret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);
+	ret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);
 	if (ret != 0) {
-		otx2_err("Could not get rule db length");
+		cn9k_err("Could not get rule db length");
 		return ret;
 	}
 
 	if (rule_db_len > 0) {
-		otx2_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
+		cn9k_ree_dbg("Incremental compile, rule db len %d rule dbi len %d",
 				rule_db_len, rule_dbi_len);
 		rule_db = rte_malloc("ree_rule_db", rule_db_len, 0);
 		if (!rule_db) {
-			otx2_err("Could not allocate memory for rule db");
+			cn9k_err("Could not allocate memory for rule db");
 			return -EFAULT;
 		}
 
-		ret = otx2_ree_rule_db_get(dev, rule_db, rule_db_len,
+		ret = roc_ree_rule_db_get(vf, rule_db, rule_db_len,
 				(char *)rule_dbi, rule_dbi_len);
 		if (ret) {
-			otx2_err("Could not read rule db");
+			cn9k_err("Could not read rule db");
 			rte_free(rule_db);
 			return -EFAULT;
 		}
@@ -188,7 +188,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 		ret = ree_rule_db_compile(data->rules, data->nb_rules, &rof,
 				&rofi, &rof_inc, rofi_inc_p);
 		if (rofi->number_of_entries == 0) {
-			otx2_ree_dbg("No change to rule db");
+			cn9k_ree_dbg("No change to rule db");
 			ret = 0;
 			goto free_structs;
 		}
@@ -201,14 +201,14 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 				&rofi, NULL, NULL);
 	}
 	if (ret != 0) {
-		otx2_err("Could not compile rule db");
+		cn9k_err("Could not compile rule db");
 		goto free_structs;
 	}
 	rule_db_len = rof->number_of_entries * sizeof(struct rxp_rof_entry);
-	ret = otx2_ree_rule_db_prog(dev, (char *)rof->rof_entries, rule_db_len,
+	ret = roc_ree_rule_db_prog(vf, (char *)rof->rof_entries, rule_db_len,
 			rofi_rof_entries, rule_dbi_len);
 	if (ret)
-		otx2_err("Could not program rule db");
+		cn9k_err("Could not program rule db");
 
 free_structs:
 	rxp_free_structs(NULL, NULL, NULL, NULL, NULL, &rof, NULL, &rofi, NULL,
@@ -221,7 +221,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 }
 #else
 int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)
 {
 	RTE_SET_USED(dev);
 	return -ENOTSUP;
diff --git a/drivers/regex/cn9k/cn9k_regexdev_compiler.h b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
new file mode 100644
index 0000000000..4c29a69ada
--- /dev/null
+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef _CN9K_REGEXDEV_COMPILER_H_
+#define _CN9K_REGEXDEV_COMPILER_H_
+
+int
+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev);
+
+#endif /* _CN9K_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/meson.build b/drivers/regex/cn9k/meson.build
similarity index 65%
rename from drivers/regex/octeontx2/meson.build
rename to drivers/regex/cn9k/meson.build
index 3f81add5bf..bb0504fba1 100644
--- a/drivers/regex/octeontx2/meson.build
+++ b/drivers/regex/cn9k/meson.build
@@ -16,12 +16,10 @@ if lib.found()
 endif
 
 sources = files(
-        'otx2_regexdev.c',
-        'otx2_regexdev_compiler.c',
-        'otx2_regexdev_hw_access.c',
-        'otx2_regexdev_mbox.c',
+        'cn9k_regexdev.c',
+        'cn9k_regexdev_compiler.c',
 )
 
-deps += ['bus_pci', 'common_octeontx2', 'regexdev']
+deps += ['bus_pci', 'regexdev']
+deps += ['common_cnxk', 'mempool_cnxk']
 
-includes += include_directories('../../common/octeontx2')
diff --git a/drivers/regex/octeontx2/version.map b/drivers/regex/cn9k/version.map
similarity index 100%
rename from drivers/regex/octeontx2/version.map
rename to drivers/regex/cn9k/version.map
diff --git a/drivers/regex/meson.build b/drivers/regex/meson.build
index 94222e55fe..7ad55af8ca 100644
--- a/drivers/regex/meson.build
+++ b/drivers/regex/meson.build
@@ -3,6 +3,6 @@
 
 drivers = [
         'mlx5',
-        'octeontx2',
+        'cn9k',
 ]
 std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc
diff --git a/drivers/regex/octeontx2/otx2_regexdev.h b/drivers/regex/octeontx2/otx2_regexdev.h
deleted file mode 100644
index d710535f5f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_H_
-#define _OTX2_REGEXDEV_H_
-
-#include <rte_common.h>
-#include <rte_regexdev.h>
-
-#include "otx2_dev.h"
-
-#define ree_func_trace otx2_ree_dbg
-
-/* Marvell OCTEON TX2 Regex PMD device name */
-#define REGEXDEV_NAME_OCTEONTX2_PMD	regex_octeontx2
-
-#define OTX2_REE_MAX_LFS		36
-#define OTX2_REE_MAX_QUEUES_PER_VF	36
-#define OTX2_REE_MAX_MATCHES_PER_VF	254
-
-#define OTX2_REE_MAX_PAYLOAD_SIZE	(1 << 14)
-
-#define OTX2_REE_NON_INC_PROG 0
-#define OTX2_REE_INC_PROG 1
-
-#define REE_MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
-
-
-/**
- * Device vf data
- */
-struct otx2_ree_vf {
-	struct otx2_dev otx2_dev;
-	/**< Base class */
-	uint16_t max_queues;
-	/**< Max queues supported */
-	uint8_t nb_queues;
-	/**< Number of regex queues attached */
-	uint16_t max_matches;
-	/**<  Max matches supported*/
-	uint16_t lf_msixoff[OTX2_REE_MAX_LFS];
-	/**< MSI-X offsets */
-	uint8_t block_address;
-	/**< REE Block Address */
-	uint8_t err_intr_registered:1;
-	/**< Are error interrupts registered? */
-};
-
-/**
- * Device private data
- */
-struct otx2_ree_data {
-	uint32_t regexdev_capa;
-	uint64_t rule_flags;
-	/**< Feature flags exposes HW/SW features for the given device */
-	uint16_t max_rules_per_group;
-	/**< Maximum rules supported per subset by this device */
-	uint16_t max_groups;
-	/**< Maximum subset supported by this device */
-	void **queue_pairs;
-	/**< Array of pointers to queue pairs. */
-	uint16_t nb_queue_pairs;
-	/**< Number of device queue pairs. */
-	struct otx2_ree_vf vf;
-	/**< vf data */
-	struct rte_regexdev_rule *rules;
-	/**< rules to be compiled */
-	uint16_t nb_rules;
-	/**< number of rules */
-} __rte_cache_aligned;
-
-struct otx2_ree_rid {
-	uintptr_t rid;
-	/** Request id of a ree operation */
-	uint64_t user_id;
-	/* Client data */
-	/**< IOVA address of the pattern to be matched. */
-};
-
-struct otx2_ree_pending_queue {
-	uint64_t pending_count;
-	/** Pending requests count */
-	struct otx2_ree_rid *rid_queue;
-	/** Array of pending requests */
-	uint16_t enq_tail;
-	/** Tail of queue to be used for enqueue */
-	uint16_t deq_head;
-	/** Head of queue to be used for dequeue */
-};
-
-struct otx2_ree_qp {
-	uint32_t id;
-	/**< Queue pair id */
-	uintptr_t base;
-	/**< Base address where BAR is mapped */
-	struct otx2_ree_pending_queue pend_q;
-	/**< Pending queue */
-	rte_iova_t iq_dma_addr;
-	/**< Instruction queue address */
-	uint32_t otx2_regexdev_jobid;
-	/**< Job ID */
-	uint32_t write_offset;
-	/**< write offset */
-	regexdev_stop_flush_t cb;
-	/**< Callback function called during rte_regex_dev_stop()*/
-};
-
-#endif /* _OTX2_REGEXDEV_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.h b/drivers/regex/octeontx2/otx2_regexdev_compiler.h
deleted file mode 100644
index 8d2625bf7f..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_COMPILER_H_
-#define _OTX2_REGEXDEV_COMPILER_H_
-
-int
-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev);
-
-#endif /* _OTX2_REGEXDEV_COMPILER_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c b/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
deleted file mode 100644
index f8031d0f72..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_hw_access.h"
-#include "otx2_regexdev_mbox.h"
-
-static void
-ree_lf_err_intr_handler(void *param)
-{
-	uintptr_t base = (uintptr_t)param;
-	uint8_t lf_id;
-	uint64_t intr;
-
-	lf_id = (base >> 12) & 0xFF;
-
-	intr = otx2_read64(base + OTX2_REE_LF_MISC_INT);
-	if (intr == 0)
-		return;
-
-	otx2_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
-
-	/* Clear interrupt */
-	otx2_write64(intr, base + OTX2_REE_LF_MISC_INT);
-}
-
-static void
-ree_lf_err_intr_unregister(const struct rte_regexdev *dev, uint16_t msix_off,
-			   uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	otx2_unregister_irq(handle, ree_lf_err_intr_handler, (void *)base,
-			    msix_off);
-}
-
-void
-otx2_ree_err_intr_unregister(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uintptr_t base;
-	uint32_t i;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
-	}
-
-	vf->err_intr_registered = 0;
-}
-
-static int
-ree_lf_err_intr_register(const struct rte_regexdev *dev, uint16_t msix_off,
-			 uintptr_t base)
-{
-	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
-	struct rte_intr_handle *handle = pci_dev->intr_handle;
-	int ret;
-
-	/* Disable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
-
-	/* Register error interrupt handler */
-	ret = otx2_register_irq(handle, ree_lf_err_intr_handler, (void *)base,
-				msix_off);
-	if (ret)
-		return ret;
-
-	/* Enable error interrupts */
-	otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1S);
-
-	return 0;
-}
-
-int
-otx2_ree_err_intr_register(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	uint32_t i, j, ret;
-	uintptr_t base;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
-			otx2_err("Invalid REE LF MSI-X offset: 0x%x",
-				    vf->lf_msixoff[i]);
-			return -EINVAL;
-		}
-	}
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_REE_LF_BAR2(vf, i);
-		ret = ree_lf_err_intr_register(dev, vf->lf_msixoff[i], base);
-		if (ret)
-			goto intr_unregister;
-	}
-
-	vf->err_intr_registered = 1;
-	return 0;
-
-intr_unregister:
-	/* Unregister the ones already registered */
-	for (j = 0; j < i; j++) {
-		base = OTX2_REE_LF_BAR2(vf, j);
-		ree_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
-	}
-	return ret;
-}
-
-int
-otx2_ree_iq_enable(const struct rte_regexdev *dev, const struct otx2_ree_qp *qp,
-		   uint8_t pri, uint32_t size_div2)
-{
-	union otx2_ree_lf_sbuf_addr base;
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Set instruction queue size and priority */
-	otx2_ree_config_lf(dev, qp->id, pri, size_div2);
-
-	/* Set instruction queue base address */
-	/* Should be written after SBUF_CTL and before LF_ENA */
-
-	base.u = otx2_read64(qp->base + OTX2_REE_LF_SBUF_ADDR);
-	base.s.ptr = qp->iq_dma_addr >> 7;
-	otx2_write64(base.u, qp->base + OTX2_REE_LF_SBUF_ADDR);
-
-	/* Enable instruction queue */
-
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 1;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-
-	return 0;
-}
-
-void
-otx2_ree_iq_disable(struct otx2_ree_qp *qp)
-{
-	union otx2_ree_lf_ena lf_ena;
-
-	/* Stop instruction execution */
-	lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
-	lf_ena.s.ena = 0x0;
-	otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
-}
-
-int
-otx2_ree_max_matches_get(const struct rte_regexdev *dev, uint8_t *max_matches)
-{
-	union otx2_ree_af_reexm_max_match reexm_max_match;
-	int ret;
-
-	ret = otx2_ree_af_reg_read(dev, REE_AF_REEXM_MAX_MATCH,
-				   &reexm_max_match.u);
-	if (ret)
-		return ret;
-
-	*max_matches = reexm_max_match.s.max;
-	return 0;
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h b/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
deleted file mode 100644
index dedf5f3282..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_HW_ACCESS_H_
-#define _OTX2_REGEXDEV_HW_ACCESS_H_
-
-#include <stdint.h>
-
-#include "otx2_regexdev.h"
-
-/* REE instruction queue length */
-#define OTX2_REE_IQ_LEN			(1 << 13)
-
-#define OTX2_REE_DEFAULT_CMD_QLEN	OTX2_REE_IQ_LEN
-
-/* Status register bits */
-#define OTX2_REE_STATUS_PMI_EOJ_BIT		(1 << 14)
-#define OTX2_REE_STATUS_PMI_SOJ_BIT		(1 << 13)
-#define OTX2_REE_STATUS_MP_CNT_DET_BIT		(1 << 7)
-#define OTX2_REE_STATUS_MM_CNT_DET_BIT		(1 << 6)
-#define OTX2_REE_STATUS_ML_CNT_DET_BIT		(1 << 5)
-#define OTX2_REE_STATUS_MST_CNT_DET_BIT		(1 << 4)
-#define OTX2_REE_STATUS_MPT_CNT_DET_BIT		(1 << 3)
-
-/* Register offsets */
-/* REE LF registers */
-#define OTX2_REE_LF_DONE_INT		0x120ull
-#define OTX2_REE_LF_DONE_INT_W1S	0x130ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1S	0x138ull
-#define OTX2_REE_LF_DONE_INT_ENA_W1C	0x140ull
-#define OTX2_REE_LF_MISC_INT		0x300ull
-#define OTX2_REE_LF_MISC_INT_W1S	0x310ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1S	0x320ull
-#define OTX2_REE_LF_MISC_INT_ENA_W1C	0x330ull
-#define OTX2_REE_LF_ENA			0x10ull
-#define OTX2_REE_LF_SBUF_ADDR		0x20ull
-#define OTX2_REE_LF_DONE		0x100ull
-#define OTX2_REE_LF_DONE_ACK		0x110ull
-#define OTX2_REE_LF_DONE_WAIT		0x148ull
-#define OTX2_REE_LF_DOORBELL		0x400ull
-#define OTX2_REE_LF_OUTSTAND_JOB	0x410ull
-
-/* BAR 0 */
-#define OTX2_REE_AF_QUE_SBUF_CTL(a)	(0x1200ull | (uint64_t)(a) << 3)
-#define OTX2_REE_PRIV_LF_CFG(a)		(0x41000ull | (uint64_t)(a) << 3)
-
-#define OTX2_REE_LF_BAR2(vf, q_id) \
-		((vf)->otx2_dev.bar2 + \
-		 (((vf)->block_address << 20) | ((q_id) << 12)))
-
-
-#define OTX2_REE_QUEUE_HI_PRIO 0x1
-
-enum ree_desc_type_e {
-	REE_TYPE_JOB_DESC    = 0x0,
-	REE_TYPE_RESULT_DESC = 0x1,
-	REE_TYPE_ENUM_LAST   = 0x2
-};
-
-union otx2_ree_priv_lf_cfg {
-	uint64_t u;
-	struct {
-		uint64_t slot                        : 8;
-		uint64_t pf_func                     : 16;
-		uint64_t reserved_24_62              : 39;
-		uint64_t ena                         : 1;
-	} s;
-};
-
-
-union otx2_ree_lf_sbuf_addr {
-	uint64_t u;
-	struct {
-		uint64_t off                         : 7;
-		uint64_t ptr                         : 46;
-		uint64_t reserved_53_63              : 11;
-	} s;
-};
-
-union otx2_ree_lf_ena {
-	uint64_t u;
-	struct {
-		uint64_t ena                         : 1;
-		uint64_t reserved_1_63               : 63;
-	} s;
-};
-
-union otx2_ree_af_reexm_max_match {
-	uint64_t u;
-	struct {
-		uint64_t max                         : 8;
-		uint64_t reserved_8_63               : 56;
-	} s;
-};
-
-union otx2_ree_lf_done {
-	uint64_t u;
-	struct {
-		uint64_t done                        : 20;
-		uint64_t reserved_20_63              : 44;
-	} s;
-};
-
-union otx2_ree_inst {
-	uint64_t u[8];
-	struct  {
-		uint64_t doneint                     :  1;
-		uint64_t reserved_1_3                :  3;
-		uint64_t dg                          :  1;
-		uint64_t reserved_5_7                :  3;
-		uint64_t ooj                         :  1;
-		uint64_t reserved_9_15               :  7;
-		uint64_t reserved_16_63              : 48;
-		uint64_t inp_ptr_addr                : 64;
-		uint64_t inp_ptr_ctl                 : 64;
-		uint64_t res_ptr_addr                : 64;
-		uint64_t wq_ptr                      : 64;
-		uint64_t tag                         : 32;
-		uint64_t tt                          :  2;
-		uint64_t ggrp                        : 10;
-		uint64_t reserved_364_383            : 20;
-		uint64_t reserved_384_391            :  8;
-		uint64_t ree_job_id                  : 24;
-		uint64_t ree_job_ctrl                : 16;
-		uint64_t ree_job_length              : 15;
-		uint64_t reserved_447_447            :  1;
-		uint64_t ree_job_subset_id_0         : 16;
-		uint64_t ree_job_subset_id_1         : 16;
-		uint64_t ree_job_subset_id_2         : 16;
-		uint64_t ree_job_subset_id_3         : 16;
-	} cn98xx;
-};
-
-union otx2_ree_res_status {
-	uint64_t u;
-	struct {
-		uint64_t job_type                    :  3;
-		uint64_t mpt_cnt_det                 :  1;
-		uint64_t mst_cnt_det                 :  1;
-		uint64_t ml_cnt_det                  :  1;
-		uint64_t mm_cnt_det                  :  1;
-		uint64_t mp_cnt_det                  :  1;
-		uint64_t mode                        :  2;
-		uint64_t reserved_10_11              :  2;
-		uint64_t reserved_12_12              :  1;
-		uint64_t pmi_soj                     :  1;
-		uint64_t pmi_eoj                     :  1;
-		uint64_t reserved_15_15              :  1;
-		uint64_t reserved_16_63              : 48;
-	} s;
-};
-
-union otx2_ree_res {
-	uint64_t u[8];
-	struct ree_res_s_98 {
-		uint64_t done			:  1;
-		uint64_t hwjid			:  7;
-		uint64_t ree_res_job_id		: 24;
-		uint64_t ree_res_status		: 16;
-		uint64_t ree_res_dmcnt		:  8;
-		uint64_t ree_res_mcnt		:  8;
-		uint64_t ree_meta_ptcnt		: 16;
-		uint64_t ree_meta_icnt		: 16;
-		uint64_t ree_meta_lcnt		: 16;
-		uint64_t ree_pmi_min_byte_ptr	: 16;
-		uint64_t ree_err		:  1;
-		uint64_t reserved_129_190	: 62;
-		uint64_t doneint		:  1;
-		uint64_t reserved_192_255	: 64;
-		uint64_t reserved_256_319	: 64;
-		uint64_t reserved_320_383	: 64;
-		uint64_t reserved_384_447	: 64;
-		uint64_t reserved_448_511	: 64;
-	} s;
-};
-
-union otx2_ree_match {
-	uint64_t u;
-	struct {
-		uint64_t ree_rule_id                 : 32;
-		uint64_t start_ptr                   : 14;
-		uint64_t reserved_46_47              :  2;
-		uint64_t match_length                : 15;
-		uint64_t reserved_63_63              :  1;
-	} s;
-};
-
-void otx2_ree_err_intr_unregister(const struct rte_regexdev *dev);
-
-int otx2_ree_err_intr_register(const struct rte_regexdev *dev);
-
-int otx2_ree_iq_enable(const struct rte_regexdev *dev,
-		       const struct otx2_ree_qp *qp,
-		       uint8_t pri, uint32_t size_div128);
-
-void otx2_ree_iq_disable(struct otx2_ree_qp *qp);
-
-int otx2_ree_max_matches_get(const struct rte_regexdev *dev,
-			     uint8_t *max_matches);
-
-#endif /* _OTX2_REGEXDEV_HW_ACCESS_H_ */
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.c b/drivers/regex/octeontx2/otx2_regexdev_mbox.c
deleted file mode 100644
index 6d58d367d4..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#include "otx2_common.h"
-#include "otx2_dev.h"
-#include "otx2_regexdev_mbox.h"
-#include "otx2_regexdev.h"
-
-int
-otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-			      uint16_t *nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct free_rsrcs_rsp *rsp;
-	struct otx2_dev *otx2_dev;
-	int ret;
-
-	otx2_dev = &vf->otx2_dev;
-	otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);
-
-	ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
-	if (ret)
-		return -EIO;
-
-	if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-		*nb_queues = rsp->ree0;
-	else
-		*nb_queues = rsp->ree1;
-	return 0;
-}
-
-int
-otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_attach_req *req;
-	struct otx2_mbox *mbox;
-
-	/* Ask AF to attach required LFs */
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_attach_resources(mbox);
-
-	/* 1 LF = 1 queue */
-	req->reelfs = nb_queues;
-	req->ree_blkaddr = vf->block_address;
-
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Update number of attached queues */
-	vf->nb_queues = nb_queues;
-
-	return 0;
-}
-
-int
-otx2_ree_queues_detach(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct rsrc_detach_req *req;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_detach_resources(mbox);
-	req->reelfs = true;
-	req->partial = true;
-	if (otx2_mbox_process(mbox) < 0)
-		return -EIO;
-
-	/* Queues have been detached */
-	vf->nb_queues = 0;
-
-	return 0;
-}
-
-int
-otx2_ree_msix_offsets_get(const struct rte_regexdev *dev)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct msix_offset_rsp *rsp;
-	struct otx2_mbox *mbox;
-	uint32_t i, ret;
-
-	/* Get REE MSI-X vector offsets */
-	mbox = vf->otx2_dev.mbox;
-	otx2_mbox_alloc_msg_msix_offset(mbox);
-
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-
-	for (i = 0; i < vf->nb_queues; i++) {
-		if (vf->block_address == RVU_BLOCK_ADDR_REE0)
-			vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
-		else
-			vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
-		otx2_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
-	}
-
-	return 0;
-}
-
-static int
-ree_send_mbox_msg(struct otx2_ree_vf *vf)
-{
-	struct otx2_mbox *mbox = vf->otx2_dev.mbox;
-	int ret;
-
-	otx2_mbox_msg_send(mbox, 0);
-
-	ret = otx2_mbox_wait_for_rsp(mbox, 0);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-
-	return 0;
-}
-
-int
-otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		   uint32_t size)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_lf_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = otx2_mbox_alloc_msg_ree_config_lf(mbox);
-
-	req->lf = lf;
-	req->pri =  pri ? 1 : 0;
-	req->size = size;
-	req->blkaddr = vf->block_address;
-
-	ret = otx2_mbox_process(mbox);
-	if (ret < 0) {
-		otx2_err("Could not get mailbox response");
-		return ret;
-	}
-	return 0;
-}
-
-int
-otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-		     uint64_t *val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox_dev *mdev;
-	struct otx2_mbox *mbox;
-	int ret, off;
-
-	mbox = vf->otx2_dev.mbox;
-	mdev = &mbox->dev[0];
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 0;
-	msg->reg_offset = reg;
-	msg->ret_val = val;
-	msg->blkaddr = vf->block_address;
-
-	ret = ree_send_mbox_msg(vf);
-	if (ret < 0)
-		return ret;
-
-	off = mbox->rx_start +
-			RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
-	msg = (struct ree_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);
-
-	*val = msg->val;
-
-	return 0;
-}
-
-int
-otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-		      uint64_t val)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_rd_wr_reg_msg *msg;
-	struct otx2_mbox *mbox;
-
-	mbox = vf->otx2_dev.mbox;
-	msg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,
-						sizeof(*msg), sizeof(*msg));
-	if (msg == NULL) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	msg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;
-	msg->hdr.sig = OTX2_MBOX_REQ_SIG;
-	msg->hdr.pcifunc = vf->otx2_dev.pf_func;
-	msg->is_write = 1;
-	msg->reg_offset = reg;
-	msg->val = val;
-	msg->blkaddr = vf->block_address;
-
-	return ree_send_mbox_msg(vf);
-}
-
-int
-otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_get_req_msg *req;
-	struct ree_rule_db_get_rsp_msg *rsp;
-	char *rule_db_ptr = (char *)rule_db;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct otx2_mbox *mbox;
-	int ret, last = 0;
-	uint32_t len = 0;
-
-	mbox = vf->otx2_dev.mbox;
-	if (!rule_db) {
-		otx2_err("Couldn't return rule db due to NULL pointer");
-		return -EFAULT;
-	}
-
-	while (!last) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 0;
-		req->offset = len;
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_db_len < len + rsp->len) {
-			otx2_err("Rule db size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);
-		len += rsp->len;
-		rule_db_ptr = rule_db_ptr + rsp->len;
-		last = rsp->is_last;
-	}
-
-	if (rule_dbi) {
-		req = (struct ree_rule_db_get_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_GET;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->blkaddr = vf->block_address;
-		req->is_dbi = 1;
-		req->offset = 0;
-
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret)
-			return ret;
-		if (rule_dbi_len < rsp->len) {
-			otx2_err("Rule dbi size is too small");
-			return -EFAULT;
-		}
-		otx2_mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-		uint32_t *rule_db_len,
-		uint32_t *rule_dbi_len)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	struct ree_rule_db_len_rsp_msg *rsp;
-	struct otx2_ree_vf *vf = &data->vf;
-	struct ree_req_msg *req;
-	struct otx2_mbox *mbox;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	req = (struct ree_req_msg *)
-		otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), sizeof(*rsp));
-	if (!req) {
-		otx2_err("Could not allocate mailbox message");
-		return -EFAULT;
-	}
-
-	req->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;
-	req->hdr.sig = OTX2_MBOX_REQ_SIG;
-	req->hdr.pcifunc = vf->otx2_dev.pf_func;
-	req->blkaddr = vf->block_address;
-	ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-	if (ret)
-		return ret;
-	if (rule_db_len != NULL)
-		*rule_db_len = rsp->len;
-	if (rule_dbi_len != NULL)
-		*rule_dbi_len = rsp->inc_len;
-
-	return 0;
-}
-
-static int
-ree_db_msg(const struct rte_regexdev *dev, const char *db, uint32_t db_len,
-		int inc, int dbi)
-{
-	struct otx2_ree_data *data = dev->data->dev_private;
-	uint32_t len_left = db_len, offset = 0;
-	struct ree_rule_db_prog_req_msg *req;
-	struct otx2_ree_vf *vf = &data->vf;
-	const char *rule_db_ptr = db;
-	struct otx2_mbox *mbox;
-	struct msg_rsp *rsp;
-	int ret;
-
-	mbox = vf->otx2_dev.mbox;
-	while (len_left) {
-		req = (struct ree_rule_db_prog_req_msg *)
-			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
-						sizeof(*rsp));
-		if (!req) {
-			otx2_err("Could not allocate mailbox message");
-			return -EFAULT;
-		}
-		req->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;
-		req->hdr.sig = OTX2_MBOX_REQ_SIG;
-		req->hdr.pcifunc = vf->otx2_dev.pf_func;
-		req->offset = offset;
-		req->total_len = db_len;
-		req->len = REE_RULE_DB_REQ_BLOCK_SIZE;
-		req->is_incremental = inc;
-		req->is_dbi = dbi;
-		req->blkaddr = vf->block_address;
-
-		if (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {
-			req->is_last = true;
-			req->len = len_left;
-		}
-		otx2_mbox_memcpy(req->rule_db, rule_db_ptr, req->len);
-		ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
-		if (ret) {
-			otx2_err("Programming mailbox processing failed");
-			return ret;
-		}
-		len_left -= req->len;
-		offset += req->len;
-		rule_db_ptr = rule_db_ptr + req->len;
-	}
-	return 0;
-}
-
-int
-otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len)
-{
-	int inc, ret;
-
-	if (rule_db_len == 0) {
-		otx2_err("Couldn't program empty rule db");
-		return -EFAULT;
-	}
-	inc = (rule_dbi_len != 0);
-	if ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {
-		otx2_err("Couldn't program NULL rule db");
-		return -EFAULT;
-	}
-	if (inc) {
-		ret = ree_db_msg(dev, rule_dbi, rule_dbi_len, inc, 1);
-		if (ret)
-			return ret;
-	}
-	return ree_db_msg(dev, rule_db, rule_db_len, inc, 0);
-}
diff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.h b/drivers/regex/octeontx2/otx2_regexdev_mbox.h
deleted file mode 100644
index 953efa6724..0000000000
--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
- */
-
-#ifndef _OTX2_REGEXDEV_MBOX_H_
-#define _OTX2_REGEXDEV_MBOX_H_
-
-#include <rte_regexdev.h>
-
-int otx2_ree_available_queues_get(const struct rte_regexdev *dev,
-				  uint16_t *nb_queues);
-
-int otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues);
-
-int otx2_ree_queues_detach(const struct rte_regexdev *dev);
-
-int otx2_ree_msix_offsets_get(const struct rte_regexdev *dev);
-
-int otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,
-		       uint32_t size);
-
-int otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,
-			 uint64_t *val);
-
-int otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,
-			  uint64_t val);
-
-int otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,
-		 uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len);
-
-int otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,
-			     uint32_t *rule_db_len, uint32_t *rule_dbi_len);
-
-int otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,
-		uint32_t rule_db_len, const char *rule_dbi,
-		uint32_t rule_dbi_len);
-
-#endif /* _OTX2_REGEXDEV_MBOX_H_ */
-- 
2.28.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

end of thread, other threads:[~2021-11-29 20:00 UTC | newest]

Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-03  6:23 [dpdk-dev] [PATCH] common/cnxk: add REE support lironh
2021-10-28  9:30 ` Jerin Jacob
2021-11-23 19:13 ` [PATCH v2 0/5] regex/cn9k: use cnxk infrastructure lironh
2021-11-23 19:13   ` [PATCH v2 1/5] common/cnxk: add REE HW definitions lironh
2021-11-23 19:13   ` [PATCH v2 2/5] common/cnxk: add REE mbox definitions lironh
2021-11-23 19:13   ` [PATCH v2 3/5] common/cnxk: add REE support lironh
2021-11-23 19:13   ` [PATCH v2 4/5] common/cnxk: link REE support to ROC files lironh
2021-11-23 19:13   ` [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure lironh
     [not found]     ` <20211123193835.20601-1-robot@bytheb.org>
2021-11-28 20:17       ` [EXT] |FAILURE| pw104631 " Liron Himi
2021-11-28 20:37         ` Thomas Monjalon
2021-11-29  9:55           ` Liron Himi
2021-11-29 10:10             ` Thomas Monjalon
2021-11-29 19:47   ` [PATCH v2 0/5] " lironh
2021-11-29 19:47     ` [PATCH v3 " lironh
2021-11-29 19:47     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
2021-11-29 19:47     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
2021-11-29 19:47     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
2021-11-29 19:47     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
2021-11-29 19:47     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
2021-11-29 19:49   ` [PATCH v3 0/5] " lironh
2021-11-29 19:49     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
2021-11-29 19:49     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
2021-11-29 19:49     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
2021-11-29 19:49     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
2021-11-29 19:49     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh
2021-11-29 19:59   ` [PATCH v3 0/5] " lironh
2021-11-29 19:59     ` [PATCH v3 1/5] common/cnxk: add REE HW definitions lironh
2021-11-29 19:59     ` [PATCH v3 2/5] common/cnxk: add REE mbox definitions lironh
2021-11-29 19:59     ` [PATCH v3 3/5] common/cnxk: add REE support lironh
2021-11-29 19:59     ` [PATCH v3 4/5] common/cnxk: link REE support to ROC files lironh
2021-11-29 19:59     ` [PATCH v3 5/5] regex/cn9k: use cnxk infrastructure lironh

DPDK patches and discussions

This inbox may be cloned and mirrored by anyone:

	git clone --mirror http://inbox.dpdk.org/dev/0 dev/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 dev dev/ http://inbox.dpdk.org/dev \
		dev@dpdk.org
	public-inbox-index dev

Example config snippet for mirrors.
Newsgroup available over NNTP:
	nntp://inbox.dpdk.org/inbox.dpdk.dev


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git