Re: [dpdk-dev] [PATCH v5 2/3] PCI: support MMIO in rte_pci_ioport_map/unap/read/write

[Ferruh Yigit <ferruh.yigit@intel.com>]

On 10/22/2020 4:51 PM, 谢华伟(此时此刻） wrote:
> From: "huawei.xhw" <huawei.xhw@alibaba-inc.com>
> 
> If IO BAR, we get PIO address.
> If MMIO BAR, we get mapped virtual address.
> We distinguish PIO and MMIO by their address like how kernel does.
> ioread/write8/16/32 is provided to access PIO/MMIO.
> BTW, for virtio on arch other than x86, BAR flag indicates PIO but is mapped.
> 
> Signed-off-by: huawei.xhw <huawei.xhw@alibaba-inc.com>

<...>

> @@ -408,15 +403,30 @@
>   		&end_addr, &flags) < 0)
>   		goto error;
>   
> -	if (!(flags & IORESOURCE_IO)) {
> -		RTE_LOG(ERR, EAL, "%s(): bar resource other than IO is not supported\n", __func__);
> +	if (flags & IORESOURCE_IO) {
> +		iobar = 1;
> +		base = (unsigned long)phys_addr;
> +		RTE_LOG(INFO, EAL, "%s(): PIO BAR %08lx detected\n", __func__, base);
> +	} else if (flags & IORESOURCE_MEM) {
> +		iobar = 0;
> +		base = (unsigned long)dev->mem_resource[bar].addr;

Hi Huawei,

At this stage, to have a valid 'addr' it should be already mmap'ed, can you 
please provide the call stack when it is set/mmaped, to confirm it will be 
always valid at this point?

Thanks,
ferruh