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* [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture
@ 2014-09-26  9:36 Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 01/12] Add compiling definations for IBM " Chao Zhu
                   ` (12 more replies)
  0 siblings, 13 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

The set of patches add IBM Power architecture to the DPDK. It adds the required support to the
EAL library. This set of patches doesn't support full function on Power processors. Many functions
are turned off in configuratidon. More patches will be added continuesly.

Chao Zhu (12):
  Add compiling definations for IBM Power architecture
  Add atomic operations for IBM Power architecture
  Add byte order operations for IBM Power architecture
  Add CPU cycle operations for IBM Power architecture
  Add prefetch operation for IBM Power architecture
  Add spinlock operation for IBM Power architecture
  Add vector memcpy for IBM Power architecture
  Add CPU flag checking for IBM Power architecture
  Remove iopl operation for IBM Power architecture
  Add cache size define for IBM Power Architecture
  Add huge page sizes for IBM Power architecture
  Add memory support for IBM Power Architecture

 app/test/test_cpuflags.c                           |   35 ++
 app/test/test_malloc.c                             |    8 +-
 app/test/test_mbuf.c                               |    2 +-
 app/test/test_memzone.c                            |  119 ++++++-
 config/common_linuxapp_powerpc                     |  388 ++++++++++++++++++++
 config/defconfig_ppc_64-native-linuxapp-gcc        |   42 +++
 config/defconfig_x86_64-native-linuxapp-clang      |    1 +
 config/defconfig_x86_64-native-linuxapp-gcc        |    1 +
 config/defconfig_x86_64-native-linuxapp-icc        |    1 +
 lib/librte_eal/common/eal_common_memzone.c         |   15 +-
 .../common/include/powerpc/arch/rte_atomic.h       |  387 +++++++++++++++++++
 .../common/include/powerpc/arch/rte_atomic_arch.h  |  318 ++++++++++++++++
 .../include/powerpc/arch/rte_byteorder_arch.h      |   79 ++++
 .../include/powerpc/arch/rte_cpuflags_arch.h       |  199 ++++++++++
 .../common/include/powerpc/arch/rte_cycles_arch.h  |   67 ++++
 .../common/include/powerpc/arch/rte_memcpy_arch.h  |  129 +++++++
 .../include/powerpc/arch/rte_prefetch_arch.h       |   67 ++++
 .../include/powerpc/arch/rte_spinlock_arch.h       |   88 +++++
 lib/librte_eal/common/include/rte_byteorder.h      |   66 ++++
 lib/librte_eal/common/include/rte_memory.h         |    9 +-
 lib/librte_eal/common/include/rte_memzone.h        |    8 +
 lib/librte_eal/linuxapp/eal/eal.c                  |   16 +-
 lib/librte_eal/linuxapp/eal/eal_memory.c           |   19 +-
 mk/arch/powerpc/rte.vars.mk                        |   39 ++
 mk/machine/powerpc/rte.vars.mk                     |   57 +++
 mk/rte.cpuflags.mk                                 |   17 +
 26 files changed, 2161 insertions(+), 16 deletions(-)
 create mode 100644 config/common_linuxapp_powerpc
 create mode 100644 config/defconfig_ppc_64-native-linuxapp-gcc
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_byteorder_arch.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_cpuflags_arch.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_memcpy_arch.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_spinlock_arch.h
 create mode 100644 mk/arch/powerpc/rte.vars.mk
 create mode 100644 mk/machine/powerpc/rte.vars.mk

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 01/12] Add compiling definations for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 02/12] Add atomic operations " Chao Zhu
                   ` (11 subsequent siblings)
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

To make DPDK run on IBM Power architecture, configuration files for
Power architecuture are added. Also, the compiling related .mk files are
added.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 config/common_linuxapp_powerpc              |  388 +++++++++++++++++++++++++++
 config/defconfig_ppc_64-native-linuxapp-gcc |   40 +++
 mk/arch/powerpc/rte.vars.mk                 |   39 +++
 mk/machine/powerpc/rte.vars.mk              |   57 ++++
 4 files changed, 524 insertions(+), 0 deletions(-)
 create mode 100644 config/common_linuxapp_powerpc
 create mode 100644 config/defconfig_ppc_64-native-linuxapp-gcc
 create mode 100644 mk/arch/powerpc/rte.vars.mk
 create mode 100644 mk/machine/powerpc/rte.vars.mk

diff --git a/config/common_linuxapp_powerpc b/config/common_linuxapp_powerpc
new file mode 100644
index 0000000..1ca70fb
--- /dev/null
+++ b/config/common_linuxapp_powerpc
@@ -0,0 +1,388 @@
+#   BSD LICENSE
+#
+#   Copyright (C) IBM Corporation 2014.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of IBM Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+#
+# define executive environment
+#
+# CONFIG_RTE_EXEC_ENV can be linuxapp, baremetal, bsdapp
+#
+CONFIG_RTE_EXEC_ENV="linuxapp"
+CONFIG_RTE_EXEC_ENV_LINUXAPP=y
+
+#
+# Use intrinsics or assembly code for key routines
+#
+CONFIG_RTE_FORCE_INTRINSICS=n
+
+#
+# Compile to share library
+#
+CONFIG_RTE_BUILD_SHARED_LIB=n
+
+#
+# Combine to one single library
+#
+CONFIG_RTE_BUILD_COMBINE_LIBS=n
+CONFIG_RTE_LIBNAME="powerpc_dpdk"
+
+#
+# Compile libc directory
+#
+CONFIG_RTE_LIBC=n
+
+#
+# Compile newlib as libc from source
+#
+CONFIG_RTE_LIBC_NEWLIB_SRC=n
+
+#
+# Use binary newlib
+#
+CONFIG_RTE_LIBC_NEWLIB_BIN=n
+
+#
+# Use binary newlib
+#
+CONFIG_RTE_LIBC_NETINCS=n
+
+#
+# Compile libgloss (newlib-stubs)
+#
+CONFIG_RTE_LIBGLOSS=n
+
+#
+# Compile Environment Abstraction Layer
+# Note: Power8 has 96 cores, so increase CONFIG_RTE_MAX_LCORE from 64 to 128
+#
+CONFIG_RTE_LIBRTE_EAL=y
+CONFIG_RTE_MAX_LCORE=128
+CONFIG_RTE_MAX_NUMA_NODES=8
+CONFIG_RTE_MAX_MEMSEG=256
+CONFIG_RTE_MAX_MEMZONE=2560
+CONFIG_RTE_MAX_TAILQ=32
+CONFIG_RTE_LOG_LEVEL=8
+CONFIG_RTE_LOG_HISTORY=256
+CONFIG_RTE_LIBEAL_USE_HPET=n
+CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n
+CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n
+CONFIG_RTE_EAL_IGB_UIO=y
+CONFIG_RTE_EAL_VFIO=y
+
+#
+# Special configurations in PCI Config Space for high performance
+#
+CONFIG_RTE_PCI_CONFIG=n
+CONFIG_RTE_PCI_EXTENDED_TAG=""
+CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE=0
+
+#
+# Compile Environment Abstraction Layer for linux
+#
+CONFIG_RTE_LIBRTE_EAL_LINUXAPP=y
+
+#
+# Compile Environment Abstraction Layer for Bare metal
+#
+CONFIG_RTE_LIBRTE_EAL_BAREMETAL=n
+
+#
+# Compile Environment Abstraction Layer to support Vmware TSC map
+# Note: Power doesn't have this support
+#
+CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n
+
+#
+# Compile the argument parser library
+#
+CONFIG_RTE_LIBRTE_KVARGS=y
+
+#
+# Compile generic ethernet library
+#
+CONFIG_RTE_LIBRTE_ETHER=y
+CONFIG_RTE_LIBRTE_ETHDEV_DEBUG=n
+CONFIG_RTE_MAX_ETHPORTS=32
+CONFIG_RTE_LIBRTE_IEEE1588=n
+CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS=16
+
+#
+# Support NIC bypass logic
+#
+CONFIG_RTE_NIC_BYPASS=n
+
+#
+# Note: Initially, all of the PMD drivers compilation are turned off on Power
+# Will turn on them only after the successful testing on Power
+#
+
+#
+# Compile burst-oriented IGB & EM PMD drivers
+#
+CONFIG_RTE_LIBRTE_EM_PMD=n
+CONFIG_RTE_LIBRTE_IGB_PMD=n
+CONFIG_RTE_LIBRTE_E1000_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_E1000_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_E1000_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_E1000_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n
+
+#
+# Compile burst-oriented IXGBE PMD driver
+#
+CONFIG_RTE_LIBRTE_IXGBE_PMD=n
+CONFIG_RTE_LIBRTE_IXGBE_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_IXGBE_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_IXGBE_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC=n
+CONFIG_RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y
+CONFIG_RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP=n
+CONFIG_RTE_IXGBE_INC_VECTOR=y
+CONFIG_RTE_IXGBE_RX_OLFLAGS_ENABLE=y
+
+#
+# Compile burst-oriented I40E PMD driver
+#
+CONFIG_RTE_LIBRTE_I40E_PMD=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_I40E_PF_DISABLE_STRIP_CRC=n
+CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y
+CONFIG_RTE_LIBRTE_I40E_ALLOW_UNSUPPORTED_SFP=n
+CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n
+CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4
+# interval up to 8160 us, aligned to 2 (or default value)
+CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1
+
+#
+# Compile burst-oriented VIRTIO PMD driver
+#
+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
+CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_DUMP=n
+
+#
+# Compile burst-oriented VMXNET3 PMD driver
+#
+CONFIG_RTE_LIBRTE_VMXNET3_PMD=n
+CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_DRIVER=n
+
+#
+# Compile example software rings based PMD
+#
+CONFIG_RTE_LIBRTE_PMD_RING=y
+CONFIG_RTE_PMD_RING_MAX_RX_RINGS=16
+CONFIG_RTE_PMD_RING_MAX_TX_RINGS=16
+
+#
+# Compile software PMD backed by PCAP files
+#
+CONFIG_RTE_LIBRTE_PMD_PCAP=n
+
+#
+# Compile link bonding PMD library
+#
+CONFIG_RTE_LIBRTE_PMD_BOND=n
+
+#
+# Compile Xen PMD
+#
+CONFIG_RTE_LIBRTE_PMD_XENVIRT=n
+
+#
+# Do prefetch of packet data within PMD driver receive function
+#
+CONFIG_RTE_PMD_PACKET_PREFETCH=y
+
+#
+# Compile librte_ring
+#
+CONFIG_RTE_LIBRTE_RING=y
+CONFIG_RTE_LIBRTE_RING_DEBUG=n
+CONFIG_RTE_RING_SPLIT_PROD_CONS=n
+
+#
+# Compile librte_mempool
+#
+CONFIG_RTE_LIBRTE_MEMPOOL=y
+CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE=512
+CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG=n
+
+#
+# Compile librte_mbuf
+#
+CONFIG_RTE_LIBRTE_MBUF=y
+CONFIG_RTE_LIBRTE_MBUF_DEBUG=n
+CONFIG_RTE_MBUF_SCATTER_GATHER=y
+CONFIG_RTE_MBUF_REFCNT_ATOMIC=y
+CONFIG_RTE_PKTMBUF_HEADROOM=128
+
+#
+# Compile librte_timer
+#
+CONFIG_RTE_LIBRTE_TIMER=y
+CONFIG_RTE_LIBRTE_TIMER_DEBUG=n
+
+#
+# Compile librte_malloc
+#
+CONFIG_RTE_LIBRTE_MALLOC=y
+CONFIG_RTE_LIBRTE_MALLOC_DEBUG=n
+CONFIG_RTE_MALLOC_MEMZONE_SIZE=11M
+
+#
+# Compile librte_cfgfile
+#
+CONFIG_RTE_LIBRTE_CFGFILE=y
+
+#
+# Compile librte_cmdline
+#
+CONFIG_RTE_LIBRTE_CMDLINE=y
+CONFIG_RTE_LIBRTE_CMDLINE_DEBUG=n
+
+#
+# Compile librte_hash
+#
+CONFIG_RTE_LIBRTE_HASH=y
+CONFIG_RTE_LIBRTE_HASH_DEBUG=n
+
+#
+# Compile librte_lpm
+#
+CONFIG_RTE_LIBRTE_LPM=n
+CONFIG_RTE_LIBRTE_LPM_DEBUG=n
+
+#
+# Compile librte_acl
+#
+CONFIG_RTE_LIBRTE_ACL=n
+CONFIG_RTE_LIBRTE_ACL_DEBUG=n
+CONFIG_RTE_LIBRTE_ACL_STANDALONE=n
+
+#
+# Compile librte_power
+#
+CONFIG_RTE_LIBRTE_POWER=y
+CONFIG_RTE_LIBRTE_POWER_DEBUG=n
+CONFIG_RTE_MAX_LCORE_FREQS=64
+
+#
+# Compile librte_net
+#
+CONFIG_RTE_LIBRTE_NET=y
+
+#
+# Compile librte_ip_frag
+#
+CONFIG_RTE_LIBRTE_IP_FRAG=y
+CONFIG_RTE_LIBRTE_IP_FRAG_DEBUG=n
+CONFIG_RTE_LIBRTE_IP_FRAG_MAX_FRAG=4
+CONFIG_RTE_LIBRTE_IP_FRAG_TBL_STAT=n
+
+#
+# Compile librte_meter
+#
+CONFIG_RTE_LIBRTE_METER=y
+
+#
+# Compile librte_sched
+#
+CONFIG_RTE_LIBRTE_SCHED=n
+CONFIG_RTE_SCHED_RED=n
+CONFIG_RTE_SCHED_COLLECT_STATS=n
+CONFIG_RTE_SCHED_SUBPORT_TC_OV=n
+CONFIG_RTE_SCHED_PORT_N_GRINDERS=8
+
+#
+# Compile the distributor library
+#
+CONFIG_RTE_LIBRTE_DISTRIBUTOR=y
+
+#
+# Compile librte_port
+#
+CONFIG_RTE_LIBRTE_PORT=n
+
+#
+# Compile librte_table
+#
+CONFIG_RTE_LIBRTE_TABLE=n
+
+#
+# Compile librte_pipeline
+#
+CONFIG_RTE_LIBRTE_PIPELINE=n
+
+#
+# Compile librte_kni
+#
+CONFIG_RTE_LIBRTE_KNI=y
+CONFIG_RTE_KNI_KO_DEBUG=n
+CONFIG_RTE_KNI_VHOST=n
+CONFIG_RTE_KNI_VHOST_MAX_CACHE_SIZE=1024
+CONFIG_RTE_KNI_VHOST_VNET_HDR_EN=n
+CONFIG_RTE_KNI_VHOST_DEBUG_RX=n
+CONFIG_RTE_KNI_VHOST_DEBUG_TX=n
+
+#
+#Compile Xen domain0 support
+#
+CONFIG_RTE_LIBRTE_XEN_DOM0=n
+
+#
+# Enable warning directives
+#
+CONFIG_RTE_INSECURE_FUNCTION_WARNING=n
+
+#
+# Compile the test application
+#
+CONFIG_RTE_APP_TEST=y
+
+#
+# Compile the PMD test application
+#
+CONFIG_RTE_TEST_PMD=n
+CONFIG_RTE_TEST_PMD_RECORD_CORE_CYCLES=n
+CONFIG_RTE_TEST_PMD_RECORD_BURST_STATS=n
diff --git a/config/defconfig_ppc_64-native-linuxapp-gcc b/config/defconfig_ppc_64-native-linuxapp-gcc
new file mode 100644
index 0000000..7d18455
--- /dev/null
+++ b/config/defconfig_ppc_64-native-linuxapp-gcc
@@ -0,0 +1,40 @@
+#   BSD LICENSE
+#
+#   Copyright (C) IBM Corporation 2014.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of IBM Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "common_linuxapp_powerpc"
+
+CONFIG_RTE_MACHINE="powerpc"
+
+CONFIG_RTE_ARCH="powerpc"
+CONFIG_RTE_ARCH_PPC_64=y
+
+CONFIG_RTE_TOOLCHAIN="gcc"
+CONFIG_RTE_TOOLCHAIN_GCC=y
+
diff --git a/mk/arch/powerpc/rte.vars.mk b/mk/arch/powerpc/rte.vars.mk
new file mode 100644
index 0000000..363fcd1
--- /dev/null
+++ b/mk/arch/powerpc/rte.vars.mk
@@ -0,0 +1,39 @@
+#   BSD LICENSE
+#
+#   Copyright (C) IBM Corporation 2014.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of IBM Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+ARCH  ?= powerpc
+CROSS ?=
+
+CPU_CFLAGS  ?= -m64
+CPU_LDFLAGS ?=
+CPU_ASFLAGS ?= -felf64
+
+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS
diff --git a/mk/machine/powerpc/rte.vars.mk b/mk/machine/powerpc/rte.vars.mk
new file mode 100644
index 0000000..bae5e98
--- /dev/null
+++ b/mk/machine/powerpc/rte.vars.mk
@@ -0,0 +1,57 @@
+#   BSD LICENSE
+#
+#   Copyright (C) IBM Corporation 2014.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of IBM Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#
+# machine:
+#
+#   - can define ARCH variable (overriden by cmdline value)
+#   - can define CROSS variable (overriden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overriden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overriden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overriden by cmdline value)
+#   - can define CPU_CFLAGS variable (overriden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overriden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overriden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+MACHINE_CFLAGS =
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 01/12] Add compiling definations for IBM " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-29  6:16   ` Hemant
  2014-10-16  0:39   ` Ananyev, Konstantin
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 03/12] Add byte order " Chao Zhu
                   ` (10 subsequent siblings)
  12 siblings, 2 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

The atomic operations implemented with assembly code in DPDK only
support x86. This patch add architecture specific atomic operations for
IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 .../common/include/powerpc/arch/rte_atomic.h       |  387 ++++++++++++++++++++
 .../common/include/powerpc/arch/rte_atomic_arch.h  |  318 ++++++++++++++++
 2 files changed, 705 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h

diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h b/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
new file mode 100644
index 0000000..7f5214e
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
@@ -0,0 +1,387 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
+ * Copyright (c) 2008 Marcel Moolenaar
+ * Copyright (c) 2001 Benno Rice
+ * Copyright (c) 2001 David E. O'Brien
+ * Copyright (c) 1998 Doug Rabson
+ * All rights reserved.
+ */
+
+#ifndef _RTE_ATOMIC_H_
+#error "don't include this file directly, please include generic <rte_atomic.h>"
+#endif
+
+#ifndef _RTE_POWERPC_64_ATOMIC_H_
+#define _RTE_POWERPC_64_ATOMIC_H_
+
+/*------------------------- 64 bit atomic operations -------------------------*/
+
+/**
+ * An atomic compare and set function used by the mutex functions.
+ * (atomic) equivalent to:
+ *   if (*dst == exp)
+ *     *dst = src (all 64-bit words)
+ *
+ * @param dst
+ *   The destination into which the value will be written.
+ * @param exp
+ *   The expected value.
+ * @param src
+ *   The new value.
+ * @return
+ *   Non-zero on success; 0 on failure.
+ */
+static inline int
+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
+{
+	unsigned int ret = 0;
+
+	asm volatile (
+			"\tlwsync\n"
+			"1: ldarx %[ret], 0, %[dst]\n"
+			"cmpld %[exp], %[ret]\n"
+			"bne 2f\n"
+			"stdcx. %[src], 0, %[dst]\n"
+			"bne- 1b\n"
+			"li %[ret], 1\n"
+			"b 3f\n"
+			"2:\n"
+			"stdcx. %[ret], 0, %[dst]\n"
+			"li %[ret], 0\n"
+			"3:\n"
+			"isync\n"
+			: [ret] "=&r" (ret), "=m" (*dst)
+			: [dst] "r" (dst), [exp] "r" (exp), [src] "r" (src), "m" (*dst)
+			: "cc", "memory");
+	return ret;
+}
+
+/**
+ * The atomic counter structure.
+ */
+typedef struct {
+	volatile int64_t cnt;  /**< Internal counter value. */
+} rte_atomic64_t;
+
+/**
+ * Static initializer for an atomic counter.
+ */
+#define RTE_ATOMIC64_INIT(val) { (val) }
+
+/**
+ * Initialize the atomic counter.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void
+rte_atomic64_init(rte_atomic64_t *v)
+{
+	v->cnt = 0;
+}
+
+/**
+ * Atomically read a 64-bit counter.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   The value of the counter.
+ */
+static inline int64_t
+rte_atomic64_read(rte_atomic64_t *v)
+{
+	long ret;
+
+	asm volatile("ld%U1%X1 %[ret],%[cnt]" : [ret] "=r"(ret) : [cnt] "m"(v->cnt));
+
+	return ret;
+}
+
+/**
+ * Atomically set a 64-bit counter.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @param new_value
+ *   The new value of the counter.
+ */
+static inline void
+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
+{
+	asm volatile("std%U0%X0 %[new_value],%[cnt]" : [cnt] "=m"(v->cnt) : [new_value] "r"(new_value));
+}
+
+/**
+ * Atomically add a 64-bit value to a counter.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @param inc
+ *   The value to be added to the counter.
+ */
+static inline void
+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
+{
+	long t;
+
+	asm volatile(
+			"1: ldarx %[t],0,%[cnt]\n"
+			"add %[t],%[inc],%[t]\n"
+			"stdcx. %[t],0,%[cnt]\n"
+			"bne- 1b\n"
+			: [t] "=&r" (t), "=m" (v->cnt)
+			: [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
+			: "cc", "memory");
+}
+
+/**
+ * Atomically subtract a 64-bit value from a counter.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @param dec
+ *   The value to be subtracted from the counter.
+ */
+static inline void
+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
+{
+	long t;
+
+	asm volatile(
+			"1: ldarx %[t],0,%[cnt]\n"
+			"subf %[t],%[dec],%[t]\n"
+			"stdcx. %[t],0,%[cnt]\n"
+			"bne- 1b\n"
+			: [t] "=&r" (t), "+m" (v->cnt)
+			: [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
+			: "cc", "memory");
+}
+
+/**
+ * Atomically increment a 64-bit counter by one and test.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void
+rte_atomic64_inc(rte_atomic64_t *v)
+{
+	long t;
+
+	asm volatile(
+			"1: ldarx %[t],0,%[cnt]\n"
+			"addic %[t],%[t],1\n"
+			"stdcx. %[t],0,%[cnt] \n"
+			"bne- 1b\n"
+			: [t] "=&r" (t), "+m" (v->cnt)
+			: [cnt] "r" (&v->cnt), "m" (v->cnt)
+			: "cc", "xer", "memory");
+}
+
+/**
+ * Atomically decrement a 64-bit counter by one and test.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void
+rte_atomic64_dec(rte_atomic64_t *v)
+{
+	long t;
+
+	asm volatile(
+			"1: ldarx %[t],0,%[cnt]\n"
+			"addic %[t],%[t],-1\n"
+			"stdcx. %[t],0,%[cnt]\n"
+			"bne- 1b\n"
+			: [t] "=&r" (t), "+m" (v->cnt)
+			: [cnt] "r" (&v->cnt), "m" (v->cnt)
+			: "cc", "xer", "memory");
+}
+
+/**
+ * Add a 64-bit value to an atomic counter and return the result.
+ *
+ * Atomically adds the 64-bit value (inc) to the atomic counter (v) and
+ * returns the value of v after the addition.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @param inc
+ *   The value to be added to the counter.
+ * @return
+ *   The value of v after the addition.
+ */
+static inline int64_t
+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
+{
+	long ret;
+
+	asm volatile(
+			"\n\tlwsync\n"
+			"1: ldarx %[ret],0,%[cnt]\n"
+			"add %[ret],%[inc],%[ret]\n"
+			"stdcx. %[ret],0,%[cnt]\n"
+			"bne- 1b\n"
+			"isync\n"
+			: [ret] "=&r" (ret)
+			: [inc] "r" (inc), [cnt] "r" (&v->cnt)
+			: "cc", "memory");
+
+	return ret;
+}
+
+/**
+ * Subtract a 64-bit value from an atomic counter and return the result.
+ *
+ * Atomically subtracts the 64-bit value (dec) from the atomic counter (v)
+ * and returns the value of v after the subtraction.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @param dec
+ *   The value to be subtracted from the counter.
+ * @return
+ *   The value of v after the subtraction.
+ */
+static inline int64_t
+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
+{
+	long ret;
+
+	asm volatile(
+			"\n\tlwsync\n"
+			"1: ldarx %[ret],0,%[cnt]\n"
+			"subf %[ret],%[dec],%[ret]\n"
+			"stdcx. %[ret],0,%[cnt] \n"
+			"bne- 1b\n"
+			"isync\n"
+			: [ret] "=&r" (ret)
+			: [dec] "r" (dec), [cnt] "r" (&v->cnt)
+			: "cc", "memory");
+
+	return ret;
+}
+
+static __inline__ long rte_atomic64_inc_return(rte_atomic64_t *v)
+{
+	long ret;
+
+	asm volatile(
+			"\n\tlwsync\n"
+			"1: ldarx %[ret],0,%[cnt]\n"
+			"addic %[ret],%[ret],1\n"
+			"stdcx. %[ret],0,%[cnt]\n"
+			"bne- 1b\n"
+			"isync\n"
+			: [ret] "=&r" (ret)
+			: [cnt] "r" (&v->cnt)
+			: "cc", "xer", "memory");
+
+	return ret;
+}
+/**
+ * Atomically increment a 64-bit counter by one and test.
+ *
+ * Atomically increments the atomic counter (v) by one and returns
+ * true if the result is 0, or false in all other cases.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   True if the result after the addition is 0; false otherwise.
+ */
+#define rte_atomic64_inc_and_test(v) (rte_atomic64_inc_return(v) == 0)
+
+static __inline__ long rte_atomic64_dec_return(rte_atomic64_t *v)
+{
+	long ret;
+
+	asm volatile(
+			"\n\tlwsync\n"
+			"1: ldarx %[ret],0,%[cnt]\n"
+			"addic %[ret],%[ret],-1\n"
+			"stdcx. %[ret],0,%[cnt]\n"
+			"bne- 1b\n"
+			"isync\n"
+			: [ret] "=&r" (ret)
+			: [cnt] "r" (&v->cnt)
+			: "cc", "xer", "memory");
+
+	return ret;
+}
+/**
+ * Atomically decrement a 64-bit counter by one and test.
+ *
+ * Atomically decrements the atomic counter (v) by one and returns true if
+ * the result is 0, or false in all other cases.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   True if the result after subtraction is 0; false otherwise.
+ */
+#define rte_atomic64_dec_and_test(v)    (rte_atomic64_dec_return((v)) == 0)
+
+/**
+ * Atomically test and set a 64-bit atomic counter.
+ *
+ * If the counter value is already set, return 0 (failed). Otherwise, set
+ * the counter value to 1 and return 1 (success).
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   0 if failed; else 1, success.
+ */
+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
+{
+	return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
+}
+
+/**
+ * Atomically set a 64-bit counter to 0.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void rte_atomic64_clear(rte_atomic64_t *v)
+{
+	v->cnt = 0;
+}
+
+#endif /* _RTE_POWERPC_64_ATOMIC_H_ */
+
diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
new file mode 100644
index 0000000..fe5666e
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
@@ -0,0 +1,318 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
+ * Copyright (c) 2008 Marcel Moolenaar
+ * Copyright (c) 2001 Benno Rice
+ * Copyright (c) 2001 David E. O'Brien
+ * Copyright (c) 1998 Doug Rabson
+ * All rights reserved.
+ */
+
+#ifndef _RTE_ATOMIC_H_
+#error "don't include this file directly, please include generic <rte_atomic.h>"
+#endif
+
+#ifndef _RTE_ATOMIC_ARCH_H_
+#define _RTE_ATOMIC_ARCH_H_
+
+#include <stdint.h>
+
+/**
+ * General memory barrier.
+ *
+ * Guarantees that the LOAD and STORE operations generated before the
+ * barrier occur before the LOAD and STORE operations generated after.
+ */
+#define	rte_arch_mb()  asm volatile("sync" : : : "memory")
+
+/**
+ * Write memory barrier.
+ *
+ * Guarantees that the STORE operations generated before the barrier
+ * occur before the STORE operations generated after.
+ */
+#define	rte_arch_wmb() asm volatile("sync" : : : "memory")
+
+/**
+ * Read memory barrier.
+ *
+ * Guarantees that the LOAD operations generated before the barrier
+ * occur before the LOAD operations generated after.
+ */
+#define	rte_arch_rmb() asm volatile("sync" : : : "memory")
+
+#define	rte_arch_compiler_barrier() do {		\
+	asm volatile ("" : : : "memory");	\
+} while(0)
+
+/*------------------------- 16 bit atomic operations -------------------------*/
+
+/**
+ * The atomic counter structure.
+ */
+typedef struct {
+	volatile int16_t cnt; /**< An internal counter value. */
+} rte_atomic16_t;
+
+/**
+ * Atomic compare and set.
+ *
+ * (atomic) equivalent to:
+ *   if (*dst == exp)
+ *     *dst = src (all 16-bit words)
+ *
+ * @param dst
+ *   The destination location into which the value will be written.
+ * @param exp
+ *   The expected value.
+ * @param src
+ *   The new value.
+ * @return
+ *   Non-zero on success; 0 on failure.
+ */
+static inline int
+rte_arch_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
+{
+	return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE) ? 1 : 0;
+}
+
+/**
+ * Atomically increment a counter by one.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void
+rte_arch_atomic16_inc(rte_atomic16_t *v)
+{
+	__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
+}
+
+/**
+ * Atomically decrement a counter by one.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void
+rte_arch_atomic16_dec(rte_atomic16_t *v)
+{
+	__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
+}
+
+/**
+ * Atomically increment a 16-bit counter by one and test.
+ *
+ * Atomically increments the atomic counter (v) by one and returns true if
+ * the result is 0, or false in all other cases.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   True if the result after the increment operation is 0; false otherwise.
+ */
+static inline int rte_arch_atomic16_inc_and_test(rte_atomic16_t *v)
+{
+	return (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);
+}
+
+/**
+ * Atomically decrement a 16-bit counter by one and test.
+ *
+ * Atomically decrements the atomic counter (v) by one and returns true if
+ * the result is 0, or false in all other cases.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   True if the result after the decrement operation is 0; false otherwise.
+ */
+static inline int rte_arch_atomic16_dec_and_test(rte_atomic16_t *v)
+{
+	return (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);
+}
+
+/*------------------------- 32 bit atomic operations -------------------------*/
+
+/**
+ * The atomic counter structure.
+ */
+typedef struct {
+	volatile int32_t cnt; /**< An internal counter value. */
+} rte_atomic32_t;
+
+/**
+ * Atomic compare and set.
+ *
+ * (atomic) equivalent to:
+ *   if (*dst == exp)
+ *     *dst = src (all 32-bit words)
+ *
+ * @param dst
+ *   The destination location into which the value will be written.
+ * @param exp
+ *   The expected value.
+ * @param src
+ *   The new value.
+ * @return
+ *   Non-zero on success; 0 on failure.
+ */
+static inline int
+rte_arch_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
+{
+	unsigned int ret = 0;
+
+	asm volatile(
+			"\tlwsync\n"
+			"1:\tlwarx %[ret], 0, %[dst]\n"
+			"cmplw %[exp], %[ret]\n"
+			"bne 2f\n"
+			"stwcx. %[src], 0, %[dst]\n"
+			"bne- 1b\n"
+			"li %[ret], 1\n"
+			"b 3f\n"
+			"2:\n"
+			"stwcx. %[ret], 0, %[dst]\n"   
+			"li %[ret], 0\n"
+			"3:\n"
+			"isync\n"
+			: [ret] "=&r" (ret), "=m" (*dst)
+			: [dst] "r" (dst), [exp] "r" (exp), [src] "r" (src), "m" (*dst)
+			: "cc", "memory");
+
+	return ret;
+}
+
+/**
+ * Atomically increment a counter by one.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void
+rte_arch_atomic32_inc(rte_atomic32_t *v)
+{
+	int t;
+
+	asm volatile(
+			"1: lwarx %[t],0,%[cnt]\n"
+			"addic %[t],%[t],1\n"
+			"stwcx. %[t],0,%[cnt]\n"
+			"bne- 1b\n"
+			: [t] "=&r" (t), "=m" (v->cnt)
+			: [cnt] "r" (&v->cnt), "m" (v->cnt)
+			: "cc", "xer", "memory");
+}
+
+/**
+ * Atomically decrement a counter by one.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ */
+static inline void
+rte_arch_atomic32_dec(rte_atomic32_t *v)
+{
+	int t;
+
+	asm volatile(
+			"1: lwarx %[t],0,%[cnt]\n"
+			"addic %[t],%[t],-1\n"
+			"stwcx. %[t],0,%[cnt]\n"
+			"bne- 1b\n"
+			: [t] "=&r" (t), "=m" (v->cnt)
+			: [cnt] "r" (&v->cnt), "m" (v->cnt)
+			: "cc", "xer", "memory");
+}
+
+/**
+ * Atomically increment a 32-bit counter by one and test.
+ *
+ * Atomically increments the atomic counter (v) by one and returns true if
+ * the result is 0, or false in all other cases.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   True if the result after the increment operation is 0; false otherwise.
+ */
+static inline int rte_arch_atomic32_inc_and_test(rte_atomic32_t *v)
+{
+	int ret;
+
+	asm volatile(
+			"\n\tlwsync\n"
+			"1: lwarx %[ret],0,%[cnt]\n"
+			"addic	%[ret],%[ret],1\n"
+			"stwcx. %[ret],0,%[cnt]\n"
+			"bne- 1b\n"
+			"isync\n"
+			: [ret] "=&r" (ret)
+			: [cnt] "r" (&v->cnt)
+			: "cc", "xer", "memory");
+
+	return (ret == 0);
+}
+
+/**
+ * Atomically decrement a 32-bit counter by one and test.
+ *
+ * Atomically decrements the atomic counter (v) by one and returns true if
+ * the result is 0, or false in all other cases.
+ *
+ * @param v
+ *   A pointer to the atomic counter.
+ * @return
+ *   True if the result after the decrement operation is 0; false otherwise.
+ */
+static inline int rte_arch_atomic32_dec_and_test(rte_atomic32_t *v)
+{
+	int ret;
+
+	asm volatile(
+			"\n\tlwsync\n"
+			"1: lwarx %[ret],0,%[cnt]\n"
+			"addic %[ret],%[ret],-1\n"
+			"stwcx. %[ret],0,%[cnt]\n"
+			"bne- 1b\n"
+			"isync\n"
+			: [ret] "=&r" (ret)
+			: [cnt] "r" (&v->cnt)
+			: "cc", "xer", "memory");
+
+	return (ret == 0);
+}
+
+#endif /* _RTE_ATOMIC_ARCH_H_ */
+
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 03/12] Add byte order operations for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 01/12] Add compiling definations for IBM " Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 02/12] Add atomic operations " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 04/12] Add CPU cycle " Chao Zhu
                   ` (9 subsequent siblings)
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

The byte order operations implemented with assembly code in DPDK only
support x86. This patch add architecture specific atomic operations for
IBM Power architecture. Since IBM Power architecture is big endian while
x86 is little endian, this patch also add endian specific functions to
support Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 config/defconfig_ppc_64-native-linuxapp-gcc        |    1 +
 .../include/powerpc/arch/rte_byteorder_arch.h      |   79 ++++++++++++++++++++
 lib/librte_eal/common/include/rte_byteorder.h      |   66 ++++++++++++++++
 3 files changed, 146 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_byteorder_arch.h

diff --git a/config/defconfig_ppc_64-native-linuxapp-gcc b/config/defconfig_ppc_64-native-linuxapp-gcc
index 7d18455..cc11cfc 100644
--- a/config/defconfig_ppc_64-native-linuxapp-gcc
+++ b/config/defconfig_ppc_64-native-linuxapp-gcc
@@ -34,6 +34,7 @@ CONFIG_RTE_MACHINE="powerpc"
 
 CONFIG_RTE_ARCH="powerpc"
 CONFIG_RTE_ARCH_PPC_64=y
+CONFIG_RTE_ARCH_BIG_ENDIAN=y
 
 CONFIG_RTE_TOOLCHAIN="gcc"
 CONFIG_RTE_TOOLCHAIN_GCC=y
diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_byteorder_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_byteorder_arch.h
new file mode 100644
index 0000000..ec4d32e
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_byteorder_arch.h
@@ -0,0 +1,79 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Inspired from FreeBSD src/sys/powerpc/include/endian.h
+ * Copyright (c) 1987, 1991, 1993
+ * The Regents of the University of California.  All rights reserved.
+*/
+
+#ifndef _RTE_BYTEORDER_ARCH_H_
+#define _RTE_BYTEORDER_ARCH_H_
+
+#include <stdint.h>
+
+/*
+ * An architecture-optimized byte swap for a 16-bit value.
+ *
+ * Do not use this function directly. The preferred function is rte_bswap16().
+ */
+static inline uint16_t rte_arch_bswap16(uint16_t _x)
+{
+	return ((_x >> 8) | ((_x << 8) & 0xff00));
+}
+
+/*
+ * An architecture-optimized byte swap for a 32-bit value.
+ *
+ * Do not use this function directly. The preferred function is rte_bswap32().
+ */
+static inline uint32_t rte_arch_bswap32(uint32_t _x)
+{
+	return ((_x >> 24) | ((_x >> 8) & 0xff00) | ((_x << 8) & 0xff0000) |
+		((_x << 24) & 0xff000000));
+}
+
+/*
+ * An architecture-optimized byte swap for a 64-bit value.
+ *
+  * Do not use this function directly. The preferred function is rte_bswap64().
+ */
+/* 64-bit mode */
+static inline uint64_t rte_arch_bswap64(uint64_t _x)
+{
+	return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
+		((_x >> 8) & 0xff000000) | ((_x << 8) & (0xffULL << 32)) |
+		((_x << 24) & (0xffULL << 40)) |
+		((_x << 40) & (0xffULL << 48)) | ((_x << 56)));
+}
+
+#endif /* _RTE_BYTEORDER_ARCH_H_ */
+
diff --git a/lib/librte_eal/common/include/rte_byteorder.h b/lib/librte_eal/common/include/rte_byteorder.h
index 98e3764..e8366ea 100644
--- a/lib/librte_eal/common/include/rte_byteorder.h
+++ b/lib/librte_eal/common/include/rte_byteorder.h
@@ -146,6 +146,7 @@ rte_constant_bswap64(uint64_t x)
 
 #endif
 
+#ifndef RTE_ARCH_BIG_ENDIAN
 /**
  * Convert a 16-bit value from CPU order to little endian.
  */
@@ -209,6 +210,71 @@ rte_constant_bswap64(uint64_t x)
  */
 #define rte_be_to_cpu_64(x) rte_bswap64(x)
 
+#else
+/**
+ * Convert a 16-bit value from CPU order to little endian.
+ */
+#define rte_cpu_to_le_16(x) rte_bswap16(x)
+
+/**
+ * Convert a 32-bit value from CPU order to little endian.
+ */
+#define rte_cpu_to_le_32(x) rte_bswap32(x)
+
+/**
+ * Convert a 64-bit value from CPU order to little endian.
+ */
+#define rte_cpu_to_le_64(x) rte_bswap64(x)
+
+
+/**
+ * Convert a 16-bit value from CPU order to big endian.
+ */
+#define rte_cpu_to_be_16(x) (x)
+
+/**
+ * Convert a 32-bit value from CPU order to big endian.
+ */
+#define rte_cpu_to_be_32(x) (x)
+
+/**
+ * Convert a 64-bit value from CPU order to big endian.
+ */
+#define rte_cpu_to_be_64(x) (x)
+
+
+/**
+ * Convert a 16-bit value from little endian to CPU order.
+ */
+#define rte_le_to_cpu_16(x) rte_bswap16(x)
+
+/**
+ * Convert a 32-bit value from little endian to CPU order.
+ */
+#define rte_le_to_cpu_32(x) rte_bswap32(x)
+
+/**
+ * Convert a 64-bit value from little endian to CPU order.
+ */
+#define rte_le_to_cpu_64(x) rte_bswap64(x)
+
+
+/**
+ * Convert a 16-bit value from big endian to CPU order.
+ */
+#define rte_be_to_cpu_16(x) (x)
+
+/**
+ * Convert a 32-bit value from big endian to CPU order.
+ */
+#define rte_be_to_cpu_32(x) (x)
+
+/**
+ * Convert a 64-bit value from big endian to CPU order.
+ */
+#define rte_be_to_cpu_64(x) (x)
+#endif
+
 #ifdef __cplusplus
 }
 #endif
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 04/12] Add CPU cycle operations for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (2 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 03/12] Add byte order " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 05/12] Add prefetch operation " Chao Zhu
                   ` (8 subsequent siblings)
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

IBM Power architecture doesn't have TSC register to get CPU cycles. This
patch implements the time base register read instead of TSC register of
x86 on IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 .../common/include/powerpc/arch/rte_cycles_arch.h  |   67 ++++++++++++++++++++
 1 files changed, 67 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h

diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h
new file mode 100644
index 0000000..faae7a6
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h
@@ -0,0 +1,67 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_CYCLES_ARCH_H_
+#define _RTE_CYCLES_ARCH_H_
+
+#include <stdint.h>
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static inline uint64_t
+rte_arch_rdtsc(void)
+{
+	union {
+		uint64_t tsc_64;
+		struct {
+			uint32_t hi_32;
+			uint32_t lo_32;
+		};
+	} tsc;
+	uint32_t tmp;
+	asm volatile(
+			"0:\n"
+			"mftbu   %[hi32]\n"
+			"mftb    %[lo32]\n"
+			"mftbu   %[tmp]\n"
+			"cmpw    %[tmp],%[hi32]\n"
+			"bne     0b\n"
+			: [hi32] "=r"(tsc.hi_32), [lo32] "=r"(tsc.lo_32), [tmp] "=r"(tmp)
+		    );
+	return tsc.tsc_64;
+}
+#endif /* _RTE_CYCLES_ARCH_H_ */
+
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 05/12] Add prefetch operation for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (3 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 04/12] Add CPU cycle " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 06/12] Add spinlock " Chao Zhu
                   ` (7 subsequent siblings)
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

The prefetch operations implemented with assembly code in DPDK only
support x86. This patch add architecture specific prefetch operations
for IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 .../include/powerpc/arch/rte_prefetch_arch.h       |   67 ++++++++++++++++++++
 1 files changed, 67 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h

diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h
new file mode 100644
index 0000000..32f18b4
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h
@@ -0,0 +1,67 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_PREFETCH_ARCH_H_
+#define _RTE_PREFETCH_ARCH_H_
+
+/**
+ * Prefetch a cache line into all cache levels.
+ * @param p
+ *   Address to prefetch
+ */
+static inline void rte_arch_prefetch0(volatile void *p)
+{
+	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+}
+
+/**
+ * Prefetch a cache line into all cache levels except the 0th cache level.
+ * @param p
+ *   Address to prefetch
+ */
+static inline void rte_arch_prefetch1(volatile void *p)
+{
+	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+}
+
+/**
+ * Prefetch a cache line into all cache levels except the 0th and 1th cache
+ * levels.
+ * @param p
+ *   Address to prefetch
+ */
+static inline void rte_arch_prefetch2(volatile void *p)
+{
+	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+}
+
+#endif /* _RTE_PREFETCH_ARCH_H_ */
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 06/12] Add spinlock operation for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (4 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 05/12] Add prefetch operation " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 07/12] Add vector memcpy " Chao Zhu
                   ` (6 subsequent siblings)
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

The spinlock operations implemented with assembly code in DPDK only
support x86. This patch add spinlock operations for IBM Power
architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 .../include/powerpc/arch/rte_spinlock_arch.h       |   88 ++++++++++++++++++++
 1 files changed, 88 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_spinlock_arch.h

diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_spinlock_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_spinlock_arch.h
new file mode 100644
index 0000000..3e4c0ea
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_spinlock_arch.h
@@ -0,0 +1,88 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_SPINLOCK_ARCH_H_
+#define _RTE_SPINLOCK_ARCH_H_
+
+#include <rte_lcore.h>
+#include <rte_common.h>
+
+/* Fixme: Use intrinsics to implement the spinlock on Power architecture */
+
+/**
+ * The rte_spinlock_t type.
+ */
+typedef struct {
+	volatile int locked; /**< lock status 0 = unlocked, 1 = locked */
+} rte_spinlock_t;
+
+/**
+ * Take the spinlock.
+ *
+ * @param sl
+ *   A pointer to the spinlock.
+ */
+static inline void
+rte_arch_spinlock_lock(rte_spinlock_t *sl)
+{
+	while (__sync_lock_test_and_set(&sl->locked, 1))
+		while(sl->locked)
+			rte_pause();
+}
+
+/**
+ * Release the spinlock.
+ *
+ * @param sl
+ *   A pointer to the spinlock.
+ */
+static inline void
+rte_arch_spinlock_unlock (rte_spinlock_t *sl)
+{
+	__sync_lock_release(&sl->locked);
+}
+
+/**
+ * Try to take the lock.
+ *
+ * @param sl
+ *   A pointer to the spinlock.
+ * @return
+ *   1 if the lock is successfully taken; 0 otherwise.
+ */
+static inline int
+rte_arch_spinlock_trylock (rte_spinlock_t *sl)
+{
+	return (__sync_lock_test_and_set(&sl->locked,1) == 0);
+}
+
+#endif /* _RTE_SPINLOCK_ARCH_H_ */
\ No newline at end of file
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 07/12] Add vector memcpy for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (5 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 06/12] Add spinlock " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 08/12] Add CPU flag checking " Chao Zhu
                   ` (5 subsequent siblings)
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

The SSE based memory copy in DPDK only support x86. This patch adds
altivec based memory copy functions for IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 .../common/include/powerpc/arch/rte_memcpy_arch.h  |  129 ++++++++++++++++++++
 1 files changed, 129 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_memcpy_arch.h

diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_memcpy_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_memcpy_arch.h
new file mode 100644
index 0000000..41aa483
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_memcpy_arch.h
@@ -0,0 +1,129 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_MEMCPY_ARCH_H_
+#define _RTE_MEMCPY_ARCH_H_
+
+#include <stdint.h>
+#include <string.h>
+#include <altivec.h>
+
+/**
+ * Copy 16 bytes from one location to another using optimised Altivec
+ * functions. The locations should not overlap.
+ *
+ * @param dst
+ *   Pointer to the destination of the data.
+ * @param src
+ *   Pointer to the source data.
+ */
+static inline void
+rte_arch_mov16(uint8_t *dst, const uint8_t *src)
+{
+	vec_vsx_st(vec_vsx_ld(0, src), 0, dst);
+}
+
+/**
+ * Copy 32 bytes from one location to another using optimised Altivec
+ * functions. The locations should not overlap.
+ *
+ * @param dst
+ *   Pointer to the destination of the data.
+ * @param src
+ *   Pointer to the source data.
+ */
+static inline void
+rte_arch_mov32(uint8_t *dst, const uint8_t *src)
+{
+	vec_vsx_st(vec_vsx_ld(0, src), 0, dst);
+	vec_vsx_st(vec_vsx_ld(16, src), 16, dst);
+}
+
+/**
+ * Copy 48 bytes from one location to another using optimised Altivec
+ * functions. The locations should not overlap.
+ *
+ * @param dst
+ *   Pointer to the destination of the data.
+ * @param src
+ *   Pointer to the source data.
+ */
+static inline void
+rte_arch_mov48(uint8_t *dst, const uint8_t *src)
+{
+	vec_vsx_st(vec_vsx_ld(0, src), 0, dst);
+	vec_vsx_st(vec_vsx_ld(16, src), 16, dst);
+	vec_vsx_st(vec_vsx_ld(32, src), 32, dst);
+}
+
+/**
+ * Copy 64 bytes from one location to another using optimised Altivec
+ * functions. The locations should not overlap.
+ *
+ * @param dst
+ *   Pointer to the destination of the data.
+ * @param src
+ *   Pointer to the source data.
+ */
+static inline void
+rte_arch_mov64(uint8_t *dst, const uint8_t *src)
+{
+	vec_vsx_st(vec_vsx_ld(0, src), 0, dst);
+	vec_vsx_st(vec_vsx_ld(16, src), 16, dst);
+	vec_vsx_st(vec_vsx_ld(32, src), 32, dst);
+	vec_vsx_st(vec_vsx_ld(48, src), 48, dst);
+}
+
+/**
+ * Copy 128 bytes from one location to another using optimised Altivec
+ * functions. The locations should not overlap.
+ *
+ * @param dst
+ *   Pointer to the destination of the data.
+ * @param src
+ *   Pointer to the source data.
+ */
+static inline void
+rte_arch_mov128(uint8_t *dst, const uint8_t *src)
+{
+	vec_vsx_st(vec_vsx_ld(0, src), 0, dst);
+	vec_vsx_st(vec_vsx_ld(16, src), 16, dst);
+	vec_vsx_st(vec_vsx_ld(32, src), 32, dst);
+	vec_vsx_st(vec_vsx_ld(48, src), 48, dst);
+	vec_vsx_st(vec_vsx_ld(64, src), 64, dst);
+	vec_vsx_st(vec_vsx_ld(80, src), 80, dst);
+	vec_vsx_st(vec_vsx_ld(96, src), 96, dst);
+	vec_vsx_st(vec_vsx_ld(112, src), 112, dst);
+}
+
+#endif /* _RTE_MEMCPY_ARCH_H_ */
+
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 08/12] Add CPU flag checking for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (6 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 07/12] Add vector memcpy " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 09/12] Remove iopl operation " Chao Zhu
                   ` (4 subsequent siblings)
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

Intel processors contain registers to identify CPU flags, DPDK reads the
registers to get the CPU flags. IBM Power processor doesn't have such
registers. This patch uses aux vector software register to get CPU flags
and add CPU flag checking support for IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 app/test/test_cpuflags.c                           |   35 ++++
 .../include/powerpc/arch/rte_cpuflags_arch.h       |  199 ++++++++++++++++++++
 mk/rte.cpuflags.mk                                 |   17 ++
 3 files changed, 251 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_cpuflags_arch.h

diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 82c0197..5aeba5d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -80,6 +80,40 @@ test_cpuflags(void)
 	int result;
 	printf("\nChecking for flags from different registers...\n");
 
+#ifdef RTE_ARCH_PPC_64
+	printf("Check for PPC64:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_PPC64);
+
+	printf("Check for PPC32:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_PPC32);
+
+	printf("Check for VSX:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_VSX);
+
+	printf("Check for DFP:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_DFP);
+
+	printf("Check for FPU:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_FPU);
+
+	printf("Check for SMT:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_SMT);
+
+	printf("Check for MMU:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_MMU);
+
+	printf("Check for ALTIVEC:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_ALTIVEC);
+
+	printf("Check for ARCH_2_06:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_06);
+
+	printf("Check for ARCH_2_07:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_07);
+
+	printf("Check for ICACHE_SNOOP:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_ICACHE_SNOOP);
+#else
 	printf("Check for SSE:\t\t");
 	CHECK_FOR_FLAG(RTE_CPUFLAG_SSE);
 
@@ -117,6 +151,7 @@ test_cpuflags(void)
 	CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
 
 
+#endif
 
 	/*
 	 * Check if invalid data is handled properly
diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_cpuflags_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_cpuflags_arch.h
new file mode 100644
index 0000000..4d0ba6b
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_cpuflags_arch.h
@@ -0,0 +1,199 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_CPUFLAGS_ARCH_H_
+#define _RTE_CPUFLAGS_ARCH_H_
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <errno.h>
+#include <stdint.h>
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+
+/* Symbolic values for the entries in the auxiliary table */
+#define AT_HWCAP  16
+#define AT_HWCAP2 26
+
+/* software based registers */
+enum cpu_register_t {
+	REG_HWCAP = 0,
+	REG_HWCAP2,
+};
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+	RTE_CPUFLAG_PPC_LE = 0,
+	RTE_CPUFLAG_TRUE_LE,
+	RTE_CPUFLAG_PSERIES_PERFMON_COMPAT,
+	RTE_CPUFLAG_VSX,
+	RTE_CPUFLAG_ARCH_2_06,
+	RTE_CPUFLAG_POWER6_EXT,
+	RTE_CPUFLAG_DFP,
+	RTE_CPUFLAG_PA6T,
+	RTE_CPUFLAG_ARCH_2_05,
+	RTE_CPUFLAG_ICACHE_SNOOP,
+	RTE_CPUFLAG_SMT,
+	RTE_CPUFLAG_BOOKE,
+	RTE_CPUFLAG_CELLBE,
+	RTE_CPUFLAG_POWER5_PLUS,
+	RTE_CPUFLAG_POWER5,
+	RTE_CPUFLAG_POWER4,
+	RTE_CPUFLAG_NOTB,
+	RTE_CPUFLAG_EFP_DOUBLE,
+	RTE_CPUFLAG_EFP_SINGLE,
+	RTE_CPUFLAG_SPE,
+	RTE_CPUFLAG_UNIFIED_CACHE,
+	RTE_CPUFLAG_4xxMAC,
+	RTE_CPUFLAG_MMU,
+	RTE_CPUFLAG_FPU,
+	RTE_CPUFLAG_ALTIVEC,
+	RTE_CPUFLAG_PPC601,
+	RTE_CPUFLAG_PPC64,
+	RTE_CPUFLAG_PPC32,
+	RTE_CPUFLAG_TAR,
+	RTE_CPUFLAG_LSEL,
+	RTE_CPUFLAG_EBB,
+	RTE_CPUFLAG_DSCR,
+	RTE_CPUFLAG_HTM,
+	RTE_CPUFLAG_ARCH_2_07,
+	/* The last item */
+	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
+};
+
+typedef uint32_t cpuid_registers_t[4];
+
+#define CPU_FLAG_NAME_MAX_LEN 64
+
+/**
+ * Struct to hold a processor feature entry
+ */
+struct feature_entry {
+	uint32_t leaf;				/**< cpuid leaf */
+	uint32_t subleaf;			/**< cpuid subleaf */
+	uint32_t reg;				/**< cpuid register */
+	uint32_t bit;				/**< cpuid register bit */
+	char name[CPU_FLAG_NAME_MAX_LEN];       /**< String for printing */
+};
+
+#define FEAT_DEF(name, leaf, subleaf, reg, bit) \
+	[RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
+
+/**
+ * An array that holds feature entries
+ */
+static const struct feature_entry cpu_feature_table[] = {
+	FEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP,  0)
+	FEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP,  1)
+	FEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP,  6)
+	FEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP,  7)
+	FEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP,  8)
+	FEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP,  9)
+	FEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP,  10)
+	FEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP,  11)
+	FEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP,  12)
+	FEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP,  13)
+	FEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP,  14)
+	FEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP,  15)
+	FEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP,  16)
+	FEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP,  17)
+	FEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP,  18)
+	FEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP,  19)
+	FEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP,  20)
+	FEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP,  21)
+	FEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP,  22)
+	FEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP,  23)
+	FEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP,  24)
+	FEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP,  25)
+	FEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP,  26)
+	FEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP,  27)
+	FEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP,  28)
+	FEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP,  29)
+	FEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP,  30)
+	FEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP,  31)
+	FEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2,  26)
+	FEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2,  27)
+	FEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2,  28)
+	FEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2,  29)
+	FEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2,  30)
+	FEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2,  31)
+};
+
+/*
+ * Read AUXV software register and get cpu features for Power
+ */
+static inline void
+rte_arch_cpu_get_features( __attribute__((unused)) uint32_t leaf, __attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
+{
+        int auxv_fd;
+        Elf64_auxv_t auxv;
+        auxv_fd = open("/proc/self/auxv", O_RDONLY);
+        assert(auxv_fd);
+        while (read(auxv_fd, &auxv, sizeof(Elf64_auxv_t))== sizeof(Elf64_auxv_t)) {
+                if (auxv.a_type == AT_HWCAP)
+                        out[REG_HWCAP] = auxv.a_un.a_val;
+                else if (auxv.a_type == AT_HWCAP2)
+                        out[REG_HWCAP2] = auxv.a_un.a_val;
+        }
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+static inline int
+rte_arch_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+	const struct feature_entry *feat;
+	cpuid_registers_t regs;
+
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		/* Flag does not match anything in the feature tables */
+		return -ENOENT;
+
+	feat = &cpu_feature_table[feature];
+
+	if (!feat->leaf)
+		/* This entry in the table wasn't filled out! */
+		return -EFAULT;
+
+	/* get the cpuid leaf containing the desired feature */
+	rte_arch_cpu_get_features(feat->leaf, feat->subleaf, regs);
+
+	/* check if the feature is enabled */
+	return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+#endif /* _RTE_CPUFLAGS_ARCH_H_ */
diff --git a/mk/rte.cpuflags.mk b/mk/rte.cpuflags.mk
index 65332e1..f595cd0 100644
--- a/mk/rte.cpuflags.mk
+++ b/mk/rte.cpuflags.mk
@@ -89,6 +89,23 @@ ifneq ($(filter $(AUTO_CPUFLAGS),__AVX2__),)
 CPUFLAGS += AVX2
 endif
 
+# IBM Power CPU flags
+ifneq ($(filter $(AUTO_CPUFLAGS),__PPC64__),)
+CPUFLAGS += PPC64
+endif
+
+ifneq ($(filter $(AUTO_CPUFLAGS),__PPC32__),)
+CPUFLAGS += PPC32
+endif
+
+ifneq ($(filter $(AUTO_CPUFLAGS),__vector),)
+CPUFLAGS += ALTIVEC
+endif
+
+ifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),)
+CPUFLAGS += VSX
+endif
+
 MACHINE_CFLAGS += $(addprefix -DRTE_MACHINE_CPUFLAG_,$(CPUFLAGS))
 
 # To strip whitespace
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 09/12] Remove iopl operation for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (7 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 08/12] Add CPU flag checking " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-10-06 22:03   ` Cyril Chemparathy
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture Chao Zhu
                   ` (3 subsequent siblings)
  12 siblings, 1 reply; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

iopl() call is mostly for the i386 architecture. In Power architecture.
It doesn't exist. This patch modified rte_eal_iopl_init() and make it
return -1 on Power. This means rte_config.flags will not contain
EAL_FLG_HIGH_IOPL flag on IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 lib/librte_eal/linuxapp/eal/eal.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/lib/librte_eal/linuxapp/eal/eal.c b/lib/librte_eal/linuxapp/eal/eal.c
index 4869e7c..8cc1f21 100644
--- a/lib/librte_eal/linuxapp/eal/eal.c
+++ b/lib/librte_eal/linuxapp/eal/eal.c
@@ -50,7 +50,10 @@
 #include <errno.h>
 #include <sys/mman.h>
 #include <sys/queue.h>
+/* Power architecture doesn't have this header file */
+#ifndef RTE_ARCH_PPC_64
 #include <sys/io.h>
+#endif
 
 #include <rte_common.h>
 #include <rte_debug.h>
@@ -1019,11 +1022,19 @@ rte_eal_mcfg_complete(void)
 
 /*
  * Request iopl privilege for all RPL, returns 0 on success
+ *
+ * Power architecture doesn't have iopl function, so this function
+ * return -1 on Power architecture, because this function is only used
+ * in rte_eal_init to add EAL_FLG_HIGH_IOPL to rte_config.flags.
  */
 static int
 rte_eal_iopl_init(void)
 {
+#ifndef RTE_ARCH_PPC_64
 	return iopl(HIGHEST_RPL);
+#else
+	return -1;
+#endif
 }
 
 /* Launch threads, called at application init(). */
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (8 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 09/12] Remove iopl operation " Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-29  6:21   ` Hemant
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 11/12] Add huge page sizes for IBM Power architecture Chao Zhu
                   ` (2 subsequent siblings)
  12 siblings, 1 reply; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

IBM Power architecture has different cache line size (128 bytes) than
x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to
override the default value 64 bytes to support IBM Power Architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 app/test/test_malloc.c      |    8 ++++----
 app/test/test_mbuf.c        |    2 +-
 mk/arch/powerpc/rte.vars.mk |    2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/app/test/test_malloc.c b/app/test/test_malloc.c
index ee34ca3..63e6b32 100644
--- a/app/test/test_malloc.c
+++ b/app/test/test_malloc.c
@@ -300,9 +300,9 @@ test_big_alloc(void)
 	size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2;
 	int align = 0;
 #ifndef RTE_LIBRTE_MALLOC_DEBUG
-	int overhead = 64 + 64;
+	int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE;
 #else
-	int overhead = 64 + 64 + 64;
+	int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE + CACHE_LINE_SIZE;
 #endif
 
 	rte_malloc_get_socket_stats(socket, &pre_stats);
@@ -356,9 +356,9 @@ test_multi_alloc_statistics(void)
 #ifndef RTE_LIBRTE_MALLOC_DEBUG
 	int trailer_size = 0;
 #else
-	int trailer_size = 64;
+	int trailer_size = CACHE_LINE_SIZE;
 #endif
-	int overhead = 64 + trailer_size;
+	int overhead = CACHE_LINE_SIZE + trailer_size;
 
 	rte_malloc_get_socket_stats(socket, &pre_stats);
 
diff --git a/app/test/test_mbuf.c b/app/test/test_mbuf.c
index 21024e7..03da329 100644
--- a/app/test/test_mbuf.c
+++ b/app/test/test_mbuf.c
@@ -832,7 +832,7 @@ test_failing_mbuf_sanity_check(void)
 static int
 test_mbuf(void)
 {
-	RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) != 64);
+	RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) != CACHE_LINE_SIZE);
 
 	/* create pktmbuf pool if it does not exist */
 	if (pktmbuf_pool == NULL) {
diff --git a/mk/arch/powerpc/rte.vars.mk b/mk/arch/powerpc/rte.vars.mk
index 363fcd1..dfdeaea 100644
--- a/mk/arch/powerpc/rte.vars.mk
+++ b/mk/arch/powerpc/rte.vars.mk
@@ -32,7 +32,7 @@
 ARCH  ?= powerpc
 CROSS ?=
 
-CPU_CFLAGS  ?= -m64
+CPU_CFLAGS  ?= -m64 -DCACHE_LINE_SIZE=128
 CPU_LDFLAGS ?=
 CPU_ASFLAGS ?= -felf64
 
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 11/12] Add huge page sizes for IBM Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (9 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 12/12] Add memory support for IBM Power Architecture Chao Zhu
  2014-11-13 10:24 ` [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Thomas Monjalon
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

IBM Power architecture has different huge page sizes (16MB, 16GB) than
x86.This patch inserts RTE_PGSIZE_16M and RTE_PGSIZE_16G to the
rte_page_sizes enum variable and adds huge page size support of DPDK for
IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 app/test/test_memzone.c                     |  119 ++++++++++++++++++++++++++-
 lib/librte_eal/common/eal_common_memzone.c  |   15 +++-
 lib/librte_eal/common/include/rte_memory.h  |    9 ++-
 lib/librte_eal/common/include/rte_memzone.h |    8 ++
 lib/librte_eal/linuxapp/eal/eal.c           |    5 +-
 5 files changed, 147 insertions(+), 9 deletions(-)

diff --git a/app/test/test_memzone.c b/app/test/test_memzone.c
index 381f643..8668103 100644
--- a/app/test/test_memzone.c
+++ b/app/test/test_memzone.c
@@ -133,6 +133,8 @@ test_memzone_reserve_flags(void)
 	const struct rte_memseg *ms;
 	int hugepage_2MB_avail = 0;
 	int hugepage_1GB_avail = 0;
+	int hugepage_16MB_avail = 0;
+	int hugepage_16GB_avail = 0;
 	const size_t size = 100;
 	int i = 0;
 	ms = rte_eal_get_physmem_layout();
@@ -141,12 +143,20 @@ test_memzone_reserve_flags(void)
 			hugepage_2MB_avail = 1;
 		if (ms[i].hugepage_sz == RTE_PGSIZE_1G)
 			hugepage_1GB_avail = 1;
+		if (ms[i].hugepage_sz == RTE_PGSIZE_16M)
+			hugepage_16MB_avail = 1;
+		if (ms[i].hugepage_sz == RTE_PGSIZE_16G)
+			hugepage_16GB_avail = 1;
 	}
-	/* Display the availability of 2MB and 1GB pages */
+	/* Display the availability of 2MB ,1GB, 16MB, 16GB pages */
 	if (hugepage_2MB_avail)
 		printf("2MB Huge pages available\n");
 	if (hugepage_1GB_avail)
 		printf("1GB Huge pages available\n");
+	if (hugepage_16MB_avail)
+		printf("16MB Huge pages available\n");
+	if (hugepage_16GB_avail)
+		printf("16GB Huge pages available\n");
 	/*
 	 * If 2MB pages available, check that a small memzone is correctly
 	 * reserved from 2MB huge pages when requested by the RTE_MEMZONE_2MB flag.
@@ -255,6 +265,113 @@ test_memzone_reserve_flags(void)
 			}
 		}
 	}
+	/*
+	 * This option is for IBM Power. If 16MB pages available, check that a small memzone is correctly
+	 * reserved from 16MB huge pages when requested by the RTE_MEMZONE_16MB flag.
+	 * Also check that RTE_MEMZONE_SIZE_HINT_ONLY flag only defaults to an
+	 * available page size (i.e 16GB ) when 16MB pages are unavailable.
+	 */
+	if (hugepage_16MB_avail){
+		mz = rte_memzone_reserve("flag_zone_16M", size, SOCKET_ID_ANY,
+				RTE_MEMZONE_16MB);
+		if (mz == NULL) {
+			printf("MEMZONE FLAG 16MB\n");
+			return -1;
+		}
+		if (mz->hugepage_sz != RTE_PGSIZE_16M) {
+			printf("hugepage_sz not equal 16M\n");
+			return -1;
+		}
+
+		mz = rte_memzone_reserve("flag_zone_16M_HINT", size, SOCKET_ID_ANY,
+				RTE_MEMZONE_16MB|RTE_MEMZONE_SIZE_HINT_ONLY);
+		if (mz == NULL) {
+			printf("MEMZONE FLAG 2MB\n");
+			return -1;
+		}
+		if (mz->hugepage_sz != RTE_PGSIZE_16M) {
+			printf("hugepage_sz not equal 16M\n");
+			return -1;
+		}
+
+		/* Check if 1GB huge pages are unavailable, that function fails unless
+		 * HINT flag is indicated
+		 */
+		if (!hugepage_16GB_avail) {
+			mz = rte_memzone_reserve("flag_zone_16G_HINT", size, SOCKET_ID_ANY,
+					RTE_MEMZONE_16GB|RTE_MEMZONE_SIZE_HINT_ONLY);
+			if (mz == NULL) {
+				printf("MEMZONE FLAG 16GB & HINT\n");
+				return -1;
+			}
+			if (mz->hugepage_sz != RTE_PGSIZE_16M) {
+				printf("hugepage_sz not equal 16M\n");
+				return -1;
+			}
+
+			mz = rte_memzone_reserve("flag_zone_16G", size, SOCKET_ID_ANY,
+					RTE_MEMZONE_16GB);
+			if (mz != NULL) {
+				printf("MEMZONE FLAG 16GB\n");
+				return -1;
+			}
+		}
+	}
+	/*As with 16MB tests above for 16GB huge page requests*/
+	if (hugepage_16GB_avail){
+		mz = rte_memzone_reserve("flag_zone_16G", size, SOCKET_ID_ANY,
+				RTE_MEMZONE_16GB);
+		if (mz == NULL) {
+			printf("MEMZONE FLAG 16GB\n");
+			return -1;
+		}
+		if (mz->hugepage_sz != RTE_PGSIZE_16G) {
+			printf("hugepage_sz not equal 16G\n");
+			return -1;
+		}
+
+		mz = rte_memzone_reserve("flag_zone_16G_HINT", size, SOCKET_ID_ANY,
+				RTE_MEMZONE_16GB|RTE_MEMZONE_SIZE_HINT_ONLY);
+		if (mz == NULL) {
+			printf("MEMZONE FLAG 16GB\n");
+			return -1;
+		}
+		if (mz->hugepage_sz != RTE_PGSIZE_16G) {
+			printf("hugepage_sz not equal 16G\n");
+			return -1;
+		}
+
+		/* Check if 1GB huge pages are unavailable, that function fails unless
+		 * HINT flag is indicated
+		 */
+		if (!hugepage_16MB_avail) {
+			mz = rte_memzone_reserve("flag_zone_16M_HINT", size, SOCKET_ID_ANY,
+					RTE_MEMZONE_16MB|RTE_MEMZONE_SIZE_HINT_ONLY);
+			if (mz == NULL){
+				printf("MEMZONE FLAG 16MB & HINT\n");
+				return -1;
+			}
+			if (mz->hugepage_sz != RTE_PGSIZE_16G) {
+				printf("hugepage_sz not equal 16G\n");
+				return -1;
+			}
+			mz = rte_memzone_reserve("flag_zone_16M", size, SOCKET_ID_ANY,
+					RTE_MEMZONE_16MB);
+			if (mz != NULL) {
+				printf("MEMZONE FLAG 16MB\n");
+				return -1;
+			}
+		}
+
+		if (hugepage_16MB_avail && hugepage_16GB_avail) {
+			mz = rte_memzone_reserve("flag_zone_16M_HINT", size, SOCKET_ID_ANY,
+								RTE_MEMZONE_16MB|RTE_MEMZONE_16GB);
+			if (mz != NULL) {
+				printf("BOTH SIZES SET\n");
+				return -1;
+			}
+		}
+	}
 	return 0;
 }
 
diff --git a/lib/librte_eal/common/eal_common_memzone.c b/lib/librte_eal/common/eal_common_memzone.c
index 5acd9ce..e552c7a 100644
--- a/lib/librte_eal/common/eal_common_memzone.c
+++ b/lib/librte_eal/common/eal_common_memzone.c
@@ -221,6 +221,12 @@ memzone_reserve_aligned_thread_unsafe(const char *name, size_t len,
 		if ((flags & RTE_MEMZONE_1GB) &&
 				free_memseg[i].hugepage_sz == RTE_PGSIZE_2M )
 			continue;
+		if ((flags & RTE_MEMZONE_16MB) &&
+				free_memseg[i].hugepage_sz == RTE_PGSIZE_16G )
+			continue;
+		if ((flags & RTE_MEMZONE_16GB) &&
+				free_memseg[i].hugepage_sz == RTE_PGSIZE_16M )
+			continue;
 
 		/* this segment is the best until now */
 		if (memseg_idx == -1) {
@@ -256,7 +262,8 @@ memzone_reserve_aligned_thread_unsafe(const char *name, size_t len,
 		 * try allocating again without the size parameter otherwise -fail.
 		 */
 		if ((flags & RTE_MEMZONE_SIZE_HINT_ONLY)  &&
-		    ((flags & RTE_MEMZONE_1GB) || (flags & RTE_MEMZONE_2MB)))
+		    ((flags & RTE_MEMZONE_1GB) || (flags & RTE_MEMZONE_2MB) 
+		     || (flags & RTE_MEMZONE_16MB) || (flags & RTE_MEMZONE_16GB)))
 			return memzone_reserve_aligned_thread_unsafe(name,
 				len, socket_id, 0, align, bound);
 
@@ -313,7 +320,8 @@ rte_memzone_reserve_aligned(const char *name, size_t len,
 	const struct rte_memzone *mz = NULL;
 
 	/* both sizes cannot be explicitly called for */
-	if ((flags & RTE_MEMZONE_1GB) && (flags & RTE_MEMZONE_2MB)) {
+	if (((flags & RTE_MEMZONE_1GB) && (flags & RTE_MEMZONE_2MB)) 
+		|| ((flags & RTE_MEMZONE_16MB) && (flags & RTE_MEMZONE_16GB))) {
 		rte_errno = EINVAL;
 		return NULL;
 	}
@@ -344,7 +352,8 @@ rte_memzone_reserve_bounded(const char *name, size_t len,
 	const struct rte_memzone *mz = NULL;
 
 	/* both sizes cannot be explicitly called for */
-	if ((flags & RTE_MEMZONE_1GB) && (flags & RTE_MEMZONE_2MB)) {
+	if (((flags & RTE_MEMZONE_1GB) && (flags & RTE_MEMZONE_2MB)) 
+		|| ((flags & RTE_MEMZONE_16MB) && (flags & RTE_MEMZONE_16GB))) {
 		rte_errno = EINVAL;
 		return NULL;
 	}
diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h
index 4cf8ea9..2ed2637 100644
--- a/lib/librte_eal/common/include/rte_memory.h
+++ b/lib/librte_eal/common/include/rte_memory.h
@@ -53,9 +53,12 @@ extern "C" {
 #endif
 
 enum rte_page_sizes {
-	RTE_PGSIZE_4K = 1 << 12,
-	RTE_PGSIZE_2M = RTE_PGSIZE_4K << 9,
-	RTE_PGSIZE_1G = RTE_PGSIZE_2M <<9
+	RTE_PGSIZE_4K = 1ULL << 12,
+	RTE_PGSIZE_2M = 1ULL << 21,
+	RTE_PGSIZE_1G = 1ULL << 30,
+	RTE_PGSIZE_64K = 1ULL << 16,
+	RTE_PGSIZE_16M = 1ULL << 24,
+	RTE_PGSIZE_16G = 1ULL << 34
 };
 
 #define SOCKET_ID_ANY -1                    /**< Any NUMA socket. */
diff --git a/lib/librte_eal/common/include/rte_memzone.h b/lib/librte_eal/common/include/rte_memzone.h
index 5014409..7d47bff 100644
--- a/lib/librte_eal/common/include/rte_memzone.h
+++ b/lib/librte_eal/common/include/rte_memzone.h
@@ -60,6 +60,8 @@ extern "C" {
 
 #define RTE_MEMZONE_2MB            0x00000001   /**< Use 2MB pages. */
 #define RTE_MEMZONE_1GB            0x00000002   /**< Use 1GB pages. */
+#define RTE_MEMZONE_16MB            0x00000100   /**< Use 16MB pages. */
+#define RTE_MEMZONE_16GB            0x00000200   /**< Use 16GB pages. */
 #define RTE_MEMZONE_SIZE_HINT_ONLY 0x00000004   /**< Use available page size */
 
 /**
@@ -111,6 +113,8 @@ struct rte_memzone {
  *   taken from 1GB or 2MB hugepages.
  *   - RTE_MEMZONE_2MB - Reserve from 2MB pages
  *   - RTE_MEMZONE_1GB - Reserve from 1GB pages
+ *   - RTE_MEMZONE_16MB - Reserve from 16MB pages
+ *   - RTE_MEMZONE_16GB - Reserve from 16GB pages
  *   - RTE_MEMZONE_SIZE_HINT_ONLY - Allow alternative page size to be used if
  *                                  the requested page size is unavailable.
  *                                  If this flag is not set, the function
@@ -156,6 +160,8 @@ const struct rte_memzone *rte_memzone_reserve(const char *name,
  *   taken from 1GB or 2MB hugepages.
  *   - RTE_MEMZONE_2MB - Reserve from 2MB pages
  *   - RTE_MEMZONE_1GB - Reserve from 1GB pages
+ *   - RTE_MEMZONE_16MB - Reserve from 16MB pages
+ *   - RTE_MEMZONE_16GB - Reserve from 16GB pages
  *   - RTE_MEMZONE_SIZE_HINT_ONLY - Allow alternative page size to be used if
  *                                  the requested page size is unavailable.
  *                                  If this flag is not set, the function
@@ -206,6 +212,8 @@ const struct rte_memzone *rte_memzone_reserve_aligned(const char *name,
  *   taken from 1GB or 2MB hugepages.
  *   - RTE_MEMZONE_2MB - Reserve from 2MB pages
  *   - RTE_MEMZONE_1GB - Reserve from 1GB pages
+ *   - RTE_MEMZONE_16MB - Reserve from 16MB pages
+ *   - RTE_MEMZONE_16GB - Reserve from 16GB pages
  *   - RTE_MEMZONE_SIZE_HINT_ONLY - Allow alternative page size to be used if
  *                                  the requested page size is unavailable.
  *                                  If this flag is not set, the function
diff --git a/lib/librte_eal/linuxapp/eal/eal.c b/lib/librte_eal/linuxapp/eal/eal.c
index 8cc1f21..e6947d5 100644
--- a/lib/librte_eal/linuxapp/eal/eal.c
+++ b/lib/librte_eal/linuxapp/eal/eal.c
@@ -619,9 +619,10 @@ eal_parse_base_virtaddr(const char *arg)
 		return -1;
 #endif
 
-	/* align the addr on 2M boundary */
+	/* align the addr on 16M boundary, 16MB is the minimum huge page size on IBM Power architecture.
+	 * If the addr is aligned to 16MB, it can align to 2MB for x86. So this alignment can also be used on x86*/
 	internal_config.base_virtaddr = RTE_PTR_ALIGN_CEIL((uintptr_t)addr,
-	                                                   RTE_PGSIZE_2M);
+	                                                   RTE_PGSIZE_16M);
 
 	return 0;
 }
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [dpdk-dev] [PATCH 12/12] Add memory support for IBM Power Architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (10 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 11/12] Add huge page sizes for IBM Power architecture Chao Zhu
@ 2014-09-26  9:36 ` Chao Zhu
  2014-11-13 10:24 ` [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Thomas Monjalon
  12 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-09-26  9:36 UTC (permalink / raw)
  To: dev

IBM Power architecture has different memory architecture with x86. When
the physical memory address is in ascending order, the mmaped virtual
address is in descending order. This patch modified the memory segment
detection code to make it work for Power.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 config/defconfig_ppc_64-native-linuxapp-gcc   |    1 +
 config/defconfig_x86_64-native-linuxapp-clang |    1 +
 config/defconfig_x86_64-native-linuxapp-gcc   |    1 +
 config/defconfig_x86_64-native-linuxapp-icc   |    1 +
 lib/librte_eal/linuxapp/eal/eal_memory.c      |   19 +++++++++++++++++--
 5 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/config/defconfig_ppc_64-native-linuxapp-gcc b/config/defconfig_ppc_64-native-linuxapp-gcc
index cc11cfc..c29888c 100644
--- a/config/defconfig_ppc_64-native-linuxapp-gcc
+++ b/config/defconfig_ppc_64-native-linuxapp-gcc
@@ -34,6 +34,7 @@ CONFIG_RTE_MACHINE="powerpc"
 
 CONFIG_RTE_ARCH="powerpc"
 CONFIG_RTE_ARCH_PPC_64=y
+CONFIG_RTE_ARCH_64=y
 CONFIG_RTE_ARCH_BIG_ENDIAN=y
 
 CONFIG_RTE_TOOLCHAIN="gcc"
diff --git a/config/defconfig_x86_64-native-linuxapp-clang b/config/defconfig_x86_64-native-linuxapp-clang
index bbda080..5f3074e 100644
--- a/config/defconfig_x86_64-native-linuxapp-clang
+++ b/config/defconfig_x86_64-native-linuxapp-clang
@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native"
 
 CONFIG_RTE_ARCH="x86_64"
 CONFIG_RTE_ARCH_X86_64=y
+CONFIG_RTE_ARCH_64=y
 
 CONFIG_RTE_TOOLCHAIN="clang"
 CONFIG_RTE_TOOLCHAIN_CLANG=y
diff --git a/config/defconfig_x86_64-native-linuxapp-gcc b/config/defconfig_x86_64-native-linuxapp-gcc
index 3de818a..60baf5b 100644
--- a/config/defconfig_x86_64-native-linuxapp-gcc
+++ b/config/defconfig_x86_64-native-linuxapp-gcc
@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native"
 
 CONFIG_RTE_ARCH="x86_64"
 CONFIG_RTE_ARCH_X86_64=y
+CONFIG_RTE_ARCH_64=y
 
 CONFIG_RTE_TOOLCHAIN="gcc"
 CONFIG_RTE_TOOLCHAIN_GCC=y
diff --git a/config/defconfig_x86_64-native-linuxapp-icc b/config/defconfig_x86_64-native-linuxapp-icc
index 795333b..71d1e28 100644
--- a/config/defconfig_x86_64-native-linuxapp-icc
+++ b/config/defconfig_x86_64-native-linuxapp-icc
@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native"
 
 CONFIG_RTE_ARCH="x86_64"
 CONFIG_RTE_ARCH_X86_64=y
+CONFIG_RTE_ARCH_64=y
 
 CONFIG_RTE_TOOLCHAIN="icc"
 CONFIG_RTE_TOOLCHAIN_ICC=y
diff --git a/lib/librte_eal/linuxapp/eal/eal_memory.c b/lib/librte_eal/linuxapp/eal/eal_memory.c
index f2454f4..6694e08 100644
--- a/lib/librte_eal/linuxapp/eal/eal_memory.c
+++ b/lib/librte_eal/linuxapp/eal/eal_memory.c
@@ -316,7 +316,7 @@ map_all_hugepages(struct hugepage_file *hugepg_tbl,
 #endif
 			hugepg_tbl[i].filepath[sizeof(hugepg_tbl[i].filepath) - 1] = '\0';
 		}
-#ifndef RTE_ARCH_X86_64
+#ifndef RTE_ARCH_64
 		/* for 32-bit systems, don't remap 1G pages, just reuse original
 		 * map address as final map address.
 		 */
@@ -412,7 +412,7 @@ remap_all_hugepages(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)
 
 	while (i < hpi->num_pages[0]) {
 
-#ifndef RTE_ARCH_X86_64
+#ifndef RTE_ARCH_64
 		/* for 32-bit systems, don't remap 1G pages, just reuse original
 		 * map address as final map address.
 		 */
@@ -1263,9 +1263,18 @@ rte_eal_hugepage_init(void)
 		else if ((hugepage[i].physaddr - hugepage[i-1].physaddr) !=
 		    hugepage[i].size)
 			new_memseg = 1;
+#ifdef RTE_ARCH_PPC_64
+		/* IBM Power architecture has different memory layout. 
+		 * If the physical address is lower address first, the mmaped virtual
+		 * address will be higher address first */
+		else if (((unsigned long)hugepage[i-1].final_va -
+		    (unsigned long)hugepage[i].final_va) != hugepage[i].size)
+			new_memseg = 1;
+#else
 		else if (((unsigned long)hugepage[i].final_va -
 		    (unsigned long)hugepage[i-1].final_va) != hugepage[i].size)
 			new_memseg = 1;
+#endif
 
 		if (new_memseg) {
 			j += 1;
@@ -1284,6 +1293,12 @@ rte_eal_hugepage_init(void)
 		}
 		/* continuation of previous memseg */
 		else {
+#ifdef RTE_ARCH_PPC_64
+		/* Use the phy and virt address of the last page as segment address 
+		 * for IBM Power architecture */ 
+			mcfg->memseg[j].phys_addr = hugepage[i].physaddr;
+			mcfg->memseg[j].addr = hugepage[i].final_va;
+#endif
 			mcfg->memseg[j].len += mcfg->memseg[j].hugepage_sz;
 		}
 		hugepage[i].memseg_id = j;
-- 
1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 02/12] Add atomic operations " Chao Zhu
@ 2014-09-29  6:16   ` Hemant
  2014-09-29  6:41     ` Chao CH Zhu
  2014-10-16  0:39   ` Ananyev, Konstantin
  1 sibling, 1 reply; 26+ messages in thread
From: Hemant @ 2014-09-29  6:16 UTC (permalink / raw)
  To: Chao Zhu, dev

Hi Chao,

This Patch seems to be incomplete. You may also need to patch the librte_eal\common\include\rte_atomic.h 
e.g.
#if !(defined RTE_ARCH_X86_64) || !(defined RTE_ARCH_I686)
#include <arch/rte_atomic.h>
#else /* if Intel*/

Otherwise you shall be getting compilation errors for "_mm_mfence"

Similar is true for other common header files as well.


Regards,
Hemant

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu
> Sent: 26/Sep/2014 3:06 PM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power
> architecture
> 
> The atomic operations implemented with assembly code in DPDK only support
> x86. This patch add architecture specific atomic operations for IBM Power
> architecture.
> 
> Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> ---
>  .../common/include/powerpc/arch/rte_atomic.h       |  387
> ++++++++++++++++++++
>  .../common/include/powerpc/arch/rte_atomic_arch.h  |  318
> ++++++++++++++++
>  2 files changed, 705 insertions(+), 0 deletions(-)  create mode 100644
> lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
>  create mode 100644
> lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> 
> diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> b/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> new file mode 100644
> index 0000000..7f5214e
> --- /dev/null
> +++ b/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> @@ -0,0 +1,387 @@
> +/*
> + *   BSD LICENSE
> + *
> + *   Copyright (C) IBM Corporation 2014.
> + *
> + *   Redistribution and use in source and binary forms, with or without
> + *   modification, are permitted provided that the following conditions
> + *   are met:
> + *
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyright
> + *       notice, this list of conditions and the following disclaimer in
> + *       the documentation and/or other materials provided with the
> + *       distribution.
> + *     * Neither the name of IBM Corporation nor the names of its
> + *       contributors may be used to endorse or promote products derived
> + *       from this software without specific prior written permission.
> + *
> + *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
> CONTRIBUTORS
> + *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
> NOT
> + *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
> FITNESS FOR
> + *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
> COPYRIGHT
> + *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
> INCIDENTAL,
> + *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> NOT
> + *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
> OF USE,
> + *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> ON ANY
> + *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
> THE USE
> + *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> DAMAGE.
> +*/
> +
> +/*
> + * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
> + * Copyright (c) 2008 Marcel Moolenaar
> + * Copyright (c) 2001 Benno Rice
> + * Copyright (c) 2001 David E. O'Brien
> + * Copyright (c) 1998 Doug Rabson
> + * All rights reserved.
> + */
> +
> +#ifndef _RTE_ATOMIC_H_
> +#error "don't include this file directly, please include generic <rte_atomic.h>"
> +#endif
> +
> +#ifndef _RTE_POWERPC_64_ATOMIC_H_
> +#define _RTE_POWERPC_64_ATOMIC_H_
> +
> +/*------------------------- 64 bit atomic operations
> +-------------------------*/
> +
> +/**
> + * An atomic compare and set function used by the mutex functions.
> + * (atomic) equivalent to:
> + *   if (*dst == exp)
> + *     *dst = src (all 64-bit words)
> + *
> + * @param dst
> + *   The destination into which the value will be written.
> + * @param exp
> + *   The expected value.
> + * @param src
> + *   The new value.
> + * @return
> + *   Non-zero on success; 0 on failure.
> + */
> +static inline int
> +rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
> +{
> +	unsigned int ret = 0;
> +
> +	asm volatile (
> +			"\tlwsync\n"
> +			"1: ldarx %[ret], 0, %[dst]\n"
> +			"cmpld %[exp], %[ret]\n"
> +			"bne 2f\n"
> +			"stdcx. %[src], 0, %[dst]\n"
> +			"bne- 1b\n"
> +			"li %[ret], 1\n"
> +			"b 3f\n"
> +			"2:\n"
> +			"stdcx. %[ret], 0, %[dst]\n"
> +			"li %[ret], 0\n"
> +			"3:\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret), "=m" (*dst)
> +			: [dst] "r" (dst), [exp] "r" (exp), [src] "r" (src), "m" (*dst)
> +			: "cc", "memory");
> +	return ret;
> +}
> +
> +/**
> + * The atomic counter structure.
> + */
> +typedef struct {
> +	volatile int64_t cnt;  /**< Internal counter value. */ }
> +rte_atomic64_t;
> +
> +/**
> + * Static initializer for an atomic counter.
> + */
> +#define RTE_ATOMIC64_INIT(val) { (val) }
> +
> +/**
> + * Initialize the atomic counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_atomic64_init(rte_atomic64_t *v)
> +{
> +	v->cnt = 0;
> +}
> +
> +/**
> + * Atomically read a 64-bit counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   The value of the counter.
> + */
> +static inline int64_t
> +rte_atomic64_read(rte_atomic64_t *v)
> +{
> +	long ret;
> +
> +	asm volatile("ld%U1%X1 %[ret],%[cnt]" : [ret] "=r"(ret) : [cnt]
> +"m"(v->cnt));
> +
> +	return ret;
> +}
> +
> +/**
> + * Atomically set a 64-bit counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param new_value
> + *   The new value of the counter.
> + */
> +static inline void
> +rte_atomic64_set(rte_atomic64_t *v, int64_t new_value) {
> +	asm volatile("std%U0%X0 %[new_value],%[cnt]" : [cnt] "=m"(v->cnt) :
> +[new_value] "r"(new_value)); }
> +
> +/**
> + * Atomically add a 64-bit value to a counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param inc
> + *   The value to be added to the counter.
> + */
> +static inline void
> +rte_atomic64_add(rte_atomic64_t *v, int64_t inc) {
> +	long t;
> +
> +	asm volatile(
> +			"1: ldarx %[t],0,%[cnt]\n"
> +			"add %[t],%[inc],%[t]\n"
> +			"stdcx. %[t],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			: [t] "=&r" (t), "=m" (v->cnt)
> +			: [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
> +			: "cc", "memory");
> +}
> +
> +/**
> + * Atomically subtract a 64-bit value from a counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param dec
> + *   The value to be subtracted from the counter.
> + */
> +static inline void
> +rte_atomic64_sub(rte_atomic64_t *v, int64_t dec) {
> +	long t;
> +
> +	asm volatile(
> +			"1: ldarx %[t],0,%[cnt]\n"
> +			"subf %[t],%[dec],%[t]\n"
> +			"stdcx. %[t],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			: [t] "=&r" (t), "+m" (v->cnt)
> +			: [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
> +			: "cc", "memory");
> +}
> +
> +/**
> + * Atomically increment a 64-bit counter by one and test.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_atomic64_inc(rte_atomic64_t *v)
> +{
> +	long t;
> +
> +	asm volatile(
> +			"1: ldarx %[t],0,%[cnt]\n"
> +			"addic %[t],%[t],1\n"
> +			"stdcx. %[t],0,%[cnt] \n"
> +			"bne- 1b\n"
> +			: [t] "=&r" (t), "+m" (v->cnt)
> +			: [cnt] "r" (&v->cnt), "m" (v->cnt)
> +			: "cc", "xer", "memory");
> +}
> +
> +/**
> + * Atomically decrement a 64-bit counter by one and test.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_atomic64_dec(rte_atomic64_t *v)
> +{
> +	long t;
> +
> +	asm volatile(
> +			"1: ldarx %[t],0,%[cnt]\n"
> +			"addic %[t],%[t],-1\n"
> +			"stdcx. %[t],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			: [t] "=&r" (t), "+m" (v->cnt)
> +			: [cnt] "r" (&v->cnt), "m" (v->cnt)
> +			: "cc", "xer", "memory");
> +}
> +
> +/**
> + * Add a 64-bit value to an atomic counter and return the result.
> + *
> + * Atomically adds the 64-bit value (inc) to the atomic counter (v) and
> + * returns the value of v after the addition.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param inc
> + *   The value to be added to the counter.
> + * @return
> + *   The value of v after the addition.
> + */
> +static inline int64_t
> +rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc) {
> +	long ret;
> +
> +	asm volatile(
> +			"\n\tlwsync\n"
> +			"1: ldarx %[ret],0,%[cnt]\n"
> +			"add %[ret],%[inc],%[ret]\n"
> +			"stdcx. %[ret],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret)
> +			: [inc] "r" (inc), [cnt] "r" (&v->cnt)
> +			: "cc", "memory");
> +
> +	return ret;
> +}
> +
> +/**
> + * Subtract a 64-bit value from an atomic counter and return the result.
> + *
> + * Atomically subtracts the 64-bit value (dec) from the atomic counter
> +(v)
> + * and returns the value of v after the subtraction.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param dec
> + *   The value to be subtracted from the counter.
> + * @return
> + *   The value of v after the subtraction.
> + */
> +static inline int64_t
> +rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec) {
> +	long ret;
> +
> +	asm volatile(
> +			"\n\tlwsync\n"
> +			"1: ldarx %[ret],0,%[cnt]\n"
> +			"subf %[ret],%[dec],%[ret]\n"
> +			"stdcx. %[ret],0,%[cnt] \n"
> +			"bne- 1b\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret)
> +			: [dec] "r" (dec), [cnt] "r" (&v->cnt)
> +			: "cc", "memory");
> +
> +	return ret;
> +}
> +
> +static __inline__ long rte_atomic64_inc_return(rte_atomic64_t *v) {
> +	long ret;
> +
> +	asm volatile(
> +			"\n\tlwsync\n"
> +			"1: ldarx %[ret],0,%[cnt]\n"
> +			"addic %[ret],%[ret],1\n"
> +			"stdcx. %[ret],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret)
> +			: [cnt] "r" (&v->cnt)
> +			: "cc", "xer", "memory");
> +
> +	return ret;
> +}
> +/**
> + * Atomically increment a 64-bit counter by one and test.
> + *
> + * Atomically increments the atomic counter (v) by one and returns
> + * true if the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the addition is 0; false otherwise.
> + */
> +#define rte_atomic64_inc_and_test(v) (rte_atomic64_inc_return(v) == 0)
> +
> +static __inline__ long rte_atomic64_dec_return(rte_atomic64_t *v) {
> +	long ret;
> +
> +	asm volatile(
> +			"\n\tlwsync\n"
> +			"1: ldarx %[ret],0,%[cnt]\n"
> +			"addic %[ret],%[ret],-1\n"
> +			"stdcx. %[ret],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret)
> +			: [cnt] "r" (&v->cnt)
> +			: "cc", "xer", "memory");
> +
> +	return ret;
> +}
> +/**
> + * Atomically decrement a 64-bit counter by one and test.
> + *
> + * Atomically decrements the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after subtraction is 0; false otherwise.
> + */
> +#define rte_atomic64_dec_and_test(v)    (rte_atomic64_dec_return((v)) ==
> 0)
> +
> +/**
> + * Atomically test and set a 64-bit atomic counter.
> + *
> + * If the counter value is already set, return 0 (failed). Otherwise,
> +set
> + * the counter value to 1 and return 1 (success).
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   0 if failed; else 1, success.
> + */
> +static inline int rte_atomic64_test_and_set(rte_atomic64_t *v) {
> +	return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1); }
> +
> +/**
> + * Atomically set a 64-bit counter to 0.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void rte_atomic64_clear(rte_atomic64_t *v) {
> +	v->cnt = 0;
> +}
> +
> +#endif /* _RTE_POWERPC_64_ATOMIC_H_ */
> +
> diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> new file mode 100644
> index 0000000..fe5666e
> --- /dev/null
> +++ b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> @@ -0,0 +1,318 @@
> +/*
> + *   BSD LICENSE
> + *
> + *   Copyright (C) IBM Corporation 2014.
> + *
> + *   Redistribution and use in source and binary forms, with or without
> + *   modification, are permitted provided that the following conditions
> + *   are met:
> + *
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyright
> + *       notice, this list of conditions and the following disclaimer in
> + *       the documentation and/or other materials provided with the
> + *       distribution.
> + *     * Neither the name of IBM Corporation nor the names of its
> + *       contributors may be used to endorse or promote products derived
> + *       from this software without specific prior written permission.
> + *
> + *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
> CONTRIBUTORS
> + *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
> NOT
> + *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
> FITNESS FOR
> + *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
> COPYRIGHT
> + *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
> INCIDENTAL,
> + *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> NOT
> + *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
> OF USE,
> + *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> ON ANY
> + *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
> THE USE
> + *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> DAMAGE.
> +*/
> +
> +/*
> + * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
> + * Copyright (c) 2008 Marcel Moolenaar
> + * Copyright (c) 2001 Benno Rice
> + * Copyright (c) 2001 David E. O'Brien
> + * Copyright (c) 1998 Doug Rabson
> + * All rights reserved.
> + */
> +
> +#ifndef _RTE_ATOMIC_H_
> +#error "don't include this file directly, please include generic <rte_atomic.h>"
> +#endif
> +
> +#ifndef _RTE_ATOMIC_ARCH_H_
> +#define _RTE_ATOMIC_ARCH_H_
> +
> +#include <stdint.h>
> +
> +/**
> + * General memory barrier.
> + *
> + * Guarantees that the LOAD and STORE operations generated before the
> + * barrier occur before the LOAD and STORE operations generated after.
> + */
> +#define	rte_arch_mb()  asm volatile("sync" : : : "memory")
> +
> +/**
> + * Write memory barrier.
> + *
> + * Guarantees that the STORE operations generated before the barrier
> + * occur before the STORE operations generated after.
> + */
> +#define	rte_arch_wmb() asm volatile("sync" : : : "memory")
> +
> +/**
> + * Read memory barrier.
> + *
> + * Guarantees that the LOAD operations generated before the barrier
> + * occur before the LOAD operations generated after.
> + */
> +#define	rte_arch_rmb() asm volatile("sync" : : : "memory")
> +
> +#define	rte_arch_compiler_barrier() do {		\
> +	asm volatile ("" : : : "memory");	\
> +} while(0)
> +
> +/*------------------------- 16 bit atomic operations
> +-------------------------*/
> +
> +/**
> + * The atomic counter structure.
> + */
> +typedef struct {
> +	volatile int16_t cnt; /**< An internal counter value. */ }
> +rte_atomic16_t;
> +
> +/**
> + * Atomic compare and set.
> + *
> + * (atomic) equivalent to:
> + *   if (*dst == exp)
> + *     *dst = src (all 16-bit words)
> + *
> + * @param dst
> + *   The destination location into which the value will be written.
> + * @param exp
> + *   The expected value.
> + * @param src
> + *   The new value.
> + * @return
> + *   Non-zero on success; 0 on failure.
> + */
> +static inline int
> +rte_arch_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t
> +src) {
> +	return __atomic_compare_exchange(dst, &exp, &src, 0,
> __ATOMIC_ACQUIRE,
> +__ATOMIC_ACQUIRE) ? 1 : 0; }
> +
> +/**
> + * Atomically increment a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic16_inc(rte_atomic16_t *v) {
> +	__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); }
> +
> +/**
> + * Atomically decrement a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic16_dec(rte_atomic16_t *v) {
> +	__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); }
> +
> +/**
> + * Atomically increment a 16-bit counter by one and test.
> + *
> + * Atomically increments the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the increment operation is 0; false otherwise.
> + */
> +static inline int rte_arch_atomic16_inc_and_test(rte_atomic16_t *v) {
> +	return (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0); }
> +
> +/**
> + * Atomically decrement a 16-bit counter by one and test.
> + *
> + * Atomically decrements the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the decrement operation is 0; false otherwise.
> + */
> +static inline int rte_arch_atomic16_dec_and_test(rte_atomic16_t *v) {
> +	return (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0); }
> +
> +/*------------------------- 32 bit atomic operations
> +-------------------------*/
> +
> +/**
> + * The atomic counter structure.
> + */
> +typedef struct {
> +	volatile int32_t cnt; /**< An internal counter value. */ }
> +rte_atomic32_t;
> +
> +/**
> + * Atomic compare and set.
> + *
> + * (atomic) equivalent to:
> + *   if (*dst == exp)
> + *     *dst = src (all 32-bit words)
> + *
> + * @param dst
> + *   The destination location into which the value will be written.
> + * @param exp
> + *   The expected value.
> + * @param src
> + *   The new value.
> + * @return
> + *   Non-zero on success; 0 on failure.
> + */
> +static inline int
> +rte_arch_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t
> +src) {
> +	unsigned int ret = 0;
> +
> +	asm volatile(
> +			"\tlwsync\n"
> +			"1:\tlwarx %[ret], 0, %[dst]\n"
> +			"cmplw %[exp], %[ret]\n"
> +			"bne 2f\n"
> +			"stwcx. %[src], 0, %[dst]\n"
> +			"bne- 1b\n"
> +			"li %[ret], 1\n"
> +			"b 3f\n"
> +			"2:\n"
> +			"stwcx. %[ret], 0, %[dst]\n"
> +			"li %[ret], 0\n"
> +			"3:\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret), "=m" (*dst)
> +			: [dst] "r" (dst), [exp] "r" (exp), [src] "r" (src), "m" (*dst)
> +			: "cc", "memory");
> +
> +	return ret;
> +}
> +
> +/**
> + * Atomically increment a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic32_inc(rte_atomic32_t *v) {
> +	int t;
> +
> +	asm volatile(
> +			"1: lwarx %[t],0,%[cnt]\n"
> +			"addic %[t],%[t],1\n"
> +			"stwcx. %[t],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			: [t] "=&r" (t), "=m" (v->cnt)
> +			: [cnt] "r" (&v->cnt), "m" (v->cnt)
> +			: "cc", "xer", "memory");
> +}
> +
> +/**
> + * Atomically decrement a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic32_dec(rte_atomic32_t *v) {
> +	int t;
> +
> +	asm volatile(
> +			"1: lwarx %[t],0,%[cnt]\n"
> +			"addic %[t],%[t],-1\n"
> +			"stwcx. %[t],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			: [t] "=&r" (t), "=m" (v->cnt)
> +			: [cnt] "r" (&v->cnt), "m" (v->cnt)
> +			: "cc", "xer", "memory");
> +}
> +
> +/**
> + * Atomically increment a 32-bit counter by one and test.
> + *
> + * Atomically increments the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the increment operation is 0; false otherwise.
> + */
> +static inline int rte_arch_atomic32_inc_and_test(rte_atomic32_t *v) {
> +	int ret;
> +
> +	asm volatile(
> +			"\n\tlwsync\n"
> +			"1: lwarx %[ret],0,%[cnt]\n"
> +			"addic	%[ret],%[ret],1\n"
> +			"stwcx. %[ret],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret)
> +			: [cnt] "r" (&v->cnt)
> +			: "cc", "xer", "memory");
> +
> +	return (ret == 0);
> +}
> +
> +/**
> + * Atomically decrement a 32-bit counter by one and test.
> + *
> + * Atomically decrements the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the decrement operation is 0; false otherwise.
> + */
> +static inline int rte_arch_atomic32_dec_and_test(rte_atomic32_t *v) {
> +	int ret;
> +
> +	asm volatile(
> +			"\n\tlwsync\n"
> +			"1: lwarx %[ret],0,%[cnt]\n"
> +			"addic %[ret],%[ret],-1\n"
> +			"stwcx. %[ret],0,%[cnt]\n"
> +			"bne- 1b\n"
> +			"isync\n"
> +			: [ret] "=&r" (ret)
> +			: [cnt] "r" (&v->cnt)
> +			: "cc", "xer", "memory");
> +
> +	return (ret == 0);
> +}
> +
> +#endif /* _RTE_ATOMIC_ARCH_H_ */
> +
> --
> 1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture Chao Zhu
@ 2014-09-29  6:21   ` Hemant
  0 siblings, 0 replies; 26+ messages in thread
From: Hemant @ 2014-09-29  6:21 UTC (permalink / raw)
  To: Chao Zhu, dev

> --- a/mk/arch/powerpc/rte.vars.mk
> +++ b/mk/arch/powerpc/rte.vars.mk
> @@ -32,7 +32,7 @@
>  ARCH  ?= powerpc
>  CROSS ?=
> 
> -CPU_CFLAGS  ?= -m64
> +CPU_CFLAGS  ?= -m64 -DCACHE_LINE_SIZE=128

 [hemant]  Instead of hardcoding the CACHE_LINE_SIZE,  can you drive the CACHE_LINE_SIZE from config file.  Other powerpc processor have it as 64.


>  CPU_LDFLAGS ?=
>  CPU_ASFLAGS ?= -felf64
> 
> --
> 1.7.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
  2014-09-29  6:16   ` Hemant
@ 2014-09-29  6:41     ` Chao CH Zhu
  0 siblings, 0 replies; 26+ messages in thread
From: Chao CH Zhu @ 2014-09-29  6:41 UTC (permalink / raw)
  To: Hemant; +Cc: dev

Hi, Hemant 

Actually, I submitted another set of patches to split the architecture 
specific operations which includes the patch to 
librte_eal\common\include\rte_atomic.h. Please refer to the previous 
email.   

Best Regards!
------------------------------
Chao Zhu (祝超)
Research Staff Member
Cloud Infrastructure and Technology Group
IBM China Research Lab
Building 19 Zhongguancun Software Park
8 Dongbeiwang West Road, Haidian District,
Beijing, PRC. 100193
Tel: +86-10-58748711
Email: bjzhuc@cn.ibm.com




From:   "Hemant@freescale.com" <Hemant@freescale.com>
To:     Chao CH Zhu/China/IBM@IBMCN, "dev@dpdk.org" <dev@dpdk.org>
Date:   2014/09/29 14:15
Subject:        RE: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM 
Power   architecture



Hi Chao,

This Patch seems to be incomplete. You may also need to patch the 
librte_eal\common\include\rte_atomic.h 
e.g.
#if !(defined RTE_ARCH_X86_64) || !(defined RTE_ARCH_I686)
#include <arch/rte_atomic.h>
#else /* if Intel*/

Otherwise you shall be getting compilation errors for "_mm_mfence"

Similar is true for other common header files as well.


Regards,
Hemant

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu
> Sent: 26/Sep/2014 3:06 PM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power
> architecture
> 
> The atomic operations implemented with assembly code in DPDK only 
support
> x86. This patch add architecture specific atomic operations for IBM 
Power
> architecture.
> 
> Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> ---
>  .../common/include/powerpc/arch/rte_atomic.h       |  387
> ++++++++++++++++++++
>  .../common/include/powerpc/arch/rte_atomic_arch.h  |  318
> ++++++++++++++++
>  2 files changed, 705 insertions(+), 0 deletions(-)  create mode 100644
> lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
>  create mode 100644
> lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> 
> diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> b/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> new file mode 100644
> index 0000000..7f5214e
> --- /dev/null
> +++ b/lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> @@ -0,0 +1,387 @@
> +/*
> + *   BSD LICENSE
> + *
> + *   Copyright (C) IBM Corporation 2014.
> + *
> + *   Redistribution and use in source and binary forms, with or without
> + *   modification, are permitted provided that the following conditions
> + *   are met:
> + *
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above 
copyright
> + *       notice, this list of conditions and the following disclaimer 
in
> + *       the documentation and/or other materials provided with the
> + *       distribution.
> + *     * Neither the name of IBM Corporation nor the names of its
> + *       contributors may be used to endorse or promote products 
derived
> + *       from this software without specific prior written permission.
> + *
> + *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
> CONTRIBUTORS
> + *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
> NOT
> + *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
> FITNESS FOR
> + *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
> COPYRIGHT
> + *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
> INCIDENTAL,
> + *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> NOT
> + *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
> OF USE,
> + *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> ON ANY
> + *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 
TORT
> + *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
> THE USE
> + *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> DAMAGE.
> +*/
> +
> +/*
> + * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
> + * Copyright (c) 2008 Marcel Moolenaar
> + * Copyright (c) 2001 Benno Rice
> + * Copyright (c) 2001 David E. O'Brien
> + * Copyright (c) 1998 Doug Rabson
> + * All rights reserved.
> + */
> +
> +#ifndef _RTE_ATOMIC_H_
> +#error "don't include this file directly, please include generic 
<rte_atomic.h>"
> +#endif
> +
> +#ifndef _RTE_POWERPC_64_ATOMIC_H_
> +#define _RTE_POWERPC_64_ATOMIC_H_
> +
> +/*------------------------- 64 bit atomic operations
> +-------------------------*/
> +
> +/**
> + * An atomic compare and set function used by the mutex functions.
> + * (atomic) equivalent to:
> + *   if (*dst == exp)
> + *     *dst = src (all 64-bit words)
> + *
> + * @param dst
> + *   The destination into which the value will be written.
> + * @param exp
> + *   The expected value.
> + * @param src
> + *   The new value.
> + * @return
> + *   Non-zero on success; 0 on failure.
> + */
> +static inline int
> +rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
> +{
> +              unsigned int ret = 0;
> +
> +              asm volatile (
> +                                              "\tlwsync\n"
> +                                              "1: ldarx %[ret], 0, 
%[dst]\n"
> +                                              "cmpld %[exp], %[ret]\n"
> +                                              "bne 2f\n"
> +                                              "stdcx. %[src], 0, 
%[dst]\n"
> +                                              "bne- 1b\n"
> +                                              "li %[ret], 1\n"
> +                                              "b 3f\n"
> +                                              "2:\n"
> +                                              "stdcx. %[ret], 0, 
%[dst]\n"
> +                                              "li %[ret], 0\n"
> +                                              "3:\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret), "=m" 
(*dst)
> +                                              : [dst] "r" (dst), [exp] 
"r" (exp), [src] "r" (src), "m" (*dst)
> +                                              : "cc", "memory");
> +              return ret;
> +}
> +
> +/**
> + * The atomic counter structure.
> + */
> +typedef struct {
> +              volatile int64_t cnt;  /**< Internal counter value. */ }
> +rte_atomic64_t;
> +
> +/**
> + * Static initializer for an atomic counter.
> + */
> +#define RTE_ATOMIC64_INIT(val) { (val) }
> +
> +/**
> + * Initialize the atomic counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_atomic64_init(rte_atomic64_t *v)
> +{
> +              v->cnt = 0;
> +}
> +
> +/**
> + * Atomically read a 64-bit counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   The value of the counter.
> + */
> +static inline int64_t
> +rte_atomic64_read(rte_atomic64_t *v)
> +{
> +              long ret;
> +
> +              asm volatile("ld%U1%X1 %[ret],%[cnt]" : [ret] "=r"(ret) : 
[cnt]
> +"m"(v->cnt));
> +
> +              return ret;
> +}
> +
> +/**
> + * Atomically set a 64-bit counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param new_value
> + *   The new value of the counter.
> + */
> +static inline void
> +rte_atomic64_set(rte_atomic64_t *v, int64_t new_value) {
> +              asm volatile("std%U0%X0 %[new_value],%[cnt]" : [cnt] 
"=m"(v->cnt) :
> +[new_value] "r"(new_value)); }
> +
> +/**
> + * Atomically add a 64-bit value to a counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param inc
> + *   The value to be added to the counter.
> + */
> +static inline void
> +rte_atomic64_add(rte_atomic64_t *v, int64_t inc) {
> +              long t;
> +
> +              asm volatile(
> +                                              "1: ldarx 
%[t],0,%[cnt]\n"
> +                                              "add %[t],%[inc],%[t]\n"
> +                                              "stdcx. %[t],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              : [t] "=&r" (t), "=m" 
(v->cnt)
> +                                              : [cnt] "r" (&v->cnt), 
[inc] "r" (inc), "m" (v->cnt)
> +                                              : "cc", "memory");
> +}
> +
> +/**
> + * Atomically subtract a 64-bit value from a counter.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param dec
> + *   The value to be subtracted from the counter.
> + */
> +static inline void
> +rte_atomic64_sub(rte_atomic64_t *v, int64_t dec) {
> +              long t;
> +
> +              asm volatile(
> +                                              "1: ldarx 
%[t],0,%[cnt]\n"
> +                                              "subf %[t],%[dec],%[t]\n"
> +                                              "stdcx. %[t],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              : [t] "=&r" (t), "+m" 
(v->cnt)
> +                                              : [cnt] "r" (&v->cnt), 
[dec] "r" (dec), "m" (v->cnt)
> +                                              : "cc", "memory");
> +}
> +
> +/**
> + * Atomically increment a 64-bit counter by one and test.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_atomic64_inc(rte_atomic64_t *v)
> +{
> +              long t;
> +
> +              asm volatile(
> +                                              "1: ldarx 
%[t],0,%[cnt]\n"
> +                                              "addic %[t],%[t],1\n"
> +                                              "stdcx. %[t],0,%[cnt] \n"
> +                                              "bne- 1b\n"
> +                                              : [t] "=&r" (t), "+m" 
(v->cnt)
> +                                              : [cnt] "r" (&v->cnt), 
"m" (v->cnt)
> +                                              : "cc", "xer", "memory");
> +}
> +
> +/**
> + * Atomically decrement a 64-bit counter by one and test.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_atomic64_dec(rte_atomic64_t *v)
> +{
> +              long t;
> +
> +              asm volatile(
> +                                              "1: ldarx 
%[t],0,%[cnt]\n"
> +                                              "addic %[t],%[t],-1\n"
> +                                              "stdcx. %[t],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              : [t] "=&r" (t), "+m" 
(v->cnt)
> +                                              : [cnt] "r" (&v->cnt), 
"m" (v->cnt)
> +                                              : "cc", "xer", "memory");
> +}
> +
> +/**
> + * Add a 64-bit value to an atomic counter and return the result.
> + *
> + * Atomically adds the 64-bit value (inc) to the atomic counter (v) and
> + * returns the value of v after the addition.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param inc
> + *   The value to be added to the counter.
> + * @return
> + *   The value of v after the addition.
> + */
> +static inline int64_t
> +rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc) {
> +              long ret;
> +
> +              asm volatile(
> +                                              "\n\tlwsync\n"
> +                                              "1: ldarx 
%[ret],0,%[cnt]\n"
> +                                              "add 
%[ret],%[inc],%[ret]\n"
> +                                              "stdcx. 
%[ret],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret)
> +                                              : [inc] "r" (inc), [cnt] 
"r" (&v->cnt)
> +                                              : "cc", "memory");
> +
> +              return ret;
> +}
> +
> +/**
> + * Subtract a 64-bit value from an atomic counter and return the 
result.
> + *
> + * Atomically subtracts the 64-bit value (dec) from the atomic counter
> +(v)
> + * and returns the value of v after the subtraction.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @param dec
> + *   The value to be subtracted from the counter.
> + * @return
> + *   The value of v after the subtraction.
> + */
> +static inline int64_t
> +rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec) {
> +              long ret;
> +
> +              asm volatile(
> +                                              "\n\tlwsync\n"
> +                                              "1: ldarx 
%[ret],0,%[cnt]\n"
> +                                              "subf 
%[ret],%[dec],%[ret]\n"
> +                                              "stdcx. %[ret],0,%[cnt] 
\n"
> +                                              "bne- 1b\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret)
> +                                              : [dec] "r" (dec), [cnt] 
"r" (&v->cnt)
> +                                              : "cc", "memory");
> +
> +              return ret;
> +}
> +
> +static __inline__ long rte_atomic64_inc_return(rte_atomic64_t *v) {
> +              long ret;
> +
> +              asm volatile(
> +                                              "\n\tlwsync\n"
> +                                              "1: ldarx 
%[ret],0,%[cnt]\n"
> +                                              "addic %[ret],%[ret],1\n"
> +                                              "stdcx. 
%[ret],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret)
> +                                              : [cnt] "r" (&v->cnt)
> +                                              : "cc", "xer", "memory");
> +
> +              return ret;
> +}
> +/**
> + * Atomically increment a 64-bit counter by one and test.
> + *
> + * Atomically increments the atomic counter (v) by one and returns
> + * true if the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the addition is 0; false otherwise.
> + */
> +#define rte_atomic64_inc_and_test(v) (rte_atomic64_inc_return(v) == 0)
> +
> +static __inline__ long rte_atomic64_dec_return(rte_atomic64_t *v) {
> +              long ret;
> +
> +              asm volatile(
> +                                              "\n\tlwsync\n"
> +                                              "1: ldarx 
%[ret],0,%[cnt]\n"
> +                                              "addic 
%[ret],%[ret],-1\n"
> +                                              "stdcx. 
%[ret],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret)
> +                                              : [cnt] "r" (&v->cnt)
> +                                              : "cc", "xer", "memory");
> +
> +              return ret;
> +}
> +/**
> + * Atomically decrement a 64-bit counter by one and test.
> + *
> + * Atomically decrements the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after subtraction is 0; false otherwise.
> + */
> +#define rte_atomic64_dec_and_test(v)    (rte_atomic64_dec_return((v)) 
==
> 0)
> +
> +/**
> + * Atomically test and set a 64-bit atomic counter.
> + *
> + * If the counter value is already set, return 0 (failed). Otherwise,
> +set
> + * the counter value to 1 and return 1 (success).
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   0 if failed; else 1, success.
> + */
> +static inline int rte_atomic64_test_and_set(rte_atomic64_t *v) {
> +              return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 
0, 1); }
> +
> +/**
> + * Atomically set a 64-bit counter to 0.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void rte_atomic64_clear(rte_atomic64_t *v) {
> +              v->cnt = 0;
> +}
> +
> +#endif /* _RTE_POWERPC_64_ATOMIC_H_ */
> +
> diff --git 
a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> new file mode 100644
> index 0000000..fe5666e
> --- /dev/null
> +++ b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> @@ -0,0 +1,318 @@
> +/*
> + *   BSD LICENSE
> + *
> + *   Copyright (C) IBM Corporation 2014.
> + *
> + *   Redistribution and use in source and binary forms, with or without
> + *   modification, are permitted provided that the following conditions
> + *   are met:
> + *
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above 
copyright
> + *       notice, this list of conditions and the following disclaimer 
in
> + *       the documentation and/or other materials provided with the
> + *       distribution.
> + *     * Neither the name of IBM Corporation nor the names of its
> + *       contributors may be used to endorse or promote products 
derived
> + *       from this software without specific prior written permission.
> + *
> + *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
> CONTRIBUTORS
> + *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
> NOT
> + *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
> FITNESS FOR
> + *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
> COPYRIGHT
> + *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
> INCIDENTAL,
> + *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> NOT
> + *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
> OF USE,
> + *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> ON ANY
> + *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 
TORT
> + *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
> THE USE
> + *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> DAMAGE.
> +*/
> +
> +/*
> + * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
> + * Copyright (c) 2008 Marcel Moolenaar
> + * Copyright (c) 2001 Benno Rice
> + * Copyright (c) 2001 David E. O'Brien
> + * Copyright (c) 1998 Doug Rabson
> + * All rights reserved.
> + */
> +
> +#ifndef _RTE_ATOMIC_H_
> +#error "don't include this file directly, please include generic 
<rte_atomic.h>"
> +#endif
> +
> +#ifndef _RTE_ATOMIC_ARCH_H_
> +#define _RTE_ATOMIC_ARCH_H_
> +
> +#include <stdint.h>
> +
> +/**
> + * General memory barrier.
> + *
> + * Guarantees that the LOAD and STORE operations generated before the
> + * barrier occur before the LOAD and STORE operations generated after.
> + */
> +#define               rte_arch_mb()  asm volatile("sync" : : : 
"memory")
> +
> +/**
> + * Write memory barrier.
> + *
> + * Guarantees that the STORE operations generated before the barrier
> + * occur before the STORE operations generated after.
> + */
> +#define               rte_arch_wmb() asm volatile("sync" : : : 
"memory")
> +
> +/**
> + * Read memory barrier.
> + *
> + * Guarantees that the LOAD operations generated before the barrier
> + * occur before the LOAD operations generated after.
> + */
> +#define               rte_arch_rmb() asm volatile("sync" : : : 
"memory")
> +
> +#define               rte_arch_compiler_barrier() do {        \
> +              asm volatile ("" : : : "memory");               \
> +} while(0)
> +
> +/*------------------------- 16 bit atomic operations
> +-------------------------*/
> +
> +/**
> + * The atomic counter structure.
> + */
> +typedef struct {
> +              volatile int16_t cnt; /**< An internal counter value. */ 
}
> +rte_atomic16_t;
> +
> +/**
> + * Atomic compare and set.
> + *
> + * (atomic) equivalent to:
> + *   if (*dst == exp)
> + *     *dst = src (all 16-bit words)
> + *
> + * @param dst
> + *   The destination location into which the value will be written.
> + * @param exp
> + *   The expected value.
> + * @param src
> + *   The new value.
> + * @return
> + *   Non-zero on success; 0 on failure.
> + */
> +static inline int
> +rte_arch_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t
> +src) {
> +              return __atomic_compare_exchange(dst, &exp, &src, 0,
> __ATOMIC_ACQUIRE,
> +__ATOMIC_ACQUIRE) ? 1 : 0; }
> +
> +/**
> + * Atomically increment a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic16_inc(rte_atomic16_t *v) {
> +              __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); }
> +
> +/**
> + * Atomically decrement a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic16_dec(rte_atomic16_t *v) {
> +              __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); }
> +
> +/**
> + * Atomically increment a 16-bit counter by one and test.
> + *
> + * Atomically increments the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the increment operation is 0; false 
otherwise.
> + */
> +static inline int rte_arch_atomic16_inc_and_test(rte_atomic16_t *v) {
> +              return (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) 
== 0); }
> +
> +/**
> + * Atomically decrement a 16-bit counter by one and test.
> + *
> + * Atomically decrements the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the decrement operation is 0; false 
otherwise.
> + */
> +static inline int rte_arch_atomic16_dec_and_test(rte_atomic16_t *v) {
> +              return (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) 
== 0); }
> +
> +/*------------------------- 32 bit atomic operations
> +-------------------------*/
> +
> +/**
> + * The atomic counter structure.
> + */
> +typedef struct {
> +              volatile int32_t cnt; /**< An internal counter value. */ 
}
> +rte_atomic32_t;
> +
> +/**
> + * Atomic compare and set.
> + *
> + * (atomic) equivalent to:
> + *   if (*dst == exp)
> + *     *dst = src (all 32-bit words)
> + *
> + * @param dst
> + *   The destination location into which the value will be written.
> + * @param exp
> + *   The expected value.
> + * @param src
> + *   The new value.
> + * @return
> + *   Non-zero on success; 0 on failure.
> + */
> +static inline int
> +rte_arch_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t
> +src) {
> +              unsigned int ret = 0;
> +
> +              asm volatile(
> +                                              "\tlwsync\n"
> +                                              "1:\tlwarx %[ret], 0, 
%[dst]\n"
> +                                              "cmplw %[exp], %[ret]\n"
> +                                              "bne 2f\n"
> +                                              "stwcx. %[src], 0, 
%[dst]\n"
> +                                              "bne- 1b\n"
> +                                              "li %[ret], 1\n"
> +                                              "b 3f\n"
> +                                              "2:\n"
> +                                              "stwcx. %[ret], 0, 
%[dst]\n"
> +                                              "li %[ret], 0\n"
> +                                              "3:\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret), "=m" 
(*dst)
> +                                              : [dst] "r" (dst), [exp] 
"r" (exp), [src] "r" (src), "m" (*dst)
> +                                              : "cc", "memory");
> +
> +              return ret;
> +}
> +
> +/**
> + * Atomically increment a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic32_inc(rte_atomic32_t *v) {
> +              int t;
> +
> +              asm volatile(
> +                                              "1: lwarx 
%[t],0,%[cnt]\n"
> +                                              "addic %[t],%[t],1\n"
> +                                              "stwcx. %[t],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              : [t] "=&r" (t), "=m" 
(v->cnt)
> +                                              : [cnt] "r" (&v->cnt), 
"m" (v->cnt)
> +                                              : "cc", "xer", "memory");
> +}
> +
> +/**
> + * Atomically decrement a counter by one.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + */
> +static inline void
> +rte_arch_atomic32_dec(rte_atomic32_t *v) {
> +              int t;
> +
> +              asm volatile(
> +                                              "1: lwarx 
%[t],0,%[cnt]\n"
> +                                              "addic %[t],%[t],-1\n"
> +                                              "stwcx. %[t],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              : [t] "=&r" (t), "=m" 
(v->cnt)
> +                                              : [cnt] "r" (&v->cnt), 
"m" (v->cnt)
> +                                              : "cc", "xer", "memory");
> +}
> +
> +/**
> + * Atomically increment a 32-bit counter by one and test.
> + *
> + * Atomically increments the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the increment operation is 0; false 
otherwise.
> + */
> +static inline int rte_arch_atomic32_inc_and_test(rte_atomic32_t *v) {
> +              int ret;
> +
> +              asm volatile(
> +                                              "\n\tlwsync\n"
> +                                              "1: lwarx 
%[ret],0,%[cnt]\n"
> +                                              "addic %[ret],%[ret],1\n"
> +                                              "stwcx. 
%[ret],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret)
> +                                              : [cnt] "r" (&v->cnt)
> +                                              : "cc", "xer", "memory");
> +
> +              return (ret == 0);
> +}
> +
> +/**
> + * Atomically decrement a 32-bit counter by one and test.
> + *
> + * Atomically decrements the atomic counter (v) by one and returns true
> +if
> + * the result is 0, or false in all other cases.
> + *
> + * @param v
> + *   A pointer to the atomic counter.
> + * @return
> + *   True if the result after the decrement operation is 0; false 
otherwise.
> + */
> +static inline int rte_arch_atomic32_dec_and_test(rte_atomic32_t *v) {
> +              int ret;
> +
> +              asm volatile(
> +                                              "\n\tlwsync\n"
> +                                              "1: lwarx 
%[ret],0,%[cnt]\n"
> +                                              "addic 
%[ret],%[ret],-1\n"
> +                                              "stwcx. 
%[ret],0,%[cnt]\n"
> +                                              "bne- 1b\n"
> +                                              "isync\n"
> +                                              : [ret] "=&r" (ret)
> +                                              : [cnt] "r" (&v->cnt)
> +                                              : "cc", "xer", "memory");
> +
> +              return (ret == 0);
> +}
> +
> +#endif /* _RTE_ATOMIC_ARCH_H_ */
> +
> --
> 1.7.1




^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 09/12] Remove iopl operation for IBM Power architecture
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 09/12] Remove iopl operation " Chao Zhu
@ 2014-10-06 22:03   ` Cyril Chemparathy
  2014-10-07 14:46     ` Ananyev, Konstantin
  0 siblings, 1 reply; 26+ messages in thread
From: Cyril Chemparathy @ 2014-10-06 22:03 UTC (permalink / raw)
  To: Chao Zhu, dev

On 9/26/2014 2:36 AM, Chao Zhu wrote:
> iopl() call is mostly for the i386 architecture. In Power architecture.
> It doesn't exist. This patch modified rte_eal_iopl_init() and make it
> return -1 on Power. This means rte_config.flags will not contain
> EAL_FLG_HIGH_IOPL flag on IBM Power architecture.

Since iopl() is an x86-only thing, shouldn't the code be conditional on 
defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) instead of below?

Better still, should we maybe break out an architecture specific init 
function?  This function could set iopl on x86, and possibly do other 
lowlevel init things on other architectures...

> Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> ---
>   lib/librte_eal/linuxapp/eal/eal.c |   11 +++++++++++
>   1 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/lib/librte_eal/linuxapp/eal/eal.c b/lib/librte_eal/linuxapp/eal/eal.c
> index 4869e7c..8cc1f21 100644
> --- a/lib/librte_eal/linuxapp/eal/eal.c
> +++ b/lib/librte_eal/linuxapp/eal/eal.c
> @@ -50,7 +50,10 @@
>   #include <errno.h>
>   #include <sys/mman.h>
>   #include <sys/queue.h>
> +/* Power architecture doesn't have this header file */
> +#ifndef RTE_ARCH_PPC_64
>   #include <sys/io.h>
> +#endif
>   
>   #include <rte_common.h>
>   #include <rte_debug.h>
> @@ -1019,11 +1022,19 @@ rte_eal_mcfg_complete(void)
>   
>   /*
>    * Request iopl privilege for all RPL, returns 0 on success
> + *
> + * Power architecture doesn't have iopl function, so this function
> + * return -1 on Power architecture, because this function is only used
> + * in rte_eal_init to add EAL_FLG_HIGH_IOPL to rte_config.flags.
>    */
>   static int
>   rte_eal_iopl_init(void)
>   {
> +#ifndef RTE_ARCH_PPC_64
>   	return iopl(HIGHEST_RPL);
> +#else
> +	return -1;
> +#endif
>   }
>   
>   /* Launch threads, called at application init(). */

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 09/12] Remove iopl operation for IBM Power architecture
  2014-10-06 22:03   ` Cyril Chemparathy
@ 2014-10-07 14:46     ` Ananyev, Konstantin
  2014-10-13  2:33       ` Chao CH Zhu
  0 siblings, 1 reply; 26+ messages in thread
From: Ananyev, Konstantin @ 2014-10-07 14:46 UTC (permalink / raw)
  To: Cyril Chemparathy, Chao Zhu, dev

> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Cyril Chemparathy
> Sent: Monday, October 06, 2014 11:04 PM
> To: Chao Zhu; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 09/12] Remove iopl operation for IBM Power architecture
> 
> On 9/26/2014 2:36 AM, Chao Zhu wrote:
> > iopl() call is mostly for the i386 architecture. In Power architecture.
> > It doesn't exist. This patch modified rte_eal_iopl_init() and make it
> > return -1 on Power. This means rte_config.flags will not contain
> > EAL_FLG_HIGH_IOPL flag on IBM Power architecture.
> 
> Since iopl() is an x86-only thing, shouldn't the code be conditional on
> defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) instead of below?
> 
> Better still, should we maybe break out an architecture specific init
> function?  This function could set iopl on x86, and possibly do other
> lowlevel init things on other architectures...

Yep, that sounds like a good way to me too. 

> 
> > Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> > ---
> >   lib/librte_eal/linuxapp/eal/eal.c |   11 +++++++++++
> >   1 files changed, 11 insertions(+), 0 deletions(-)
> >
> > diff --git a/lib/librte_eal/linuxapp/eal/eal.c b/lib/librte_eal/linuxapp/eal/eal.c
> > index 4869e7c..8cc1f21 100644
> > --- a/lib/librte_eal/linuxapp/eal/eal.c
> > +++ b/lib/librte_eal/linuxapp/eal/eal.c
> > @@ -50,7 +50,10 @@
> >   #include <errno.h>
> >   #include <sys/mman.h>
> >   #include <sys/queue.h>
> > +/* Power architecture doesn't have this header file */
> > +#ifndef RTE_ARCH_PPC_64
> >   #include <sys/io.h>
> > +#endif
> >
> >   #include <rte_common.h>
> >   #include <rte_debug.h>
> > @@ -1019,11 +1022,19 @@ rte_eal_mcfg_complete(void)
> >
> >   /*
> >    * Request iopl privilege for all RPL, returns 0 on success
> > + *
> > + * Power architecture doesn't have iopl function, so this function
> > + * return -1 on Power architecture, because this function is only used
> > + * in rte_eal_init to add EAL_FLG_HIGH_IOPL to rte_config.flags.
> >    */
> >   static int
> >   rte_eal_iopl_init(void)
> >   {
> > +#ifndef RTE_ARCH_PPC_64
> >   	return iopl(HIGHEST_RPL);
> > +#else
> > +	return -1;
> > +#endif
> >   }
> >
> >   /* Launch threads, called at application init(). */

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 09/12] Remove iopl operation for IBM Power architecture
  2014-10-07 14:46     ` Ananyev, Konstantin
@ 2014-10-13  2:33       ` Chao CH Zhu
  0 siblings, 0 replies; 26+ messages in thread
From: Chao CH Zhu @ 2014-10-13  2:33 UTC (permalink / raw)
  To: Ananyev, Konstantin; +Cc: dev

OK. I'll update the patches.
Thanks for your comments!

Best Regards!
------------------------------
Chao Zhu 




From:   "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To:     Cyril Chemparathy <cchemparathy@tilera.com>, Chao CH 
Zhu/China/IBM@IBMCN, "dev@dpdk.org" <dev@dpdk.org>
Date:   2014/10/07 22:45
Subject:        RE: [dpdk-dev] [PATCH 09/12] Remove iopl operation for IBM 
Power architecture



> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Cyril Chemparathy
> Sent: Monday, October 06, 2014 11:04 PM
> To: Chao Zhu; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 09/12] Remove iopl operation for IBM 
Power architecture
> 
> On 9/26/2014 2:36 AM, Chao Zhu wrote:
> > iopl() call is mostly for the i386 architecture. In Power 
architecture.
> > It doesn't exist. This patch modified rte_eal_iopl_init() and make it
> > return -1 on Power. This means rte_config.flags will not contain
> > EAL_FLG_HIGH_IOPL flag on IBM Power architecture.
> 
> Since iopl() is an x86-only thing, shouldn't the code be conditional on
> defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) instead of below?
> 
> Better still, should we maybe break out an architecture specific init
> function?  This function could set iopl on x86, and possibly do other
> lowlevel init things on other architectures...

Yep, that sounds like a good way to me too. 

> 
> > Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> > ---
> >   lib/librte_eal/linuxapp/eal/eal.c |   11 +++++++++++
> >   1 files changed, 11 insertions(+), 0 deletions(-)
> >
> > diff --git a/lib/librte_eal/linuxapp/eal/eal.c 
b/lib/librte_eal/linuxapp/eal/eal.c
> > index 4869e7c..8cc1f21 100644
> > --- a/lib/librte_eal/linuxapp/eal/eal.c
> > +++ b/lib/librte_eal/linuxapp/eal/eal.c
> > @@ -50,7 +50,10 @@
> >   #include <errno.h>
> >   #include <sys/mman.h>
> >   #include <sys/queue.h>
> > +/* Power architecture doesn't have this header file */
> > +#ifndef RTE_ARCH_PPC_64
> >   #include <sys/io.h>
> > +#endif
> >
> >   #include <rte_common.h>
> >   #include <rte_debug.h>
> > @@ -1019,11 +1022,19 @@ rte_eal_mcfg_complete(void)
> >
> >   /*
> >    * Request iopl privilege for all RPL, returns 0 on success
> > + *
> > + * Power architecture doesn't have iopl function, so this function
> > + * return -1 on Power architecture, because this function is only 
used
> > + * in rte_eal_init to add EAL_FLG_HIGH_IOPL to rte_config.flags.
> >    */
> >   static int
> >   rte_eal_iopl_init(void)
> >   {
> > +#ifndef RTE_ARCH_PPC_64
> >              return iopl(HIGHEST_RPL);
> > +#else
> > +            return -1;
> > +#endif
> >   }
> >
> >   /* Launch threads, called at application init(). */

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 02/12] Add atomic operations " Chao Zhu
  2014-09-29  6:16   ` Hemant
@ 2014-10-16  0:39   ` Ananyev, Konstantin
  2014-10-16  3:14     ` Chao CH Zhu
  1 sibling, 1 reply; 26+ messages in thread
From: Ananyev, Konstantin @ 2014-10-16  0:39 UTC (permalink / raw)
  To: Chao Zhu, dev


Hi,

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu
> Sent: Friday, September 26, 2014 10:36 AM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
> 
> The atomic operations implemented with assembly code in DPDK only
> support x86. This patch add architecture specific atomic operations for
> IBM Power architecture.
> 
> Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> ---
>  .../common/include/powerpc/arch/rte_atomic.h       |  387 ++++++++++++++++++++
>  .../common/include/powerpc/arch/rte_atomic_arch.h  |  318 ++++++++++++++++
>  2 files changed, 705 insertions(+), 0 deletions(-)
>  create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
>  create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> 
...
> +
> diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> new file mode 100644
> index 0000000..fe5666e
> --- /dev/null
> +
...
>+#define	rte_arch_rmb() asm volatile("sync" : : : "memory")
>+
> +#define	rte_arch_compiler_barrier() do {		\
> +	asm volatile ("" : : : "memory");	\
> +} while(0)

I don't know much about PPC architecture, but as I remember it uses a  weakly-ordering memory model.
Is that correct?
If so, then you probably need rte_arch_compiler_barrier() to be "sync" instruction (like mb()s above) .
The reason is that IA has much stronger memory ordering model and there are a lot of places in the code where it implies that  ordering.
For example - ring enqueue/dequeue functions.	

Konstantin

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
  2014-10-16  0:39   ` Ananyev, Konstantin
@ 2014-10-16  3:14     ` Chao CH Zhu
  2014-10-16  9:42       ` Richardson, Bruce
       [not found]       ` <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com>
  0 siblings, 2 replies; 26+ messages in thread
From: Chao CH Zhu @ 2014-10-16  3:14 UTC (permalink / raw)
  To: Ananyev, Konstantin; +Cc: dev

Konstantin,

In my understanding, compiler barrier is a kind of software barrier which 
prevents the compiler from moving memory accesses across the barrier. This 
should be architecture-independent. And the "sync" instruction is a 
hardware barrier which depends on PowerPC architecture. So I think the 
compiler barrier should be the same on x86 and PowerPC. Any comments? 
Please correct me if I was wrong.

Thanks a lot! 
 
Best Regards!
------------------------------
Chao Zhu 




From:   "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To:     Chao CH Zhu/China/IBM@IBMCN, "dev@dpdk.org" <dev@dpdk.org>
Date:   2014/10/16 08:38
Subject:        RE: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM 
Power   architecture




Hi,

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu
> Sent: Friday, September 26, 2014 10:36 AM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power 
architecture
> 
> The atomic operations implemented with assembly code in DPDK only
> support x86. This patch add architecture specific atomic operations for
> IBM Power architecture.
> 
> Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> ---
>  .../common/include/powerpc/arch/rte_atomic.h       |  387 
++++++++++++++++++++
>  .../common/include/powerpc/arch/rte_atomic_arch.h  |  318 
++++++++++++++++
>  2 files changed, 705 insertions(+), 0 deletions(-)
>  create mode 100644 
lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
>  create mode 100644 
lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> 
...
> +
> diff --git 
a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> new file mode 100644
> index 0000000..fe5666e
> --- /dev/null
> +
...
>+#define                rte_arch_rmb() asm volatile("sync" : : : 
"memory")
>+
> +#define               rte_arch_compiler_barrier() do {        \
> +              asm volatile ("" : : : "memory");               \
> +} while(0)

I don't know much about PPC architecture, but as I remember it uses a 
weakly-ordering memory model.
Is that correct?
If so, then you probably need rte_arch_compiler_barrier() to be "sync" 
instruction (like mb()s above) .
The reason is that IA has much stronger memory ordering model and there 
are a lot of places in the code where it implies that  ordering.
For example - ring enqueue/dequeue functions. 

Konstantin

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
  2014-10-16  3:14     ` Chao CH Zhu
@ 2014-10-16  9:42       ` Richardson, Bruce
  2014-10-16 11:04         ` Ananyev, Konstantin
       [not found]       ` <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com>
  1 sibling, 1 reply; 26+ messages in thread
From: Richardson, Bruce @ 2014-10-16  9:42 UTC (permalink / raw)
  To: Chao CH Zhu, Ananyev, Konstantin; +Cc: dev

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao CH Zhu
> Sent: Thursday, October 16, 2014 4:14 AM
> To: Ananyev, Konstantin
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power
> architecture
> 
> Konstantin,
> 
> In my understanding, compiler barrier is a kind of software barrier which
> prevents the compiler from moving memory accesses across the barrier. This
> should be architecture-independent. And the "sync" instruction is a
> hardware barrier which depends on PowerPC architecture. So I think the
> compiler barrier should be the same on x86 and PowerPC. Any comments?
> Please correct me if I was wrong.
> 
I would agree with that assessment, as far as it goes, in that a compiler barrier is going to be the same on both architectures. However, we also need to start thinking about actual use cases - how to we specify the barriers in a piece of code where we need a full memory barrier on PPC and only a compiler barrier on IA? 
My suggestion would be to do first as you propose and have proper primitives for the different barrier types defined correctly for each platform - with the compiler barrier being, presumably, common across each one. Then, as a second step, we probably need to look at defining "logical" barrier types (for want of a better term) that can then be used in the code and which would be different across platforms.

Does this make sense to do this way? Is it the best solution? Do we want to define the basic primitives or are we only ever likely to need the logical barrier types?

/Bruce

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
       [not found]       ` <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com>
@ 2014-10-16 10:59         ` Ananyev, Konstantin
  0 siblings, 0 replies; 26+ messages in thread
From: Ananyev, Konstantin @ 2014-10-16 10:59 UTC (permalink / raw)
  To: dev



> 
> 
> From: Chao CH Zhu [mailto:bjzhuc@cn.ibm.com]
> Sent: Thursday, October 16, 2014 4:14 AM
> To: Ananyev, Konstantin
> Cc: dev@dpdk.org
> Subject: RE: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
> 
> Konstantin,
> 
> In my understanding, compiler barrier is a kind of software barrier which prevents the compiler from moving memory accesses across
> the barrier.

Yes, compiler_barrier() right now only guarantees that the compiler wouldn't reorder instructions across it while emitting the code.

> This should be architecture-independent. And the "sync" instruction is a hardware barrier which depends on PowerPC
> architecture.

I understand what "sync" does.

>So I think the compiler barrier should be the same on x86 and PowerPC. Any comments? Please correct me if I was
> wrong.

The thing is that current DPDK code will not work correctly on system with weak memory ordering -
IA has quite strict memory ordering model and there is a code inside DPDK that relies on the fact that CPU would follow that model.
For such places in the code - compiler barrier is enough for IA, but is not enough for PPC. 

Do you worry about the names here- compiler barrier will become a HW one? :)?
In that case what you probably can do:
Create a new architecture dependent macro: rte_barrier().
That  would expand into rte_compiler_barrier() for IA and to rte_mb() for PPC.
Got through all references of rte_compiler_barrier() inside DPDK and replace it with rte_barrier().

Konstantin

> 
> Thanks a lot!
> 
> Best Regards!
> ------------------------------
> Chao Zhu
> 
> 
> 
> 
> From:        "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
> To:        Chao CH Zhu/China/IBM@IBMCN, "dev@dpdk.org" <dev@dpdk.org>
> Date:        2014/10/16 08:38
> Subject:        RE: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power        architecture
> ________________________________________
> 
> 
> 
> 
> Hi,
> 
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu
> > Sent: Friday, September 26, 2014 10:36 AM
> > To: dev@dpdk.org
> > Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
> >
> > The atomic operations implemented with assembly code in DPDK only
> > support x86. This patch add architecture specific atomic operations for
> > IBM Power architecture.
> >
> > Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
> > ---
> >  .../common/include/powerpc/arch/rte_atomic.h       |  387 ++++++++++++++++++++
> >  .../common/include/powerpc/arch/rte_atomic_arch.h  |  318 ++++++++++++++++
> >  2 files changed, 705 insertions(+), 0 deletions(-)
> >  create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic.h
> >  create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> >
> ...
> > +
> > diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> > b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h
> > new file mode 100644
> > index 0000000..fe5666e
> > --- /dev/null
> > +
> ...
> >+#define                 rte_arch_rmb() asm volatile("sync" : : : "memory")
> >+
> > +#define                 rte_arch_compiler_barrier() do {                                  \
> > +                 asm volatile ("" : : : "memory");                 \
> > +} while(0)
> 
> I don't know much about PPC architecture, but as I remember it uses a  weakly-ordering memory model.
> Is that correct?
> If so, then you probably need rte_arch_compiler_barrier() to be "sync" instruction (like mb()s above) .
> The reason is that IA has much stronger memory ordering model and there are a lot of places in the code where it implies
> that  ordering.
> For example - ring enqueue/dequeue functions.
> 
> Konstantin

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
  2014-10-16  9:42       ` Richardson, Bruce
@ 2014-10-16 11:04         ` Ananyev, Konstantin
  0 siblings, 0 replies; 26+ messages in thread
From: Ananyev, Konstantin @ 2014-10-16 11:04 UTC (permalink / raw)
  To: Richardson, Bruce, Chao CH Zhu; +Cc: dev



> -----Original Message-----
> From: Richardson, Bruce
> Sent: Thursday, October 16, 2014 10:43 AM
> To: Chao CH Zhu; Ananyev, Konstantin
> Cc: dev@dpdk.org
> Subject: RE: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture
> 
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao CH Zhu
> > Sent: Thursday, October 16, 2014 4:14 AM
> > To: Ananyev, Konstantin
> > Cc: dev@dpdk.org
> > Subject: Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power
> > architecture
> >
> > Konstantin,
> >
> > In my understanding, compiler barrier is a kind of software barrier which
> > prevents the compiler from moving memory accesses across the barrier. This
> > should be architecture-independent. And the "sync" instruction is a
> > hardware barrier which depends on PowerPC architecture. So I think the
> > compiler barrier should be the same on x86 and PowerPC. Any comments?
> > Please correct me if I was wrong.
> >
> I would agree with that assessment, as far as it goes, in that a compiler barrier is going to be the same on both architectures. However,
> we also need to start thinking about actual use cases - how to we specify the barriers in a piece of code where we need a full memory
> barrier on PPC and only a compiler barrier on IA?
> My suggestion would be to do first as you propose and have proper primitives for the different barrier types defined correctly for
> each platform - with the compiler barrier being, presumably, common across each one. Then, as a second step, we probably need to
> look at defining "logical" barrier types (for want of a better term) that can then be used in the code and which would be different
> across platforms.

Yeh, as I said in other mail, what we probably can do:

Create a new architecture dependent macro: rte_barrier().
That  would expand into rte_compiler_barrier() for IA and to rte_mb() for PPC.
Got through all references of rte_compiler_barrier() inside DPDK and replace it with rte_barrier().

BTW, for my own curiosity:
Is there any good use for compiler_barrier() on systems with weakly ordered memory model? 

> 
> Does this make sense to do this way? Is it the best solution? Do we want to define the basic primitives or are we only ever likely to
> need the logical barrier types?
> 
> /Bruce

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture
  2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
                   ` (11 preceding siblings ...)
  2014-09-26  9:36 ` [dpdk-dev] [PATCH 12/12] Add memory support for IBM Power Architecture Chao Zhu
@ 2014-11-13 10:24 ` Thomas Monjalon
  2014-11-13 10:31   ` Chao Zhu
  12 siblings, 1 reply; 26+ messages in thread
From: Thomas Monjalon @ 2014-11-13 10:24 UTC (permalink / raw)
  To: Chao Zhu; +Cc: dev

Hi Chao,

2014-09-26 05:36, Chao Zhu:
> The set of patches add IBM Power architecture to the DPDK. It adds the required support to the
> EAL library. This set of patches doesn't support full function on Power processors. Many functions
> are turned off in configuratidon. More patches will be added continuesly.
> 
> Chao Zhu (12):
>   Add compiling definations for IBM Power architecture
>   Add atomic operations for IBM Power architecture
>   Add byte order operations for IBM Power architecture
>   Add CPU cycle operations for IBM Power architecture
>   Add prefetch operation for IBM Power architecture
>   Add spinlock operation for IBM Power architecture
>   Add vector memcpy for IBM Power architecture
>   Add CPU flag checking for IBM Power architecture
>   Remove iopl operation for IBM Power architecture
>   Add cache size define for IBM Power Architecture
>   Add huge page sizes for IBM Power architecture
>   Add memory support for IBM Power Architecture

Could you share the status of the rework of these patches?
Maybe that some parts could enter in 1.8 as a preview.

-- 
Thomas

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture
  2014-11-13 10:24 ` [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Thomas Monjalon
@ 2014-11-13 10:31   ` Chao Zhu
  0 siblings, 0 replies; 26+ messages in thread
From: Chao Zhu @ 2014-11-13 10:31 UTC (permalink / raw)
  To: Thomas Monjalon, Chao Zhu; +Cc: dev

Thomas,

Sorry for the delay. I'll push the updated patches to the mail list 
before next Monday.
Thanks a lot!

Best Regards!
------------------------------
Chao Zhu

On 2014/11/13 18:24, Thomas Monjalon wrote:
> Hi Chao,
>
> 2014-09-26 05:36, Chao Zhu:
>> The set of patches add IBM Power architecture to the DPDK. It adds the required support to the
>> EAL library. This set of patches doesn't support full function on Power processors. Many functions
>> are turned off in configuratidon. More patches will be added continuesly.
>>
>> Chao Zhu (12):
>>    Add compiling definations for IBM Power architecture
>>    Add atomic operations for IBM Power architecture
>>    Add byte order operations for IBM Power architecture
>>    Add CPU cycle operations for IBM Power architecture
>>    Add prefetch operation for IBM Power architecture
>>    Add spinlock operation for IBM Power architecture
>>    Add vector memcpy for IBM Power architecture
>>    Add CPU flag checking for IBM Power architecture
>>    Remove iopl operation for IBM Power architecture
>>    Add cache size define for IBM Power Architecture
>>    Add huge page sizes for IBM Power architecture
>>    Add memory support for IBM Power Architecture
> Could you share the status of the rework of these patches?
> Maybe that some parts could enter in 1.8 as a preview.
>

^ permalink raw reply	[flat|nested] 26+ messages in thread

end of thread, other threads:[~2014-11-13 10:20 UTC | newest]

Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-09-26  9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 01/12] Add compiling definations for IBM " Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 02/12] Add atomic operations " Chao Zhu
2014-09-29  6:16   ` Hemant
2014-09-29  6:41     ` Chao CH Zhu
2014-10-16  0:39   ` Ananyev, Konstantin
2014-10-16  3:14     ` Chao CH Zhu
2014-10-16  9:42       ` Richardson, Bruce
2014-10-16 11:04         ` Ananyev, Konstantin
     [not found]       ` <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com>
2014-10-16 10:59         ` Ananyev, Konstantin
2014-09-26  9:36 ` [dpdk-dev] [PATCH 03/12] Add byte order " Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 04/12] Add CPU cycle " Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 05/12] Add prefetch operation " Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 06/12] Add spinlock " Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 07/12] Add vector memcpy " Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 08/12] Add CPU flag checking " Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 09/12] Remove iopl operation " Chao Zhu
2014-10-06 22:03   ` Cyril Chemparathy
2014-10-07 14:46     ` Ananyev, Konstantin
2014-10-13  2:33       ` Chao CH Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture Chao Zhu
2014-09-29  6:21   ` Hemant
2014-09-26  9:36 ` [dpdk-dev] [PATCH 11/12] Add huge page sizes for IBM Power architecture Chao Zhu
2014-09-26  9:36 ` [dpdk-dev] [PATCH 12/12] Add memory support for IBM Power Architecture Chao Zhu
2014-11-13 10:24 ` [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Thomas Monjalon
2014-11-13 10:31   ` Chao Zhu

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