* [dpdk-dev] [PATCH 00/22] Add DLB2 PMD
@ 2020-09-11 20:26 Timothy McDaniel
2020-09-11 20:26 ` [dpdk-dev] [PATCH 01/22] event/dlb2: add meson build infrastructure Timothy McDaniel
` (23 more replies)
0 siblings, 24 replies; 366+ messages in thread
From: Timothy McDaniel @ 2020-09-11 20:26 UTC (permalink / raw)
Cc: dev, erik.g.carrillo, gage.eads, harry.van.haaren, jerinj
The following patch series adds support for a new eventdev PMD. The DLB2
PMD adds support for the Intel Dynamic Load Balancer 2.0 (DLB2)
hardware.
The DLB2 is a PCIe device that provides load-balanced, prioritized
scheduling of core-to-core communication. The device consists of
queues and arbiters that connect producer and consumer cores, and
implements load-balanced queueing features including:
- Lock-free multi-producer/multi-consumer operation.
- Multiple priority levels for varying traffic types.
- 'Direct' traffic (i.e. multi-producer/single-consumer)
- Simple unordered load-balanced distribution.
- Atomic lock-free load balancing across multiple consumers.
- Queue element reordering feature allowing ordered load-balanced
distribution.
The DLB2 hardware supports both load balanced and directed ports and
queues. Unlike other eventdev devices already in the repo, not all
DLB2 ports and queues are equally capable. In particular, directed
ports are limited to a single link, and must be connected to a
directed queue. Additionally, even though LDB ports may link multiple queues,
the number of queues that may be linked is limited by hardware.
While reviewing the code, please be aware that this PMD has full
control over the DLB2 hardware. Intel will be extending the DLB2 PMD
in the future (not as part of this first series) with a mode that we
refer to as the bifurcated PMD. The bifurcated PMD communicates with a
kernel driver to configure the device, ports, and queues, and memory
maps device MMIO so datapath operations occur purely in user-space.
Note that the DLB2 hardware is a successor of the DLB hardware, and
as such is structured similarly, both in terms of code layout and
implementation.
The framework to support both the PF PMD and bifurcated PMD exists in
this patchset, and is why the iface.[ch] layer is present.
Depends-on: patch-77466 ("eventdev: add PCI probe named convenience function")
Depends-on: series-12160 ("Eventdev ABI changes")
Depends-on: patch-77460 ("eal: add umonitor umwait to x86 cpuflags")
Timothy McDaniel (22):
event/dlb2: add meson build infrastructure
event/dlb2: add dynamic logging
event/dlb2: add private data structures and constants
event/dlb2: add definitions shared with LKM or shared code
event/dlb2: add inline functions
event/dlb2: add probe
event/dlb2: add xstats
event/dlb2: add infos get and configure
event/dlb2: add queue and port default conf
event/dlb2: add queue setup
event/dlb2: add port setup
event/dlb2: add port link
event/dlb2: add port unlink and port unlinks in progress
event/dlb2: add eventdev start
event/dlb2: add enqueue and its burst variants
event/dlb2: add dequeue and its burst variants
event/dlb2: add eventdev stop and close
event/dlb2: add PMD's token pop public interface
event/dlb2: add PMD self-tests
event/dlb2: add queue and port release
event/dlb2: add timeout ticks entry point
doc: add new DLB2 eventdev driver to relnotes
app/test/test_eventdev.c | 9 +
config/rte_config.h | 7 +
doc/guides/rel_notes/release_20_11.rst | 5 +
drivers/event/dlb2/dlb2.c | 4046 ++++++++++++++
drivers/event/dlb2/dlb2_iface.c | 88 +
drivers/event/dlb2/dlb2_iface.h | 75 +
drivers/event/dlb2/dlb2_inline_fns.h | 85 +
drivers/event/dlb2/dlb2_log.h | 25 +
drivers/event/dlb2/dlb2_priv.h | 619 +++
drivers/event/dlb2/dlb2_selftest.c | 1570 ++++++
drivers/event/dlb2/dlb2_user.h | 883 +++
drivers/event/dlb2/dlb2_xstats.c | 1269 +++++
drivers/event/dlb2/meson.build | 16 +
drivers/event/dlb2/pf/base/dlb2_hw_types.h | 367 ++
drivers/event/dlb2/pf/base/dlb2_mbox.h | 596 ++
drivers/event/dlb2/pf/base/dlb2_osdep.h | 248 +
drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h | 447 ++
drivers/event/dlb2/pf/base/dlb2_osdep_list.h | 131 +
drivers/event/dlb2/pf/base/dlb2_osdep_types.h | 31 +
drivers/event/dlb2/pf/base/dlb2_regs.h | 2527 +++++++++
drivers/event/dlb2/pf/base/dlb2_resource.c | 6023 +++++++++++++++++++++
drivers/event/dlb2/pf/base/dlb2_resource.h | 1913 +++++++
drivers/event/dlb2/pf/dlb2_main.c | 692 +++
drivers/event/dlb2/pf/dlb2_main.h | 107 +
drivers/event/dlb2/pf/dlb2_pf.c | 734 +++
drivers/event/dlb2/rte_pmd_dlb2.c | 39 +
drivers/event/dlb2/rte_pmd_dlb2.h | 59 +
drivers/event/dlb2/rte_pmd_dlb2_event_version.map | 9 +
drivers/event/meson.build | 4 +
29 files changed, 22624 insertions(+)
create mode 100644 drivers/event/dlb2/dlb2.c
create mode 100644 drivers/event/dlb2/dlb2_iface.c
create mode 100644 drivers/event/dlb2/dlb2_iface.h
create mode 100644 drivers/event/dlb2/dlb2_inline_fns.h
create mode 100644 drivers/event/dlb2/dlb2_log.h
create mode 100644 drivers/event/dlb2/dlb2_priv.h
create mode 100644 drivers/event/dlb2/dlb2_selftest.c
create mode 100644 drivers/event/dlb2/dlb2_user.h
create mode 100644 drivers/event/dlb2/dlb2_xstats.c
create mode 100644 drivers/event/dlb2/meson.build
create mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types.h
create mode 100644 drivers/event/dlb2/pf/base/dlb2_mbox.h
create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep.h
create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h
create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep_list.h
create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep_types.h
create mode 100644 drivers/event/dlb2/pf/base/dlb2_regs.h
create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource.c
create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource.h
create mode 100644 drivers/event/dlb2/pf/dlb2_main.c
create mode 100644 drivers/event/dlb2/pf/dlb2_main.h
create mode 100644 drivers/event/dlb2/pf/dlb2_pf.c
create mode 100644 drivers/event/dlb2/rte_pmd_dlb2.c
create mode 100644 drivers/event/dlb2/rte_pmd_dlb2.h
create mode 100644 drivers/event/dlb2/rte_pmd_dlb2_event_version.map
--
2.6.4
^ permalink raw reply [flat|nested] 366+ messages in thread
* [dpdk-dev] [PATCH 01/22] event/dlb2: add meson build infrastructure
2020-09-11 20:26 [dpdk-dev] [PATCH 00/22] Add DLB2 PMD Timothy McDaniel
@ 2020-09-11 20:26 ` Timothy McDaniel
2020-10-06 15:58 ` Eads, Gage
` (3 more replies)
2020-09-11 20:26 ` [dpdk-dev] [PATCH 02/22] event/dlb2: add dynamic logging Timothy McDaniel
` (22 subsequent siblings)
23 siblings, 4 replies; 366+ messages in thread
From: Timothy McDaniel @ 2020-09-11 20:26 UTC (permalink / raw)
To: Bruce Richardson, Ray Kinsella, Neil Horman
Cc: dev, erik.g.carrillo, gage.eads, harry.van.haaren, jerinj
Adds the meson build infrastructure, which includes
compile-time constants in rte_config.h. DLB2 is
only supported on Linux X86 platforms at this time.
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
config/rte_config.h | 7 +++++++
drivers/event/dlb2/meson.build | 7 +++++++
drivers/event/dlb2/rte_pmd_dlb2_event_version.map | 3 +++
drivers/event/meson.build | 4 ++++
4 files changed, 21 insertions(+)
create mode 100644 drivers/event/dlb2/meson.build
create mode 100644 drivers/event/dlb2/rte_pmd_dlb2_event_version.map
diff --git a/config/rte_config.h b/config/rte_config.h
index 0bae630..fd1b3c3 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -131,4 +131,11 @@
/* QEDE PMD defines */
#define RTE_LIBRTE_QEDE_FW ""
+/* DLB2 defines */
+#define RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL 1000
+#define RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE 0
+#undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
+#define RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA 32
+#define RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH 256
+
#endif /* _RTE_CONFIG_H_ */
diff --git a/drivers/event/dlb2/meson.build b/drivers/event/dlb2/meson.build
new file mode 100644
index 0000000..d4fd39f
--- /dev/null
+++ b/drivers/event/dlb2/meson.build
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019-2020 Intel Corporation
+
+sources = files(
+)
+
+deps += ['mbuf', 'mempool', 'ring', 'bus_vdev', 'pci', 'bus_pci']
diff --git a/drivers/event/dlb2/rte_pmd_dlb2_event_version.map b/drivers/event/dlb2/rte_pmd_dlb2_event_version.map
new file mode 100644
index 0000000..299ae63
--- /dev/null
+++ b/drivers/event/dlb2/rte_pmd_dlb2_event_version.map
@@ -0,0 +1,3 @@
+DPDK_21.0 {
+ local: *;
+};
diff --git a/drivers/event/meson.build b/drivers/event/meson.build
index ebe76a7..f73fcb9 100644
--- a/drivers/event/meson.build
+++ b/drivers/event/meson.build
@@ -10,6 +10,10 @@ if not (toolchain == 'gcc' and cc.version().version_compare('<4.8.6') and
dpdk_conf.has('RTE_ARCH_ARM64'))
drivers += 'octeontx'
endif
+if ((dpdk_conf.has('RTE_ARCH_X86_64') or dpdk_conf.has('RTE_ARCH_X86')) and
+ is_linux)
+ drivers += 'dlb2'
+endif
std_deps = ['eventdev', 'kvargs']
config_flag_fmt = 'RTE_LIBRTE_@0@_EVENTDEV_PMD'
driver_name_fmt = 'rte_pmd_@0@_event'
--
2.6.4
^ permalink raw reply [flat|nested] 366+ messages in thread
* [dpdk-dev] [PATCH 02/22] event/dlb2: add dynamic logging
2020-09-11 20:26 [dpdk-dev] [PATCH 00/22] Add DLB2 PMD Timothy McDaniel
2020-09-11 20:26 ` [dpdk-dev] [PATCH 01/22] event/dlb2: add meson build infrastructure Timothy McDaniel
@ 2020-09-11 20:26 ` Timothy McDaniel
2020-10-06 16:52 ` Eads, Gage
2020-09-11 20:26 ` [dpdk-dev] [PATCH 03/22] event/dlb2: add private data structures and constants Timothy McDaniel
` (21 subsequent siblings)
23 siblings, 1 reply; 366+ messages in thread
From: Timothy McDaniel @ 2020-09-11 20:26 UTC (permalink / raw)
Cc: dev, erik.g.carrillo, gage.eads, harry.van.haaren, jerinj
This commit adds base support for dynamic logging.
The default log level is NOTICE. Dynamic logging
is used exclusively throughout this patchset.
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
drivers/event/dlb2/dlb2_log.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 drivers/event/dlb2/dlb2_log.h
diff --git a/drivers/event/dlb2/dlb2_log.h b/drivers/event/dlb2/dlb2_log.h
new file mode 100644
index 0000000..dc1481e
--- /dev/null
+++ b/drivers/event/dlb2/dlb2_log.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016-2020 Intel Corporation
+ */
+
+#ifndef _DLB2_EVDEV_LOG_H_
+#define _DLB2_EVDEV_LOG_H_
+
+extern int eventdev_dlb2_log_level;
+
+/* Dynamic logging */
+#define DLB2_LOG_IMPL(level, fmt, args...) \
+ rte_log(RTE_LOG_ ## level, eventdev_dlb2_log_level, "%s" fmt "\n", \
+ __func__, ##args)
+
+#define DLB2_LOG_INFO(fmt, args...) \
+ DLB2_LOG_IMPL(INFO, fmt, ## args)
+
+#define DLB2_LOG_ERR(fmt, args...) \
+ DLB2_LOG_IMPL(ERR, fmt, ## args)
+
+/* remove debug logs at compile time unless actually debugging */
+#define DLB2_LOG_DBG(fmt, args...) \
+ RTE_LOG_DP(DEBUG, PMD, fmt, ## args)
+
+#endif /* _DLB2_EVDEV_LOG_H_ */
--
2.6.4
^ permalink raw reply [flat|nested] 366+ messages in thread
* [dpdk-dev] [PATCH 03/22] event/dlb2: add private data structures and constants
2020-09-11 20:26 [dpdk-dev] [PATCH 00/22] Add DLB2 PMD Timothy McDaniel
2020-09-11 20:26 ` [dpdk-dev] [PATCH 01/22] event/dlb2: add meson build infrastructure Timothy McDaniel
2020-09-11 20:26 ` [dpdk-dev] [PATCH 02/22] event/dlb2: add dynamic logging Timothy McDaniel
@ 2020-09-11 20:26 ` Timothy McDaniel
2020-10-06 16:52 ` Eads, Gage
2020-10-07 16:14 ` Eads, Gage
2020-09-11 20:26 ` [dpdk-dev] [PATCH 04/22] event/dlb2: add definitions shared with LKM or shared code Timothy McDaniel
` (20 subsequent siblings)
23 siblings, 2 replies; 366+ messages in thread
From: Timothy McDaniel @ 2020-09-11 20:26 UTC (permalink / raw)
Cc: dev, erik.g.carrillo, gage.eads, harry.van.haaren, jerinj
The header file dlb2_priv.h is used internally by the PMD.
It include constants, macros for device resources,
structure definitions for hardware interfaces and
software state, and various forward-declarations.
The header file rte_pmd_dlb2.h will be exported in a
subsequent patch, but is included here due to a data
structure dependency.
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
drivers/event/dlb2/dlb2_priv.h | 614 ++++++++++++++++++++++++++++++++++++++
drivers/event/dlb2/rte_pmd_dlb2.h | 59 ++++
2 files changed, 673 insertions(+)
create mode 100644 drivers/event/dlb2/dlb2_priv.h
create mode 100644 drivers/event/dlb2/rte_pmd_dlb2.h
diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h
new file mode 100644
index 0000000..7bec835
--- /dev/null
+++ b/drivers/event/dlb2/dlb2_priv.h
@@ -0,0 +1,614 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016-2020 Intel Corporation
+ */
+
+#ifndef _DLB2_PRIV_H_
+#define _DLB2_PRIV_H_
+
+#include <emmintrin.h>
+#include <stdbool.h>
+
+#include <rte_eventdev.h>
+
+#include "rte_config.h"
+#include "dlb2_user.h"
+#include "dlb2_log.h"
+#include "rte_pmd_dlb2.h"
+
+#ifndef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
+#define DLB2_INC_STAT(_stat, _incr_val) ((_stat) += _incr_val)
+#else
+#define DLB2_INC_STAT(_stat, _incr_val)
+#endif
+
+#define EVDEV_DLB2_NAME_PMD dlb2_event
+
+/* command line arg strings */
+#define NUMA_NODE_ARG "numa_node"
+#define DLB2_MAX_NUM_EVENTS "max_num_events"
+#define DLB2_NUM_DIR_CREDITS "num_dir_credits"
+#define DEV_ID_ARG "dev_id"
+#define DLB2_DEFER_SCHED_ARG "defer_sched"
+#define DLB2_QID_DEPTH_THRESH_ARG "qid_depth_thresh"
+#define DLB2_COS_ARG "cos"
+
+/* Begin HW related defines and structs */
+
+#define DLB2_MAX_NUM_DOMAINS 32
+#define DLB2_MAX_NUM_VFS 16
+#define DLB2_MAX_NUM_LDB_QUEUES 32
+#define DLB2_MAX_NUM_LDB_PORTS 64
+#define DLB2_MAX_NUM_DIR_PORTS 64
+#define DLB2_MAX_NUM_DIR_QUEUES 64
+#define DLB2_MAX_NUM_FLOWS (64 * 1024)
+#define DLB2_MAX_NUM_LDB_CREDITS (8 * 1024)
+#define DLB2_MAX_NUM_DIR_CREDITS (2 * 1024)
+#define DLB2_MAX_NUM_LDB_CREDIT_POOLS 64
+#define DLB2_MAX_NUM_DIR_CREDIT_POOLS 64
+#define DLB2_MAX_NUM_HIST_LIST_ENTRIES 2048
+#define DLB2_MAX_NUM_AQOS_ENTRIES 2048
+#define DLB2_MAX_NUM_QIDS_PER_LDB_CQ 8
+#define DLB2_QID_PRIORITIES 8
+#define DLB2_MAX_DEVICE_PATH 32
+#define DLB2_MIN_DEQUEUE_TIMEOUT_NS 1
+/* Note: "- 1" here to support the timeout range check in eventdev_autotest */
+#define DLB2_MAX_DEQUEUE_TIMEOUT_NS (UINT32_MAX - 1)
+#define DLB2_SW_CREDIT_BATCH_SZ 32
+#define DLB2_NUM_SN_GROUPS 2
+#define DLB2_MAX_LDB_SN_ALLOC 1024
+#define DLB2_MAX_QUEUE_DEPTH_THRESHOLD 8191
+
+/* 2048 total hist list entries and 64 total ldb ports, which
+ * makes for 2048/64 == 32 hist list entries per port. However, CQ
+ * depth must be a power of 2 and must also be >= HIST LIST entries.
+ * As a result we just limit the maximum dequeue depth to 32.
+ */
+#define DLB2_MIN_CQ_DEPTH 1
+#define DLB2_MAX_CQ_DEPTH 32
+#define DLB2_MIN_HARDWARE_CQ_DEPTH 8
+#define DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT \
+ DLB2_MAX_CQ_DEPTH
+
+/*
+ * Static per queue/port provisioning values
+ */
+#define DLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE 64
+
+#define CQ_BASE(is_dir) ((is_dir) ? DLB2_DIR_CQ_BASE : DLB2_LDB_CQ_BASE)
+#define CQ_SIZE(is_dir) ((is_dir) ? DLB2_DIR_CQ_MAX_SIZE : \
+ DLB2_LDB_CQ_MAX_SIZE)
+#define PP_BASE(is_dir) ((is_dir) ? DLB2_DIR_PP_BASE : DLB2_LDB_PP_BASE)
+
+#define PAGE_SIZE (sysconf(_SC_PAGESIZE))
+
+#define DLB2_NUM_QES_PER_CACHE_LINE 4
+
+#define DLB2_MAX_ENQUEUE_DEPTH 64
+#define DLB2_MIN_ENQUEUE_DEPTH 4
+
+#define DLB2_NAME_SIZE 64
+
+#define DLB2_1K 1024
+#define DLB2_2K (2 * DLB2_1K)
+#define DLB2_4K (4 * DLB2_1K)
+#define DLB2_16K (16 * DLB2_1K)
+#define DLB2_32K (32 * DLB2_1K)
+#define DLB2_1MB (DLB2_1K * DLB2_1K)
+#define DLB2_16MB (16 * DLB2_1MB)
+
+/* Use the upper 3 bits of the event priority to select the DLB2 priority */
+#define EV_TO_DLB2_PRIO(x) ((x) >> 5)
+#define DLB2_TO_EV_PRIO(x) ((x) << 5)
+
+enum dlb2_hw_port_types {
+ DLB2_LDB_PORT,
+ DLB2_DIR_PORT,
+ DLB2_NUM_PORT_TYPES /* Must be last */
+};
+
+enum dlb2_hw_queue_types {
+ DLB2_LDB_QUEUE,
+ DLB2_DIR_QUEUE,
+ DLB2_NUM_QUEUE_TYPES /* Must be last */
+};
+
+#define PORT_TYPE(p) ((p)->is_directed ? DLB2_DIR_PORT : DLB2_LDB_PORT)
+
+/* Do not change - must match hardware! */
+enum dlb2_hw_sched_type {
+ DLB2_SCHED_ATOMIC = 0,
+ DLB2_SCHED_UNORDERED,
+ DLB2_SCHED_ORDERED,
+ DLB2_SCHED_DIRECTED,
+ /* DLB2_NUM_HW_SCHED_TYPES must be last */
+ DLB2_NUM_HW_SCHED_TYPES
+};
+
+/* TODO - these structs have been converted from qm - some fields may not be
+ * required
+ */
+
+struct dlb2_hw_rsrcs {
+ int32_t nb_events_limit;
+ uint32_t num_queues; /**> Total queues (lb + dir) */
+ uint32_t num_ldb_queues; /**> Number of available ldb queues */
+ uint32_t num_ldb_ports; /**< Number of load balanced ports */
+ uint32_t num_dir_ports; /**< Number of directed ports */
+ uint32_t num_ldb_credits; /**< Number of load balanced credits */
+ uint32_t num_dir_credits; /**< Number of directed credits */
+ uint32_t reorder_window_size; /**< Size of reorder window */
+};
+
+struct dlb2_hw_resource_info {
+ /**> Max resources that can be provided */
+ struct dlb2_hw_rsrcs hw_rsrc_max;
+ int num_sched_domains;
+ uint32_t socket_id;
+ /**> EAL flags passed to this QM instance, allowing the application to
+ * identify the pmd backend indicating hardware or software.
+ */
+ const char *eal_flags;
+};
+
+enum DLB2_ENQUEUE_TYPE {
+ /**>
+ * New : Used to inject a new packet into the QM.
+ */
+ DLB2_ENQ_NEW,
+ /**>
+ * Forward : Enqueues a packet, and
+ * - if atomic: release any lock it holds in the QM
+ * - if ordered: release the packet for egress re-ordering
+ */
+ DLB2_ENQ_FWD,
+ /**>
+ * Enqueue Drop : Release an inflight packet. Must be called with
+ * event == NULL. Used to drop a packet.
+ *
+ * Note that all packets dequeued from a load-balanced port must be
+ * released, either with DLB2_ENQ_DROP or DLB2_ENQ_FWD.
+ */
+ DLB2_ENQ_DROP,
+
+ /* marker for array sizing etc. */
+ _DLB2_NB_ENQ_TYPES
+};
+
+/* hw-specific format - do not change */
+
+struct dlb2_event_type {
+ uint8_t major:4;
+ uint8_t unused:4;
+ uint8_t sub;
+};
+
+union dlb2_opaque_data {
+ uint16_t opaque_data;
+ struct dlb2_event_type event_type;
+};
+
+struct dlb2_msg_info {
+ uint8_t qid;
+ uint8_t sched_type:2;
+ uint8_t priority:3;
+ uint8_t msg_type:3;
+};
+
+#define DLB2_NEW_CMD_BYTE 0x08
+#define DLB2_FWD_CMD_BYTE 0x0A
+#define DLB2_COMP_CMD_BYTE 0x02
+#define DLB2_POP_CMD_BYTE 0x01
+#define DLB2_NOOP_CMD_BYTE 0x00
+
+/* hw-specific format - do not change */
+struct dlb2_enqueue_qe {
+ uint64_t data;
+ /* Word 3 */
+ union dlb2_opaque_data u;
+ uint8_t qid;
+ uint8_t sched_type:2;
+ uint8_t priority:3;
+ uint8_t msg_type:3;
+ /* Word 4 */
+ uint16_t lock_id;
+ uint8_t meas_lat:1;
+ uint8_t rsvd1:2;
+ uint8_t no_dec:1;
+ uint8_t cmp_id:4;
+ union {
+ uint8_t cmd_byte;
+ struct {
+ uint8_t cq_token:1;
+ uint8_t qe_comp:1;
+ uint8_t qe_frag:1;
+ uint8_t qe_valid:1;
+ uint8_t rsvd3:1;
+ uint8_t error:1;
+ uint8_t rsvd:2;
+ };
+ };
+};
+
+/* hw-specific format - do not change */
+struct dlb2_cq_pop_qe {
+ uint64_t data;
+ union dlb2_opaque_data u;
+ uint8_t qid;
+ uint8_t sched_type:2;
+ uint8_t priority:3;
+ uint8_t msg_type:3;
+ uint16_t tokens:10;
+ uint16_t rsvd2:6;
+ uint8_t meas_lat:1;
+ uint8_t rsvd1:2;
+ uint8_t no_dec:1;
+ uint8_t cmp_id:4;
+ union {
+ uint8_t cmd_byte;
+ struct {
+ uint8_t cq_token:1;
+ uint8_t qe_comp:1;
+ uint8_t qe_frag:1;
+ uint8_t qe_valid:1;
+ uint8_t rsvd3:1;
+ uint8_t error:1;
+ uint8_t rsvd:2;
+ };
+ };
+};
+
+/* hw-specific format - do not change */
+struct dlb2_dequeue_qe {
+ uint64_t data;
+ union dlb2_opaque_data u;
+ uint8_t qid;
+ uint8_t sched_type:2;
+ uint8_t priority:3;
+ uint8_t msg_type:3;
+ uint16_t flow_id:16; /* was pp_id in v1 */
+ uint8_t debug;
+ uint8_t cq_gen:1;
+ uint8_t qid_depth:2; /* 2 bits in v2 */
+ uint8_t rsvd1:2;
+ uint8_t error:1;
+ uint8_t rsvd2:2;
+};
+
+union dlb2_port_config {
+ struct dlb2_create_ldb_port_args ldb;
+ struct dlb2_create_dir_port_args dir;
+};
+
+enum DLB2_PORT_STATE {
+ PORT_CLOSED,
+ PORT_STARTED,
+ PORT_STOPPED
+};
+
+enum dlb2_configuration_state {
+ /* The resource has not been configured */
+ DLB2_NOT_CONFIGURED,
+ /* The resource was configured, but the device was stopped */
+ DLB2_PREV_CONFIGURED,
+ /* The resource is currently configured */
+ DLB2_CONFIGURED
+};
+
+struct dlb2_port {
+ uint32_t id;
+ bool is_directed;
+ bool gen_bit;
+ uint16_t dir_credits;
+ uint32_t dequeue_depth;
+ enum dlb2_token_pop_mode token_pop_mode;
+ union dlb2_port_config cfg;
+ uint32_t *credit_pool[DLB2_NUM_QUEUE_TYPES]; /* use __atomic builtins */
+ uint16_t cached_ldb_credits;
+ uint16_t ldb_credits;
+ uint16_t cached_dir_credits;
+ bool int_armed;
+ uint16_t owed_tokens;
+ int16_t issued_releases;
+ int16_t token_pop_thresh;
+ int cq_depth;
+ uint16_t cq_idx;
+ uint16_t cq_idx_unmasked;
+ uint16_t cq_depth_mask;
+ uint16_t gen_bit_shift;
+ enum DLB2_PORT_STATE state;
+ enum dlb2_configuration_state config_state;
+ int num_mapped_qids;
+ uint8_t *qid_mappings;
+ struct dlb2_enqueue_qe *qe4; /* Cache line's worth of QEs (4) */
+ struct dlb2_enqueue_qe *int_arm_qe;
+ struct dlb2_cq_pop_qe *consume_qe;
+ struct dlb2_eventdev *dlb2; /* back ptr */
+ struct dlb2_eventdev_port *ev_port; /* back ptr */
+};
+
+/* Per-process per-port mmio and memory pointers */
+struct process_local_port_data {
+ uint64_t *pp_addr;
+ struct dlb2_dequeue_qe *cq_base;
+ bool mmaped;
+};
+
+struct dlb2_eventdev;
+
+struct dlb2_port_low_level_io_functions {
+ void (*pp_enqueue_four)(void *qe4,
+ void *pp_addr);
+};
+
+/* TODO - Optimize memory use and layout */
+struct dlb2_config {
+ int configured;
+ int reserved;
+ uint32_t num_ldb_credits;
+ uint32_t num_dir_credits;
+ struct dlb2_create_sched_domain_args resources;
+};
+
+enum dlb2_cos {
+ DLB2_COS_DEFAULT = -1,
+ DLB2_COS_0 = 0,
+ DLB2_COS_1,
+ DLB2_COS_2,
+ DLB2_COS_3
+};
+
+struct dlb2_hw_dev {
+ char device_name[DLB2_NAME_SIZE];
+ char device_path[DLB2_MAX_DEVICE_PATH];
+ int device_path_id;
+ struct dlb2_config cfg;
+ struct dlb2_hw_resource_info info;
+ void *pf_dev; /* opaque pointer to PF PMD dev (struct dlb2_dev) */
+ int device_id;
+ uint32_t domain_id;
+ int domain_id_valid;
+ enum dlb2_cos cos_id;
+ rte_spinlock_t resource_lock; /* for MP support */
+}; __rte_cache_aligned
+
+/* End HW related defines and structs */
+
+/* Begin DLB2 PMD Eventdev related defines and structs */
+
+#define DLB2_MAX_NUM_QUEUES \
+ (DLB2_MAX_NUM_DIR_QUEUES + DLB2_MAX_NUM_LDB_QUEUES)
+
+#define DLB2_MAX_NUM_PORTS (DLB2_MAX_NUM_DIR_PORTS + DLB2_MAX_NUM_LDB_PORTS)
+#define DLB2_MAX_INPUT_QUEUE_DEPTH 256
+
+/* Used for parsing dir ports/queues. */
+
+/* Note: eventdev currently is limited to 64 ports, but DLB hardware has 128
+ * directed ports/queues.
+ */
+struct dlb2_dir_resource_list {
+ int entries;
+ uint32_t id[DLB2_MAX_NUM_DIR_PORTS];
+};
+
+/** Structure to hold the queue to port link establishment attributes */
+
+struct dlb2_event_queue_link {
+ uint8_t queue_id;
+ uint8_t priority;
+ bool mapped;
+ bool valid;
+};
+
+struct dlb2_traffic_stats {
+ uint64_t rx_ok;
+ uint64_t rx_drop;
+ uint64_t rx_interrupt_wait;
+ uint64_t rx_umonitor_umwait;
+ uint64_t tx_ok;
+ uint64_t total_polls;
+ uint64_t zero_polls;
+ uint64_t tx_nospc_ldb_hw_credits;
+ uint64_t tx_nospc_dir_hw_credits;
+ uint64_t tx_nospc_inflight_max;
+ uint64_t tx_nospc_new_event_limit;
+ uint64_t tx_nospc_inflight_credits;
+};
+
+/* DLB2 HW sets the 2bit qid_depth in rx QEs based on the programmable depth
+ * threshold. The global default value in config/common_base (or rte_config.h)
+ * can be overridden on a per-qid basis using a vdev command line parameter.
+ * 3: depth > threshold
+ * 2: threshold >= depth > 3/4 threshold
+ * 1: 3/4 threshold >= depth > 1/2 threshold
+ * 0: depth <= 1/2 threshold.
+ */
+#define DLB2_QID_DEPTH_LE50 0
+#define DLB2_QID_DEPTH_GT50_LE75 1
+#define DLB2_QID_DEPTH_GT75_LE100 2
+#define DLB2_QID_DEPTH_GT100 3
+#define DLB2_NUM_QID_DEPTH_STAT_VALS 4 /* 2 bits */
+
+struct dlb2_queue_stats {
+ uint64_t enq_ok;
+ uint64_t qid_depth[DLB2_NUM_QID_DEPTH_STAT_VALS];
+};
+
+struct dlb2_port_stats {
+ struct dlb2_traffic_stats traffic;
+ uint64_t tx_op_cnt[4]; /* indexed by rte_event.op */
+ uint64_t tx_implicit_rel;
+ uint64_t tx_sched_cnt[DLB2_NUM_HW_SCHED_TYPES];
+ uint64_t tx_invalid;
+ uint64_t rx_sched_cnt[DLB2_NUM_HW_SCHED_TYPES];
+ uint64_t rx_sched_invalid;
+ struct dlb2_queue_stats queue[DLB2_MAX_NUM_QUEUES];
+};
+
+struct dlb2_eventdev_port {
+ struct dlb2_port qm_port; /* hw specific data structure */
+ struct rte_event_port_conf conf; /* user-supplied configuration */
+ uint16_t inflight_credits; /* num credits this port has right now */
+ uint16_t credit_update_quanta;
+ struct dlb2_eventdev *dlb2; /* backlink optimization */
+ struct dlb2_port_stats stats __rte_cache_aligned;
+ struct dlb2_event_queue_link link[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];
+ int num_links;
+ uint32_t id; /* port id */
+ /* num releases yet to be completed on this port.
+ * Only applies to load-balanced ports.
+ */
+ uint16_t outstanding_releases;
+ uint16_t inflight_max; /* app requested max inflights for this port */
+ /* setup_done is set when the event port is setup */
+ bool setup_done;
+ /* enq_configured is set when the qm port is created */
+ bool enq_configured;
+ uint8_t implicit_release; /* release events before dequeueing */
+} __rte_cache_aligned;
+
+struct dlb2_queue {
+ uint32_t num_qid_inflights; /* User config */
+ uint32_t num_atm_inflights; /* User config */
+ enum dlb2_configuration_state config_state;
+ int sched_type; /* LB queue only */
+ uint32_t id;
+ bool is_directed;
+};
+
+struct dlb2_eventdev_queue {
+ struct dlb2_queue qm_queue;
+ struct rte_event_queue_conf conf; /* User config */
+ int depth_threshold; /* use default if 0 */
+ uint32_t id;
+ bool setup_done;
+ uint8_t num_links;
+};
+
+struct dlb2_device_stats {
+ /* Device specific */
+};
+
+enum dlb2_run_state {
+ DLB2_RUN_STATE_STOPPED = 0,
+ DLB2_RUN_STATE_STOPPING,
+ DLB2_RUN_STATE_STARTING,
+ DLB2_RUN_STATE_STARTED
+};
+
+struct dlb2_eventdev {
+ struct dlb2_eventdev_port ev_ports[DLB2_MAX_NUM_PORTS];
+ struct dlb2_eventdev_queue ev_queues[DLB2_MAX_NUM_QUEUES];
+ uint8_t qm_ldb_to_ev_queue_id[DLB2_MAX_NUM_QUEUES];
+ uint8_t qm_dir_to_ev_queue_id[DLB2_MAX_NUM_QUEUES];
+ /* store num stats and offset of the stats for each queue */
+ uint16_t xstats_count_per_qid[DLB2_MAX_NUM_QUEUES];
+ uint16_t xstats_offset_for_qid[DLB2_MAX_NUM_QUEUES];
+ /* store num stats and offset of the stats for each port */
+ uint16_t xstats_count_per_port[DLB2_MAX_NUM_PORTS];
+ uint16_t xstats_offset_for_port[DLB2_MAX_NUM_PORTS];
+ struct dlb2_get_num_resources_args hw_rsrc_query_results;
+ uint32_t xstats_count_mode_queue;
+ struct dlb2_hw_dev qm_instance; /* strictly hw related */
+ uint64_t global_dequeue_wait_ticks;
+ struct dlb2_xstats_entry *xstats;
+ struct rte_eventdev *event_dev; /* backlink to dev */
+ uint32_t xstats_count_mode_dev;
+ uint32_t xstats_count_mode_port;
+ uint32_t xstats_count;
+ uint32_t inflights; /* use __atomic builtins */
+ uint32_t new_event_limit;
+ int max_num_events_override;
+ int num_dir_credits_override;
+ volatile enum dlb2_run_state run_state;
+ uint16_t num_dir_queues; /* total num of evdev dir queues requested */
+ uint16_t num_dir_credits;
+ uint16_t num_ldb_credits;
+ uint16_t num_queues; /* total queues */
+ uint16_t num_ldb_queues; /* total num of evdev ldb queues requested */
+ uint16_t num_ports; /* total num of evdev ports requested */
+ uint16_t num_ldb_ports; /* total num of ldb ports requested */
+ uint16_t num_dir_ports; /* total num of dir ports requested */
+ bool umwait_allowed;
+ bool global_dequeue_wait; /* Not using per dequeue wait if true */
+ bool defer_sched;
+ enum dlb2_cq_poll_modes poll_mode;
+ uint8_t revision;
+ bool configured;
+ uint16_t max_ldb_credits;
+ uint16_t max_dir_credits;
+
+ /* force hw credit pool counters into exclusive cache lines */
+
+ /* use __atomic builtins */ /* shared hw cred */
+ uint32_t ldb_credit_pool __rte_cache_aligned;
+ /* use __atomic builtins */ /* shared hw cred */
+ uint32_t dir_credit_pool __rte_cache_aligned;
+
+ /* Device stats */
+ struct dlb2_device_stats stats __rte_cache_aligned;
+};
+
+/* used for collecting and passing around the dev args */
+struct dlb2_qid_depth_thresholds {
+ int val[DLB2_MAX_NUM_QUEUES];
+};
+struct dlb2_devargs {
+ int socket_id;
+ int max_num_events;
+ int num_dir_credits_override;
+ int dev_id;
+ int defer_sched;
+ struct dlb2_qid_depth_thresholds qid_depth_thresholds;
+ enum dlb2_cos cos_id;
+};
+
+/* End Eventdev related defines and structs */
+
+/* Forwards for non-inlined functions */
+
+int dlb2_uninit(const char *name);
+
+void dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f);
+
+int dlb2_xstats_init(struct dlb2_eventdev *dlb2);
+
+void dlb2_xstats_uninit(struct dlb2_eventdev *dlb2);
+
+int dlb2_eventdev_xstats_get(const struct rte_eventdev *dev,
+ enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
+ const unsigned int ids[], uint64_t values[], unsigned int n);
+
+int dlb2_eventdev_xstats_get_names(const struct rte_eventdev *dev,
+ enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
+ struct rte_event_dev_xstats_name *xstat_names,
+ unsigned int *ids, unsigned int size);
+
+uint64_t dlb2_eventdev_xstats_get_by_name(const struct rte_eventdev *dev,
+ const char *name, unsigned int *id);
+
+int dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,
+ enum rte_event_dev_xstats_mode mode,
+ int16_t queue_port_id,
+ const uint32_t ids[],
+ uint32_t nb_ids);
+
+int test_dlb2_eventdev(void);
+
+int dlb2_primary_eventdev_probe(struct rte_eventdev *dev,
+ const char *name,
+ struct dlb2_devargs *dlb2_args);
+
+int dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,
+ const char *name);
+
+uint32_t dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,
+ struct dlb2_eventdev_queue *queue);
+
+/* arg parsing helper functions */
+int dlb2_parse_params(const char *params,
+ const char *name,
+ struct dlb2_devargs *dlb2_args);
+
+int dlb2_string_to_int(int *result, const char *str);
+#endif /* _DLB2_PRIV_H_ */
diff --git a/drivers/event/dlb2/rte_pmd_dlb2.h b/drivers/event/dlb2/rte_pmd_dlb2.h
new file mode 100644
index 0000000..ff914af
--- /dev/null
+++ b/drivers/event/dlb2/rte_pmd_dlb2.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+
+#ifndef _RTE_PMD_DLB2_H_
+#define _RTE_PMD_DLB2_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * Selects the token pop mode for a DLB2 port.
+ */
+enum dlb2_token_pop_mode {
+ /* Pop the CQ tokens immediately after dequeueing. */
+ AUTO_POP,
+ /* Pop CQ tokens after (dequeue_depth - 1) events are released.
+ * Supported on load-balanced ports only.
+ */
+ DELAYED_POP,
+ /* Pop the CQ tokens during next dequeue operation. */
+ DEFERRED_POP,
+
+ /* NUM_TOKEN_POP_MODES must be last */
+ NUM_TOKEN_POP_MODES
+};
+
+/*!
+ * Configure the token pop mode for a DLB2 port. By default, all ports use
+ * AUTO_POP. This function must be called before calling rte_event_port_setup()
+ * for the port, but after calling rte_event_dev_configure().
+ *
+ * @param dev_id
+ * The identifier of the event device.
+ * @param port_id
+ * The identifier of the event port.
+ * @param mode
+ * The token pop mode.
+ *
+ * @return
+ * - 0: Success
+ * - EINVAL: Invalid dev_id, port_id, or mode
+ * - EINVAL: The DLB2 is not configured, is already running, or the port is
+ * already setup
+ */
+
+int
+rte_pmd_dlb2_set_token_pop_mode(uint8_t dev_id,
+ uint8_t port_id,
+ enum dlb2_token_pop_mode mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PMD_DLB2_H_ */
--
2.6.4
^ permalink raw reply [flat|nested] 366+ messages in thread
* [dpdk-dev] [PATCH 04/22] event/dlb2: add definitions shared with LKM or shared code
2020-09-11 20:26 [dpdk-dev] [PATCH 00/22] Add DLB2 PMD Timothy McDaniel
` (2 preceding siblings ...)
2020-09-11 20:26 ` [dpdk-dev] [PATCH 03/22] event/dlb2: add private data structures and constants Timothy McDaniel
@ 2020-09-11 20:26 ` Timothy McDaniel
2020-10-06 19:26 ` Eads, Gage
2020-09-11 20:26 ` [dpdk-dev] [PATCH 05/22] event/dlb2: add inline functions Timothy McDaniel
` (19 subsequent siblings)
23 siblings, 1 reply; 366+ messages in thread
From: Timothy McDaniel @ 2020-09-11 20:26 UTC (permalink / raw)
Cc: dev, erik.g.carrillo, gage.eads, harry.van.haaren, jerinj
Add headers containing structs and constants shared between
the PMD and the shared code. The term shared code refers to
the code that implements the hardware interface. The shared code
is introduced in the probe patch, and then is extended as
additional eventdev PMD entry points are added to the patchset.
In the case of the bifurcated PMD (to be introduced in the
future), the shared code is contained in the Linux kernel
module itself.
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
drivers/event/dlb2/dlb2_user.h | 883 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 883 insertions(+)
create mode 100644 drivers/event/dlb2/dlb2_user.h
diff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb2/dlb2_user.h
new file mode 100644
index 0000000..1bfec7f
--- /dev/null
+++ b/drivers/event/dlb2/dlb2_user.h
@@ -0,0 +1,883 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016-2020 Intel Corporation
+ */
+
+#ifndef __DLB2_USER_H
+#define __DLB2_USER_H
+
+#define DLB2_MAX_NAME_LEN 64
+
+#include <linux/types.h>
+
+enum dlb2_error {
+ DLB2_ST_SUCCESS = 0,
+ DLB2_ST_NAME_EXISTS,
+ DLB2_ST_DOMAIN_UNAVAILABLE,
+ DLB2_ST_LDB_PORTS_UNAVAILABLE,
+ DLB2_ST_DIR_PORTS_UNAVAILABLE,
+ DLB2_ST_LDB_QUEUES_UNAVAILABLE,
+ DLB2_ST_LDB_CREDITS_UNAVAILABLE,
+ DLB2_ST_DIR_CREDITS_UNAVAILABLE,
+ DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE,
+ DLB2_ST_INVALID_DOMAIN_ID,
+ DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION,
+ DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE,
+ DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE,
+ DLB2_ST_INVALID_LDB_QUEUE_ID,
+ DLB2_ST_INVALID_CQ_DEPTH,
+ DLB2_ST_INVALID_CQ_VIRT_ADDR,
+ DLB2_ST_INVALID_PORT_ID,
+ DLB2_ST_INVALID_QID,
+ DLB2_ST_INVALID_PRIORITY,
+ DLB2_ST_NO_QID_SLOTS_AVAILABLE,
+ DLB2_ST_INVALID_DIR_QUEUE_ID,
+ DLB2_ST_DIR_QUEUES_UNAVAILABLE,
+ DLB2_ST_DOMAIN_NOT_CONFIGURED,
+ DLB2_ST_INTERNAL_ERROR,
+ DLB2_ST_DOMAIN_IN_USE,
+ DLB2_ST_DOMAIN_NOT_FOUND,
+ DLB2_ST_QUEUE_NOT_FOUND,
+ DLB2_ST_DOMAIN_STARTED,
+ DLB2_ST_DOMAIN_NOT_STARTED,
+ DLB2_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES,
+ DLB2_ST_DOMAIN_RESET_FAILED,
+ DLB2_ST_MBOX_ERROR,
+ DLB2_ST_INVALID_HIST_LIST_DEPTH,
+ DLB2_ST_NO_MEMORY,
+ DLB2_ST_INVALID_LOCK_ID_COMP_LEVEL,
+ DLB2_ST_INVALID_COS_ID,
+};
+
+static const char dlb2_error_strings[][128] = {
+ "DLB2_ST_SUCCESS",
+ "DLB2_ST_NAME_EXISTS",
+ "DLB2_ST_DOMAIN_UNAVAILABLE",
+ "DLB2_ST_LDB_PORTS_UNAVAILABLE",
+ "DLB2_ST_DIR_PORTS_UNAVAILABLE",
+ "DLB2_ST_LDB_QUEUES_UNAVAILABLE",
+ "DLB2_ST_LDB_CREDITS_UNAVAILABLE",
+ "DLB2_ST_DIR_CREDITS_UNAVAILABLE",
+ "DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE",
+ "DLB2_ST_INVALID_DOMAIN_ID",
+ "DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION",
+ "DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE",
+ "DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE",
+ "DLB2_ST_INVALID_LDB_QUEUE_ID",
+ "DLB2_ST_INVALID_CQ_DEPTH",
+ "DLB2_ST_INVALID_CQ_VIRT_ADDR",
+ "DLB2_ST_INVALID_PORT_ID",
+ "DLB2_ST_INVALID_QID",
+ "DLB2_ST_INVALID_PRIORITY",
+ "DLB2_ST_NO_QID_SLOTS_AVAILABLE",
+ "DLB2_ST_INVALID_DIR_QUEUE_ID",
+ "DLB2_ST_DIR_QUEUES_UNAVAILABLE",
+ "DLB2_ST_DOMAIN_NOT_CONFIGURED",
+ "DLB2_ST_INTERNAL_ERROR",
+ "DLB2_ST_DOMAIN_IN_USE",
+ "DLB2_ST_DOMAIN_NOT_FOUND",
+ "DLB2_ST_QUEUE_NOT_FOUND",
+ "DLB2_ST_DOMAIN_STARTED",
+ "DLB2_ST_DOMAIN_NOT_STARTED",
+ "DLB2_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES",
+ "DLB2_ST_DOMAIN_RESET_FAILED",
+ "DLB2_ST_MBOX_ERROR",
+ "DLB2_ST_INVALID_HIST_LIST_DEPTH",
+ "DLB2_ST_NO_MEMORY",
+ "DLB2_ST_INVALID_LOCK_ID_COMP_LEVEL",
+ "DLB2_ST_INVALID_COS_ID",
+};
+
+struct dlb2_cmd_response {
+ __u32 status; /* Interpret using enum dlb2_error */
+ __u32 id;
+};
+
+/********************************/
+/* 'dlb2' device file commands */
+/********************************/
+
+#define DLB2_DEVICE_VERSION(x) (((x) >> 8) & 0xFF)
+#define DLB2_DEVICE_REVISION(x) ((x) & 0xFF)
+
+enum dlb2_revisions {
+ DLB2_REV_A0 = 0,
+};
+
+/*
+ * DLB2_CMD_GET_DEVICE_VERSION: Query the DLB device version.
+ *
+ * This ioctl interface is the same in all driver versions and is always
+ * the first ioctl.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id[7:0]: Device revision.
+ * - response.id[15:8]: Device version.
+ */
+
+struct dlb2_get_device_version_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+};
+
+/*
+ * DLB2_CMD_CREATE_SCHED_DOMAIN: Create a DLB 2.0 scheduling domain and reserve
+ * its hardware resources. This command returns the newly created domain
+ * ID and a file descriptor for accessing the domain.
+ *
+ * Input parameters:
+ * - num_ldb_queues: Number of load-balanced queues.
+ * - num_ldb_ports: Number of load-balanced ports that can be allocated from
+ * from any class-of-service with available ports.
+ * - num_cos_ldb_ports[4]: Number of load-balanced ports from
+ * classes-of-service 0-3.
+ * - num_dir_ports: Number of directed ports. A directed port has one directed
+ * queue, so no num_dir_queues argument is necessary.
+ * - num_atomic_inflights: This specifies the amount of temporary atomic QE
+ * storage for the domain. This storage is divided among the domain's
+ * load-balanced queues that are configured for atomic scheduling.
+ * - num_hist_list_entries: Amount of history list storage. This is divided
+ * among the domain's CQs.
+ * - num_ldb_credits: Amount of load-balanced QE storage (QED). QEs occupy this
+ * space until they are scheduled to a load-balanced CQ. One credit
+ * represents the storage for one QE.
+ * - num_dir_credits: Amount of directed QE storage (DQED). QEs occupy this
+ * space until they are scheduled to a directed CQ. One credit represents
+ * the storage for one QE.
+ * - cos_strict: If set, return an error if there are insufficient ports in
+ * class-of-service N to satisfy the num_ldb_ports_cosN argument. If
+ * unset, attempt to fulfill num_ldb_ports_cosN arguments from other
+ * classes-of-service if class N does not contain enough free ports.
+ * - padding1: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: domain ID.
+ * - domain_fd: file descriptor for performing the domain's ioctl operations
+ * - padding0: Reserved for future use.
+ */
+struct dlb2_create_sched_domain_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ __u32 domain_fd;
+ __u32 padding0;
+ /* Input parameters */
+ __u32 num_ldb_queues;
+ __u32 num_ldb_ports;
+ __u32 num_cos_ldb_ports[4];
+ __u32 num_dir_ports;
+ __u32 num_atomic_inflights;
+ __u32 num_hist_list_entries;
+ __u32 num_ldb_credits;
+ __u32 num_dir_credits;
+ __u8 cos_strict;
+ __u8 padding1[3];
+};
+
+/*
+ * DLB2_CMD_GET_NUM_RESOURCES: Return the number of available resources
+ * (queues, ports, etc.) that this device owns.
+ *
+ * Output parameters:
+ * - num_domains: Number of available scheduling domains.
+ * - num_ldb_queues: Number of available load-balanced queues.
+ * - num_ldb_ports: Total number of available load-balanced ports.
+ * - num_cos_ldb_ports[4]: Number of available load-balanced ports from
+ * classes-of-service 0-3.
+ * - num_dir_ports: Number of available directed ports. There is one directed
+ * queue for every directed port.
+ * - num_atomic_inflights: Amount of available temporary atomic QE storage.
+ * - num_hist_list_entries: Amount of history list storage.
+ * - max_contiguous_hist_list_entries: History list storage is allocated in
+ * a contiguous chunk, and this return value is the longest available
+ * contiguous range of history list entries.
+ * - num_ldb_credits: Amount of available load-balanced QE storage.
+ * - num_dir_credits: Amount of available directed QE storage.
+ */
+struct dlb2_get_num_resources_args {
+ /* Output parameters */
+ __u32 num_sched_domains;
+ __u32 num_ldb_queues;
+ __u32 num_ldb_ports;
+ __u32 num_cos_ldb_ports[4];
+ __u32 num_dir_ports;
+ __u32 num_atomic_inflights;
+ __u32 num_hist_list_entries;
+ __u32 max_contiguous_hist_list_entries;
+ __u32 num_ldb_credits;
+ __u32 num_dir_credits;
+};
+
+/*
+ * DLB2_CMD_SET_SN_ALLOCATION: Configure a sequence number group (PF only)
+ *
+ * Input parameters:
+ * - group: Sequence number group ID.
+ * - num: Number of sequence numbers per queue.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_set_sn_allocation_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 group;
+ __u32 num;
+};
+
+/*
+ * DLB2_CMD_GET_SN_ALLOCATION: Get a sequence number group's configuration
+ *
+ * Input parameters:
+ * - group: Sequence number group ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: Specified group's number of sequence numbers per queue.
+ */
+struct dlb2_get_sn_allocation_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 group;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_CMD_SET_COS_BW: Set a bandwidth allocation percentage for a
+ * load-balanced port class-of-service (PF only).
+ *
+ * Input parameters:
+ * - cos_id: class-of-service ID, between 0 and 3 (inclusive).
+ * - bandwidth: class-of-service bandwidth percentage. Total bandwidth
+ * percentages across all 4 classes cannot exceed 100%.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_set_cos_bw_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 cos_id;
+ __u32 bandwidth;
+};
+
+/*
+ * DLB2_CMD_GET_COS_BW: Get the bandwidth allocation percentage for a
+ * load-balanced port class-of-service.
+ *
+ * Input parameters:
+ * - cos_id: class-of-service ID, between 0 and 3 (inclusive).
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: Specified class's bandwidth percentage.
+ */
+struct dlb2_get_cos_bw_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 cos_id;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_CMD_GET_SN_OCCUPANCY: Get a sequence number group's occupancy
+ *
+ * Each sequence number group has one or more slots, depending on its
+ * configuration. I.e.:
+ * - If configured for 1024 sequence numbers per queue, the group has 1 slot
+ * - If configured for 512 sequence numbers per queue, the group has 2 slots
+ * ...
+ * - If configured for 32 sequence numbers per queue, the group has 32 slots
+ *
+ * This ioctl returns the group's number of in-use slots. If its occupancy is
+ * 0, the group's sequence number allocation can be reconfigured.
+ *
+ * Input parameters:
+ * - group: Sequence number group ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: Specified group's number of used slots.
+ */
+struct dlb2_get_sn_occupancy_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 group;
+ __u32 padding0;
+};
+
+enum dlb2_cq_poll_modes {
+ DLB2_CQ_POLL_MODE_STD,
+ DLB2_CQ_POLL_MODE_SPARSE,
+
+ /* NUM_DLB2_CQ_POLL_MODE must be last */
+ NUM_DLB2_CQ_POLL_MODE,
+};
+
+/*
+ * DLB2_CMD_QUERY_CQ_POLL_MODE: Query the CQ poll mode setting
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: CQ poll mode (see enum dlb2_cq_poll_modes).
+ */
+struct dlb2_query_cq_poll_mode_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+};
+
+enum dlb2_user_interface_commands {
+ DLB2_CMD_GET_DEVICE_VERSION,
+ DLB2_CMD_CREATE_SCHED_DOMAIN,
+ DLB2_CMD_GET_NUM_RESOURCES,
+ DLB2_CMD_SET_SN_ALLOCATION,
+ DLB2_CMD_GET_SN_ALLOCATION,
+ DLB2_CMD_SET_COS_BW,
+ DLB2_CMD_GET_COS_BW,
+ DLB2_CMD_GET_SN_OCCUPANCY,
+ DLB2_CMD_QUERY_CQ_POLL_MODE,
+
+ /* NUM_DLB2_CMD must be last */
+ NUM_DLB2_CMD,
+};
+
+/*******************************/
+/* 'domain' device file alerts */
+/*******************************/
+
+/*
+ * Scheduling domain device files can be read to receive domain-specific
+ * notifications, for alerts such as hardware errors or device reset.
+ *
+ * Each alert is encoded in a 16B message. The first 8B contains the alert ID,
+ * and the second 8B is optional and contains additional information.
+ * Applications should cast read data to a struct dlb2_domain_alert, and
+ * interpret the struct's alert_id according to dlb2_domain_alert_id. The read
+ * length must be 16B, or the function will return -EINVAL.
+ *
+ * Reads are destructive, and in the case of multiple file descriptors for the
+ * same domain device file, an alert will be read by only one of the file
+ * descriptors.
+ *
+ * The driver stores alerts in a fixed-size alert ring until they are read. If
+ * the alert ring fills completely, subsequent alerts will be dropped. It is
+ * recommended that DLB2 applications dedicate a thread to perform blocking
+ * reads on the device file.
+ */
+enum dlb2_domain_alert_id {
+ /*
+ * Software issued an illegal enqueue for a port in this domain. An
+ * illegal enqueue could be:
+ * - Illegal (excess) completion
+ * - Illegal fragment
+ * - Insufficient credits
+ * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]
+ * contains a flag indicating whether the port is load-balanced (1) or
+ * directed (0).
+ */
+ DLB2_DOMAIN_ALERT_PP_ILLEGAL_ENQ,
+ /*
+ * Software issued excess CQ token pops for a port in this domain.
+ * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]
+ * contains a flag indicating whether the port is load-balanced (1) or
+ * directed (0).
+ */
+ DLB2_DOMAIN_ALERT_PP_EXCESS_TOKEN_POPS,
+ /*
+ * A enqueue contained either an invalid command encoding or a REL,
+ * REL_T, RLS, FWD, FWD_T, FRAG, or FRAG_T from a directed port.
+ *
+ * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]
+ * contains a flag indicating whether the port is load-balanced (1) or
+ * directed (0).
+ */
+ DLB2_DOMAIN_ALERT_ILLEGAL_HCW,
+ /*
+ * The QID must be valid and less than 128.
+ *
+ * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]
+ * contains a flag indicating whether the port is load-balanced (1) or
+ * directed (0).
+ */
+ DLB2_DOMAIN_ALERT_ILLEGAL_QID,
+ /*
+ * An enqueue went to a disabled QID.
+ *
+ * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]
+ * contains a flag indicating whether the port is load-balanced (1) or
+ * directed (0).
+ */
+ DLB2_DOMAIN_ALERT_DISABLED_QID,
+ /*
+ * The device containing this domain was reset. All applications using
+ * the device need to exit for the driver to complete the reset
+ * procedure.
+ *
+ * aux_alert_data doesn't contain any information for this alert.
+ */
+ DLB2_DOMAIN_ALERT_DEVICE_RESET,
+ /*
+ * User-space has enqueued an alert.
+ *
+ * aux_alert_data contains user-provided data.
+ */
+ DLB2_DOMAIN_ALERT_USER,
+ /*
+ * The watchdog timer fired for the specified port. This occurs if its
+ * CQ was not serviced for a large amount of time, likely indicating a
+ * hung thread.
+ * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]
+ * contains a flag indicating whether the port is load-balanced (1) or
+ * directed (0).
+ */
+ DLB2_DOMAIN_ALERT_CQ_WATCHDOG_TIMEOUT,
+
+ /* Number of DLB2 domain alerts */
+ NUM_DLB2_DOMAIN_ALERTS
+};
+
+static const char dlb2_domain_alert_strings[][128] = {
+ "DLB2_DOMAIN_ALERT_PP_ILLEGAL_ENQ",
+ "DLB2_DOMAIN_ALERT_PP_EXCESS_TOKEN_POPS",
+ "DLB2_DOMAIN_ALERT_ILLEGAL_HCW",
+ "DLB2_DOMAIN_ALERT_ILLEGAL_QID",
+ "DLB2_DOMAIN_ALERT_DISABLED_QID",
+ "DLB2_DOMAIN_ALERT_DEVICE_RESET",
+ "DLB2_DOMAIN_ALERT_USER",
+ "DLB2_DOMAIN_ALERT_CQ_WATCHDOG_TIMEOUT",
+};
+
+struct dlb2_domain_alert {
+ __u64 alert_id;
+ __u64 aux_alert_data;
+};
+
+/*********************************/
+/* 'domain' device file commands */
+/*********************************/
+
+/*
+ * DLB2_DOMAIN_CMD_CREATE_LDB_QUEUE: Configure a load-balanced queue.
+ * Input parameters:
+ * - num_atomic_inflights: This specifies the amount of temporary atomic QE
+ * storage for this queue. If zero, the queue will not support atomic
+ * scheduling.
+ * - num_sequence_numbers: This specifies the number of sequence numbers used
+ * by this queue. If zero, the queue will not support ordered scheduling.
+ * If non-zero, the queue will not support unordered scheduling.
+ * - num_qid_inflights: The maximum number of QEs that can be inflight
+ * (scheduled to a CQ but not completed) at any time. If
+ * num_sequence_numbers is non-zero, num_qid_inflights must be set equal
+ * to num_sequence_numbers.
+ * - lock_id_comp_level: Lock ID compression level. Specifies the number of
+ * unique lock IDs the queue should compress down to. Valid compression
+ * levels: 0, 64, 128, 256, 512, 1k, 2k, 4k, 64k. If lock_id_comp_level is
+ * 0, the queue won't compress its lock IDs.
+ * - depth_threshold: DLB sets two bits in the received QE to indicate the
+ * depth of the queue relative to the threshold before scheduling the
+ * QE to a CQ:
+ * - 2’b11: depth > threshold
+ * - 2’b10: threshold >= depth > 0.75 * threshold
+ * - 2’b01: 0.75 * threshold >= depth > 0.5 * threshold
+ * - 2’b00: depth <= 0.5 * threshold
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: Queue ID.
+ */
+struct dlb2_create_ldb_queue_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 num_sequence_numbers;
+ __u32 num_qid_inflights;
+ __u32 num_atomic_inflights;
+ __u32 lock_id_comp_level;
+ __u32 depth_threshold;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_CREATE_DIR_QUEUE: Configure a directed queue.
+ * Input parameters:
+ * - port_id: Port ID. If the corresponding directed port is already created,
+ * specify its ID here. Else this argument must be 0xFFFFFFFF to indicate
+ * that the queue is being created before the port.
+ * - depth_threshold: DLB sets two bits in the received QE to indicate the
+ * depth of the queue relative to the threshold before scheduling the
+ * QE to a CQ:
+ * - 2’b11: depth > threshold
+ * - 2’b10: threshold >= depth > 0.75 * threshold
+ * - 2’b01: 0.75 * threshold >= depth > 0.5 * threshold
+ * - 2’b00: depth <= 0.5 * threshold
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: Queue ID.
+ */
+struct dlb2_create_dir_queue_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __s32 port_id;
+ __u32 depth_threshold;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_CREATE_LDB_PORT: Configure a load-balanced port.
+ * Input parameters:
+ * - cq_depth: Depth of the port's CQ. Must be a power-of-two between 8 and
+ * 1024, inclusive.
+ * - cq_depth_threshold: CQ depth interrupt threshold. A value of N means that
+ * the CQ interrupt won't fire until there are N or more outstanding CQ
+ * tokens.
+ * - num_hist_list_entries: Number of history list entries. This must be
+ * greater than or equal cq_depth.
+ * - cos_id: class-of-service to allocate this port from. Must be between 0 and
+ * 3, inclusive.
+ * - cos_strict: If set, return an error if there are no available ports in the
+ * requested class-of-service. Else, allocate the port from a different
+ * class-of-service if the requested class has no available ports.
+ *
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: port ID.
+ */
+
+struct dlb2_create_ldb_port_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u16 cq_depth;
+ __u16 cq_depth_threshold;
+ __u16 cq_history_list_size;
+ __u8 cos_id;
+ __u8 cos_strict;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_CREATE_DIR_PORT: Configure a directed port.
+ * Input parameters:
+ * - cq_depth: Depth of the port's CQ. Must be a power-of-two between 8 and
+ * 1024, inclusive.
+ * - cq_depth_threshold: CQ depth interrupt threshold. A value of N means that
+ * the CQ interrupt won't fire until there are N or more outstanding CQ
+ * tokens.
+ * - qid: Queue ID. If the corresponding directed queue is already created,
+ * specify its ID here. Else this argument must be 0xFFFFFFFF to indicate
+ * that the port is being created before the queue.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: Port ID.
+ */
+struct dlb2_create_dir_port_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u16 cq_depth;
+ __u16 cq_depth_threshold;
+ __s32 queue_id;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_START_DOMAIN: Mark the end of the domain configuration. This
+ * must be called before passing QEs into the device, and no configuration
+ * ioctls can be issued once the domain has started. Sending QEs into the
+ * device before calling this ioctl will result in undefined behavior.
+ * Input parameters:
+ * - (None)
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_start_domain_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_MAP_QID: Map a load-balanced queue to a load-balanced port.
+ * Input parameters:
+ * - port_id: Load-balanced port ID.
+ * - qid: Load-balanced queue ID.
+ * - priority: Queue->port service priority.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_map_qid_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+ __u32 qid;
+ __u32 priority;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_UNMAP_QID: Unmap a load-balanced queue to a load-balanced
+ * port.
+ * Input parameters:
+ * - port_id: Load-balanced port ID.
+ * - qid: Load-balanced queue ID.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_unmap_qid_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+ __u32 qid;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_ENABLE_LDB_PORT: Enable scheduling to a load-balanced port.
+ * Input parameters:
+ * - port_id: Load-balanced port ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_enable_ldb_port_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_ENABLE_DIR_PORT: Enable scheduling to a directed port.
+ * Input parameters:
+ * - port_id: Directed port ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_enable_dir_port_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_DISABLE_LDB_PORT: Disable scheduling to a load-balanced
+ * port.
+ * Input parameters:
+ * - port_id: Load-balanced port ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_disable_ldb_port_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_DISABLE_DIR_PORT: Disable scheduling to a directed port.
+ * Input parameters:
+ * - port_id: Directed port ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_disable_dir_port_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_ENQUEUE_DOMAIN_ALERT: Enqueue a domain alert that will be
+ * read by one reader thread.
+ *
+ * Input parameters:
+ * - aux_alert_data: user-defined auxiliary data.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ */
+struct dlb2_enqueue_domain_alert_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u64 aux_alert_data;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_GET_LDB_QUEUE_DEPTH: Get a load-balanced queue's depth.
+ * Input parameters:
+ * - queue_id: The load-balanced queue ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: queue depth.
+ */
+struct dlb2_get_ldb_queue_depth_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 queue_id;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_DIR_QUEUE_DEPTH: Get a directed queue's depth.
+ * Input parameters:
+ * - queue_id: The directed queue ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: queue depth.
+ */
+struct dlb2_get_dir_queue_depth_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 queue_id;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_DOMAIN_CMD_PENDING_PORT_UNMAPS: Get number of queue unmap operations in
+ * progress for a load-balanced port.
+ *
+ * Note: This is a snapshot; the number of unmap operations in progress
+ * is subject to change at any time.
+ *
+ * Input parameters:
+ * - port_id: Load-balanced port ID.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: number of unmaps in progress.
+ */
+struct dlb2_pending_port_unmaps_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+ __u32 padding0;
+};
+
+/*
+ * DLB2_CMD_GET_LDB_PORT_PP_FD: Get file descriptor to mmap a load-balanced
+ * port's producer port (PP).
+ * DLB2_CMD_GET_LDB_PORT_CQ_FD: Get file descriptor to mmap a load-balanced
+ * port's consumer queue (CQ).
+ *
+ * The load-balanced port must have been previously created with the ioctl
+ * DLB2_CMD_CREATE_LDB_PORT. The fd is used to mmap the PP/CQ region.
+ *
+ * DLB2_CMD_GET_DIR_PORT_PP_FD: Get file descriptor to mmap a directed port's
+ * producer port (PP).
+ * DLB2_CMD_GET_DIR_PORT_CQ_FD: Get file descriptor to mmap a directed port's
+ * consumer queue (CQ).
+ *
+ * The directed port must have been previously created with the ioctl
+ * DLB2_CMD_CREATE_DIR_PORT. The fd is used to mmap PP/CQ region.
+ *
+ * Input parameters:
+ * - port_id: port ID.
+ * - padding0: Reserved for future use.
+ *
+ * Output parameters:
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
+ * - response.id: fd.
+ */
+struct dlb2_get_port_fd_args {
+ /* Output parameters */
+ struct dlb2_cmd_response response;
+ /* Input parameters */
+ __u32 port_id;
+ __u32 padding0;
+};
+
+enum dlb2_domain_user_interface_commands {
+ DLB2_DOMAIN_CMD_CREATE_LDB_QUEUE,
+ DLB2_DOMAIN_CMD_CREATE_DIR_QUEUE,
+ DLB2_DOMAIN_CMD_CREATE_LDB_PORT,
+ DLB2_DOMAIN_CMD_CREATE_DIR_PORT,
+ DLB2_DOMAIN_CMD_START_DOMAIN,
+ DLB2_DOMAIN_CMD_MAP_QID,
+ DLB2_DOMAIN_CMD_UNMAP_QID,
+ DLB2_DOMAIN_CMD_ENABLE_LDB_PORT,
+ DLB2_DOMAIN_CMD_ENABLE_DIR_PORT,
+ DLB2_DOMAIN_CMD_DISABLE_LDB_PORT,
+ DLB2_DOMAIN_CMD_DISABLE_DIR_PORT,
+ DLB2_DOMAIN_CMD_BLOCK_ON_CQ_INTERRUPT,
+ DLB2_DOMAIN_CMD_ENQUEUE_DOMAIN_ALERT,
+ DLB2_DOMAIN_CMD_GET_LDB_QUEUE_DEPTH,
+ DLB2_DOMAIN_CMD_GET_DIR_QUEUE_DEPTH,
+ DLB2_DOMAIN_CMD_PENDING_PORT_UNMAPS,
+ DLB2_DOMAIN_CMD_GET_LDB_PORT_PP_FD,
+ DLB2_DOMAIN_CMD_GET_LDB_PORT_CQ_FD,
+ DLB2_DOMAIN_CMD_GET_DIR_PORT_PP_FD,
+ DLB2_DOMAIN_CMD_GET_DIR_PORT_CQ_FD,
+
+ /* NUM_DLB2_DOMAIN_CMD must be last */
+ NUM_DLB2_DOMAIN_CMD,
+};
+
+/*
+ * Mapping sizes for memory mapping the consumer queue (CQ) memory space, and
+ * producer port (PP) MMIO space.
+ */
+#define DLB2_CQ_SIZE 65536
+#define DLB2_PP_SIZE 4096
+
+
+#endif /* __DLB2_USER_H */
--
2.6.4